1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MMSCH_V4_0_H__ 25 #define __MMSCH_V4_0_H__ 26 27 #include "amdgpu_vcn.h" 28 29 #define MMSCH_VERSION_MAJOR 4 30 #define MMSCH_VERSION_MINOR 0 31 #define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR) 32 33 #define RB_ENABLED (1 << 0) 34 #define RB4_ENABLED (1 << 1) 35 36 #define MMSCH_VF_ENGINE_STATUS__PASS 0x1 37 38 #define MMSCH_VF_MAILBOX_RESP__OK 0x1 39 #define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2 40 41 enum mmsch_v4_0_command_type { 42 MMSCH_COMMAND__DIRECT_REG_WRITE = 0, 43 MMSCH_COMMAND__DIRECT_REG_POLLING = 2, 44 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3, 45 MMSCH_COMMAND__INDIRECT_REG_WRITE = 8, 46 MMSCH_COMMAND__END = 0xf 47 }; 48 49 struct mmsch_v4_0_table_info { 50 uint32_t init_status; 51 uint32_t table_offset; 52 uint32_t table_size; 53 }; 54 55 struct mmsch_v4_0_init_header { 56 uint32_t version; 57 uint32_t total_size; 58 struct mmsch_v4_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES]; 59 struct mmsch_v4_0_table_info jpegdec; 60 }; 61 62 struct mmsch_v4_0_cmd_direct_reg_header { 63 uint32_t reg_offset : 28; 64 uint32_t command_type : 4; 65 }; 66 67 struct mmsch_v4_0_cmd_indirect_reg_header { 68 uint32_t reg_offset : 20; 69 uint32_t reg_idx_space : 8; 70 uint32_t command_type : 4; 71 }; 72 73 struct mmsch_v4_0_cmd_direct_write { 74 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 75 uint32_t reg_value; 76 }; 77 78 struct mmsch_v4_0_cmd_direct_read_modify_write { 79 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 80 uint32_t write_data; 81 uint32_t mask_value; 82 }; 83 84 struct mmsch_v4_0_cmd_direct_polling { 85 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 86 uint32_t mask_value; 87 uint32_t wait_value; 88 }; 89 90 struct mmsch_v4_0_cmd_end { 91 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 92 }; 93 94 struct mmsch_v4_0_cmd_indirect_write { 95 struct mmsch_v4_0_cmd_indirect_reg_header cmd_header; 96 uint32_t reg_value; 97 }; 98 99 #define MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ 100 size = sizeof(struct mmsch_v4_0_cmd_direct_read_modify_write); \ 101 size_dw = size / 4; \ 102 direct_rd_mod_wt.cmd_header.reg_offset = reg; \ 103 direct_rd_mod_wt.mask_value = mask; \ 104 direct_rd_mod_wt.write_data = data; \ 105 memcpy((void *)table_loc, &direct_rd_mod_wt, size); \ 106 table_loc += size_dw; \ 107 table_size += size_dw; \ 108 } 109 110 #define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \ 111 size = sizeof(struct mmsch_v4_0_cmd_direct_write); \ 112 size_dw = size / 4; \ 113 direct_wt.cmd_header.reg_offset = reg; \ 114 direct_wt.reg_value = value; \ 115 memcpy((void *)table_loc, &direct_wt, size); \ 116 table_loc += size_dw; \ 117 table_size += size_dw; \ 118 } 119 120 #define MMSCH_V4_0_INSERT_DIRECT_POLL(reg, mask, wait) { \ 121 size = sizeof(struct mmsch_v4_0_cmd_direct_polling); \ 122 size_dw = size / 4; \ 123 direct_poll.cmd_header.reg_offset = reg; \ 124 direct_poll.mask_value = mask; \ 125 direct_poll.wait_value = wait; \ 126 memcpy((void *)table_loc, &direct_poll, size); \ 127 table_loc += size_dw; \ 128 table_size += size_dw; \ 129 } 130 131 #define MMSCH_V4_0_INSERT_END() { \ 132 size = sizeof(struct mmsch_v4_0_cmd_end); \ 133 size_dw = size / 4; \ 134 memcpy((void *)table_loc, &end, size); \ 135 table_loc += size_dw; \ 136 table_size += size_dw; \ 137 } 138 139 #endif 140