1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/module.h>
33 #include <linux/oom.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/string_helpers.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42
43 #include <drm/drm_aperture.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_ioctl.h>
46 #include <drm/drm_managed.h>
47 #include <drm/drm_probe_helper.h>
48
49 #include "display/intel_acpi.h"
50 #include "display/intel_bw.h"
51 #include "display/intel_cdclk.h"
52 #include "display/intel_display_types.h"
53 #include "display/intel_dmc.h"
54 #include "display/intel_dp.h"
55 #include "display/intel_dpt.h"
56 #include "display/intel_fbdev.h"
57 #include "display/intel_hotplug.h"
58 #include "display/intel_overlay.h"
59 #include "display/intel_pch_refclk.h"
60 #include "display/intel_pipe_crc.h"
61 #include "display/intel_pps.h"
62 #include "display/intel_sprite.h"
63 #include "display/intel_vga.h"
64 #include "display/skl_watermark.h"
65
66 #include "gem/i915_gem_context.h"
67 #include "gem/i915_gem_create.h"
68 #include "gem/i915_gem_dmabuf.h"
69 #include "gem/i915_gem_ioctls.h"
70 #include "gem/i915_gem_mman.h"
71 #include "gem/i915_gem_pm.h"
72 #include "gt/intel_gt.h"
73 #include "gt/intel_gt_pm.h"
74 #include "gt/intel_rc6.h"
75
76 #include "pxp/intel_pxp_pm.h"
77
78 #include "i915_file_private.h"
79 #include "i915_debugfs.h"
80 #include "i915_driver.h"
81 #include "i915_drm_client.h"
82 #include "i915_drv.h"
83 #include "i915_getparam.h"
84 #include "i915_ioc32.h"
85 #include "i915_ioctl.h"
86 #include "i915_irq.h"
87 #include "i915_memcpy.h"
88 #include "i915_perf.h"
89 #include "i915_query.h"
90 #include "i915_suspend.h"
91 #include "i915_switcheroo.h"
92 #include "i915_sysfs.h"
93 #include "i915_utils.h"
94 #include "i915_vgpu.h"
95 #include "intel_dram.h"
96 #include "intel_gvt.h"
97 #include "intel_memory_region.h"
98 #include "intel_pci_config.h"
99 #include "intel_pcode.h"
100 #include "intel_pm.h"
101 #include "intel_region_ttm.h"
102 #include "vlv_suspend.h"
103
104 /* Intel Rapid Start Technology ACPI device name */
105 static const char irst_name[] = "INT3392";
106
107 static const struct drm_driver i915_drm_driver;
108
i915_release_bridge_dev(struct drm_device * dev,void * bridge)109 static void i915_release_bridge_dev(struct drm_device *dev,
110 void *bridge)
111 {
112 pci_dev_put(bridge);
113 }
114
i915_get_bridge_dev(struct drm_i915_private * dev_priv)115 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
116 {
117 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
118
119 dev_priv->bridge_dev =
120 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
121 if (!dev_priv->bridge_dev) {
122 drm_err(&dev_priv->drm, "bridge device not found\n");
123 return -EIO;
124 }
125
126 return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev,
127 dev_priv->bridge_dev);
128 }
129
130 /* Allocate space for the MCH regs if needed, return nonzero on error */
131 static int
intel_alloc_mchbar_resource(struct drm_i915_private * dev_priv)132 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
133 {
134 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
135 u32 temp_lo, temp_hi = 0;
136 u64 mchbar_addr;
137 int ret;
138
139 if (GRAPHICS_VER(dev_priv) >= 4)
140 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
141 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
142 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
143
144 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
145 #ifdef CONFIG_PNP
146 if (mchbar_addr &&
147 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
148 return 0;
149 #endif
150
151 /* Get some space for it */
152 dev_priv->mch_res.name = "i915 MCHBAR";
153 dev_priv->mch_res.flags = IORESOURCE_MEM;
154 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
155 &dev_priv->mch_res,
156 MCHBAR_SIZE, MCHBAR_SIZE,
157 PCIBIOS_MIN_MEM,
158 0, pcibios_align_resource,
159 dev_priv->bridge_dev);
160 if (ret) {
161 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
162 dev_priv->mch_res.start = 0;
163 return ret;
164 }
165
166 if (GRAPHICS_VER(dev_priv) >= 4)
167 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
168 upper_32_bits(dev_priv->mch_res.start));
169
170 pci_write_config_dword(dev_priv->bridge_dev, reg,
171 lower_32_bits(dev_priv->mch_res.start));
172 return 0;
173 }
174
175 /* Setup MCHBAR if possible, return true if we should disable it again */
176 static void
intel_setup_mchbar(struct drm_i915_private * dev_priv)177 intel_setup_mchbar(struct drm_i915_private *dev_priv)
178 {
179 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
180 u32 temp;
181 bool enabled;
182
183 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
184 return;
185
186 dev_priv->mchbar_need_disable = false;
187
188 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
189 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
190 enabled = !!(temp & DEVEN_MCHBAR_EN);
191 } else {
192 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
193 enabled = temp & 1;
194 }
195
196 /* If it's already enabled, don't have to do anything */
197 if (enabled)
198 return;
199
200 if (intel_alloc_mchbar_resource(dev_priv))
201 return;
202
203 dev_priv->mchbar_need_disable = true;
204
205 /* Space is allocated or reserved, so enable it. */
206 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
207 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
208 temp | DEVEN_MCHBAR_EN);
209 } else {
210 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
211 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
212 }
213 }
214
215 static void
intel_teardown_mchbar(struct drm_i915_private * dev_priv)216 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
217 {
218 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
219
220 if (dev_priv->mchbar_need_disable) {
221 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
222 u32 deven_val;
223
224 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
225 &deven_val);
226 deven_val &= ~DEVEN_MCHBAR_EN;
227 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
228 deven_val);
229 } else {
230 u32 mchbar_val;
231
232 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
233 &mchbar_val);
234 mchbar_val &= ~1;
235 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
236 mchbar_val);
237 }
238 }
239
240 if (dev_priv->mch_res.start)
241 release_resource(&dev_priv->mch_res);
242 }
243
i915_workqueues_init(struct drm_i915_private * dev_priv)244 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
245 {
246 /*
247 * The i915 workqueue is primarily used for batched retirement of
248 * requests (and thus managing bo) once the task has been completed
249 * by the GPU. i915_retire_requests() is called directly when we
250 * need high-priority retirement, such as waiting for an explicit
251 * bo.
252 *
253 * It is also used for periodic low-priority events, such as
254 * idle-timers and recording error state.
255 *
256 * All tasks on the workqueue are expected to acquire the dev mutex
257 * so there is no point in running more than one instance of the
258 * workqueue at any time. Use an ordered one.
259 */
260 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
261 if (dev_priv->wq == NULL)
262 goto out_err;
263
264 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
265 if (dev_priv->display.hotplug.dp_wq == NULL)
266 goto out_free_wq;
267
268 return 0;
269
270 out_free_wq:
271 destroy_workqueue(dev_priv->wq);
272 out_err:
273 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
274
275 return -ENOMEM;
276 }
277
i915_workqueues_cleanup(struct drm_i915_private * dev_priv)278 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
279 {
280 destroy_workqueue(dev_priv->display.hotplug.dp_wq);
281 destroy_workqueue(dev_priv->wq);
282 }
283
284 /*
285 * We don't keep the workarounds for pre-production hardware, so we expect our
286 * driver to fail on these machines in one way or another. A little warning on
287 * dmesg may help both the user and the bug triagers.
288 *
289 * Our policy for removing pre-production workarounds is to keep the
290 * current gen workarounds as a guide to the bring-up of the next gen
291 * (workarounds have a habit of persisting!). Anything older than that
292 * should be removed along with the complications they introduce.
293 */
intel_detect_preproduction_hw(struct drm_i915_private * dev_priv)294 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
295 {
296 bool pre = false;
297
298 pre |= IS_HSW_EARLY_SDV(dev_priv);
299 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
300 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
301 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
302 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
303 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
304
305 if (pre) {
306 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
307 "It may not be fully functional.\n");
308 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
309 }
310 }
311
sanitize_gpu(struct drm_i915_private * i915)312 static void sanitize_gpu(struct drm_i915_private *i915)
313 {
314 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
315 struct intel_gt *gt;
316 unsigned int i;
317
318 for_each_gt(gt, i915, i)
319 __intel_gt_reset(gt, ALL_ENGINES);
320 }
321 }
322
323 /**
324 * i915_driver_early_probe - setup state not requiring device access
325 * @dev_priv: device private
326 *
327 * Initialize everything that is a "SW-only" state, that is state not
328 * requiring accessing the device or exposing the driver via kernel internal
329 * or userspace interfaces. Example steps belonging here: lock initialization,
330 * system memory allocation, setting up device specific attributes and
331 * function hooks not requiring accessing the device.
332 */
i915_driver_early_probe(struct drm_i915_private * dev_priv)333 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
334 {
335 int ret = 0;
336
337 if (i915_inject_probe_failure(dev_priv))
338 return -ENODEV;
339
340 intel_device_info_subplatform_init(dev_priv);
341 intel_step_init(dev_priv);
342
343 intel_uncore_mmio_debug_init_early(dev_priv);
344
345 spin_lock_init(&dev_priv->irq_lock);
346 spin_lock_init(&dev_priv->gpu_error.lock);
347 mutex_init(&dev_priv->display.backlight.lock);
348
349 mutex_init(&dev_priv->sb_lock);
350 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
351
352 mutex_init(&dev_priv->display.audio.mutex);
353 mutex_init(&dev_priv->display.wm.wm_mutex);
354 mutex_init(&dev_priv->display.pps.mutex);
355 mutex_init(&dev_priv->display.hdcp.comp_mutex);
356 spin_lock_init(&dev_priv->display.dkl.phy_lock);
357
358 i915_memcpy_init_early(dev_priv);
359 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
360
361 ret = i915_workqueues_init(dev_priv);
362 if (ret < 0)
363 return ret;
364
365 ret = vlv_suspend_init(dev_priv);
366 if (ret < 0)
367 goto err_workqueues;
368
369 ret = intel_region_ttm_device_init(dev_priv);
370 if (ret)
371 goto err_ttm;
372
373 intel_wopcm_init_early(&dev_priv->wopcm);
374
375 ret = intel_root_gt_init_early(dev_priv);
376 if (ret < 0)
377 goto err_rootgt;
378
379 i915_drm_clients_init(&dev_priv->clients, dev_priv);
380
381 i915_gem_init_early(dev_priv);
382
383 /* This must be called before any calls to HAS_PCH_* */
384 intel_detect_pch(dev_priv);
385
386 intel_pm_setup(dev_priv);
387 ret = intel_power_domains_init(dev_priv);
388 if (ret < 0)
389 goto err_gem;
390 intel_irq_init(dev_priv);
391 intel_init_display_hooks(dev_priv);
392 intel_init_clock_gating_hooks(dev_priv);
393
394 intel_detect_preproduction_hw(dev_priv);
395
396 return 0;
397
398 err_gem:
399 i915_gem_cleanup_early(dev_priv);
400 intel_gt_driver_late_release_all(dev_priv);
401 i915_drm_clients_fini(&dev_priv->clients);
402 err_rootgt:
403 intel_region_ttm_device_fini(dev_priv);
404 err_ttm:
405 vlv_suspend_cleanup(dev_priv);
406 err_workqueues:
407 i915_workqueues_cleanup(dev_priv);
408 return ret;
409 }
410
411 /**
412 * i915_driver_late_release - cleanup the setup done in
413 * i915_driver_early_probe()
414 * @dev_priv: device private
415 */
i915_driver_late_release(struct drm_i915_private * dev_priv)416 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
417 {
418 intel_irq_fini(dev_priv);
419 intel_power_domains_cleanup(dev_priv);
420 i915_gem_cleanup_early(dev_priv);
421 intel_gt_driver_late_release_all(dev_priv);
422 i915_drm_clients_fini(&dev_priv->clients);
423 intel_region_ttm_device_fini(dev_priv);
424 vlv_suspend_cleanup(dev_priv);
425 i915_workqueues_cleanup(dev_priv);
426
427 cpu_latency_qos_remove_request(&dev_priv->sb_qos);
428 mutex_destroy(&dev_priv->sb_lock);
429
430 i915_params_free(&dev_priv->params);
431 }
432
433 /**
434 * i915_driver_mmio_probe - setup device MMIO
435 * @dev_priv: device private
436 *
437 * Setup minimal device state necessary for MMIO accesses later in the
438 * initialization sequence. The setup here should avoid any other device-wide
439 * side effects or exposing the driver via kernel internal or user space
440 * interfaces.
441 */
i915_driver_mmio_probe(struct drm_i915_private * dev_priv)442 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
443 {
444 struct intel_gt *gt;
445 int ret, i;
446
447 if (i915_inject_probe_failure(dev_priv))
448 return -ENODEV;
449
450 ret = i915_get_bridge_dev(dev_priv);
451 if (ret < 0)
452 return ret;
453
454 for_each_gt(gt, dev_priv, i) {
455 ret = intel_uncore_init_mmio(gt->uncore);
456 if (ret)
457 return ret;
458
459 ret = drmm_add_action_or_reset(&dev_priv->drm,
460 intel_uncore_fini_mmio,
461 gt->uncore);
462 if (ret)
463 return ret;
464 }
465
466 /* Try to make sure MCHBAR is enabled before poking at it */
467 intel_setup_mchbar(dev_priv);
468 intel_device_info_runtime_init(dev_priv);
469
470 for_each_gt(gt, dev_priv, i) {
471 ret = intel_gt_init_mmio(gt);
472 if (ret)
473 goto err_uncore;
474 }
475
476 /* As early as possible, scrub existing GPU state before clobbering */
477 sanitize_gpu(dev_priv);
478
479 return 0;
480
481 err_uncore:
482 intel_teardown_mchbar(dev_priv);
483
484 return ret;
485 }
486
487 /**
488 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
489 * @dev_priv: device private
490 */
i915_driver_mmio_release(struct drm_i915_private * dev_priv)491 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
492 {
493 intel_teardown_mchbar(dev_priv);
494 }
495
496 /**
497 * i915_set_dma_info - set all relevant PCI dma info as configured for the
498 * platform
499 * @i915: valid i915 instance
500 *
501 * Set the dma max segment size, device and coherent masks. The dma mask set
502 * needs to occur before i915_ggtt_probe_hw.
503 *
504 * A couple of platforms have special needs. Address them as well.
505 *
506 */
i915_set_dma_info(struct drm_i915_private * i915)507 static int i915_set_dma_info(struct drm_i915_private *i915)
508 {
509 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
510 int ret;
511
512 GEM_BUG_ON(!mask_size);
513
514 /*
515 * We don't have a max segment size, so set it to the max so sg's
516 * debugging layer doesn't complain
517 */
518 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
519
520 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
521 if (ret)
522 goto mask_err;
523
524 /* overlay on gen2 is broken and can't address above 1G */
525 if (GRAPHICS_VER(i915) == 2)
526 mask_size = 30;
527
528 /*
529 * 965GM sometimes incorrectly writes to hardware status page (HWS)
530 * using 32bit addressing, overwriting memory if HWS is located
531 * above 4GB.
532 *
533 * The documentation also mentions an issue with undefined
534 * behaviour if any general state is accessed within a page above 4GB,
535 * which also needs to be handled carefully.
536 */
537 if (IS_I965G(i915) || IS_I965GM(i915))
538 mask_size = 32;
539
540 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
541 if (ret)
542 goto mask_err;
543
544 return 0;
545
546 mask_err:
547 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
548 return ret;
549 }
550
i915_pcode_init(struct drm_i915_private * i915)551 static int i915_pcode_init(struct drm_i915_private *i915)
552 {
553 struct intel_gt *gt;
554 int id, ret;
555
556 for_each_gt(gt, i915, id) {
557 ret = intel_pcode_init(gt->uncore);
558 if (ret) {
559 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
560 return ret;
561 }
562 }
563
564 return 0;
565 }
566
567 /**
568 * i915_driver_hw_probe - setup state requiring device access
569 * @dev_priv: device private
570 *
571 * Setup state that requires accessing the device, but doesn't require
572 * exposing the driver via kernel internal or userspace interfaces.
573 */
i915_driver_hw_probe(struct drm_i915_private * dev_priv)574 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
575 {
576 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
577 int ret;
578
579 if (i915_inject_probe_failure(dev_priv))
580 return -ENODEV;
581
582 if (HAS_PPGTT(dev_priv)) {
583 if (intel_vgpu_active(dev_priv) &&
584 !intel_vgpu_has_full_ppgtt(dev_priv)) {
585 i915_report_error(dev_priv,
586 "incompatible vGPU found, support for isolated ppGTT required\n");
587 return -ENXIO;
588 }
589 }
590
591 if (HAS_EXECLISTS(dev_priv)) {
592 /*
593 * Older GVT emulation depends upon intercepting CSB mmio,
594 * which we no longer use, preferring to use the HWSP cache
595 * instead.
596 */
597 if (intel_vgpu_active(dev_priv) &&
598 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
599 i915_report_error(dev_priv,
600 "old vGPU host found, support for HWSP emulation required\n");
601 return -ENXIO;
602 }
603 }
604
605 /* needs to be done before ggtt probe */
606 intel_dram_edram_detect(dev_priv);
607
608 ret = i915_set_dma_info(dev_priv);
609 if (ret)
610 return ret;
611
612 i915_perf_init(dev_priv);
613
614 ret = intel_gt_assign_ggtt(to_gt(dev_priv));
615 if (ret)
616 goto err_perf;
617
618 ret = i915_ggtt_probe_hw(dev_priv);
619 if (ret)
620 goto err_perf;
621
622 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
623 if (ret)
624 goto err_ggtt;
625
626 ret = i915_ggtt_init_hw(dev_priv);
627 if (ret)
628 goto err_ggtt;
629
630 ret = intel_memory_regions_hw_probe(dev_priv);
631 if (ret)
632 goto err_ggtt;
633
634 ret = intel_gt_tiles_init(dev_priv);
635 if (ret)
636 goto err_mem_regions;
637
638 ret = i915_ggtt_enable_hw(dev_priv);
639 if (ret) {
640 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
641 goto err_mem_regions;
642 }
643
644 pci_set_master(pdev);
645
646 /* On the 945G/GM, the chipset reports the MSI capability on the
647 * integrated graphics even though the support isn't actually there
648 * according to the published specs. It doesn't appear to function
649 * correctly in testing on 945G.
650 * This may be a side effect of MSI having been made available for PEG
651 * and the registers being closely associated.
652 *
653 * According to chipset errata, on the 965GM, MSI interrupts may
654 * be lost or delayed, and was defeatured. MSI interrupts seem to
655 * get lost on g4x as well, and interrupt delivery seems to stay
656 * properly dead afterwards. So we'll just disable them for all
657 * pre-gen5 chipsets.
658 *
659 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
660 * interrupts even when in MSI mode. This results in spurious
661 * interrupt warnings if the legacy irq no. is shared with another
662 * device. The kernel then disables that interrupt source and so
663 * prevents the other device from working properly.
664 */
665 if (GRAPHICS_VER(dev_priv) >= 5) {
666 if (pci_enable_msi(pdev) < 0)
667 drm_dbg(&dev_priv->drm, "can't enable MSI");
668 }
669
670 ret = intel_gvt_init(dev_priv);
671 if (ret)
672 goto err_msi;
673
674 intel_opregion_setup(dev_priv);
675
676 ret = i915_pcode_init(dev_priv);
677 if (ret)
678 goto err_msi;
679
680 /*
681 * Fill the dram structure to get the system dram info. This will be
682 * used for memory latency calculation.
683 */
684 intel_dram_detect(dev_priv);
685
686 intel_bw_init_hw(dev_priv);
687
688 return 0;
689
690 err_msi:
691 if (pdev->msi_enabled)
692 pci_disable_msi(pdev);
693 err_mem_regions:
694 intel_memory_regions_driver_release(dev_priv);
695 err_ggtt:
696 i915_ggtt_driver_release(dev_priv);
697 i915_gem_drain_freed_objects(dev_priv);
698 i915_ggtt_driver_late_release(dev_priv);
699 err_perf:
700 i915_perf_fini(dev_priv);
701 return ret;
702 }
703
704 /**
705 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
706 * @dev_priv: device private
707 */
i915_driver_hw_remove(struct drm_i915_private * dev_priv)708 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
709 {
710 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
711
712 i915_perf_fini(dev_priv);
713
714 if (pdev->msi_enabled)
715 pci_disable_msi(pdev);
716 }
717
718 /**
719 * i915_driver_register - register the driver with the rest of the system
720 * @dev_priv: device private
721 *
722 * Perform any steps necessary to make the driver available via kernel
723 * internal or userspace interfaces.
724 */
i915_driver_register(struct drm_i915_private * dev_priv)725 static void i915_driver_register(struct drm_i915_private *dev_priv)
726 {
727 struct drm_device *dev = &dev_priv->drm;
728 struct intel_gt *gt;
729 unsigned int i;
730
731 i915_gem_driver_register(dev_priv);
732 i915_pmu_register(dev_priv);
733
734 intel_vgpu_register(dev_priv);
735
736 /* Reveal our presence to userspace */
737 if (drm_dev_register(dev, 0)) {
738 drm_err(&dev_priv->drm,
739 "Failed to register driver for userspace access!\n");
740 return;
741 }
742
743 i915_debugfs_register(dev_priv);
744 i915_setup_sysfs(dev_priv);
745
746 /* Depends on sysfs having been initialized */
747 i915_perf_register(dev_priv);
748
749 for_each_gt(gt, dev_priv, i)
750 intel_gt_driver_register(gt);
751
752 intel_display_driver_register(dev_priv);
753
754 intel_power_domains_enable(dev_priv);
755 intel_runtime_pm_enable(&dev_priv->runtime_pm);
756
757 intel_register_dsm_handler();
758
759 if (i915_switcheroo_register(dev_priv))
760 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
761 }
762
763 /**
764 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
765 * @dev_priv: device private
766 */
i915_driver_unregister(struct drm_i915_private * dev_priv)767 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
768 {
769 struct intel_gt *gt;
770 unsigned int i;
771
772 i915_switcheroo_unregister(dev_priv);
773
774 intel_unregister_dsm_handler();
775
776 intel_runtime_pm_disable(&dev_priv->runtime_pm);
777 intel_power_domains_disable(dev_priv);
778
779 intel_display_driver_unregister(dev_priv);
780
781 for_each_gt(gt, dev_priv, i)
782 intel_gt_driver_unregister(gt);
783
784 i915_perf_unregister(dev_priv);
785 i915_pmu_unregister(dev_priv);
786
787 i915_teardown_sysfs(dev_priv);
788 drm_dev_unplug(&dev_priv->drm);
789
790 i915_gem_driver_unregister(dev_priv);
791 }
792
793 void
i915_print_iommu_status(struct drm_i915_private * i915,struct drm_printer * p)794 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
795 {
796 drm_printf(p, "iommu: %s\n",
797 str_enabled_disabled(i915_vtd_active(i915)));
798 }
799
i915_welcome_messages(struct drm_i915_private * dev_priv)800 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
801 {
802 if (drm_debug_enabled(DRM_UT_DRIVER)) {
803 struct drm_printer p = drm_debug_printer("i915 device info:");
804 struct intel_gt *gt;
805 unsigned int i;
806
807 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
808 INTEL_DEVID(dev_priv),
809 INTEL_REVID(dev_priv),
810 intel_platform_name(INTEL_INFO(dev_priv)->platform),
811 intel_subplatform(RUNTIME_INFO(dev_priv),
812 INTEL_INFO(dev_priv)->platform),
813 GRAPHICS_VER(dev_priv));
814
815 intel_device_info_print(INTEL_INFO(dev_priv),
816 RUNTIME_INFO(dev_priv), &p);
817 i915_print_iommu_status(dev_priv, &p);
818 for_each_gt(gt, dev_priv, i)
819 intel_gt_info_print(>->info, &p);
820 }
821
822 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
823 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
824 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
825 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
826 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
827 drm_info(&dev_priv->drm,
828 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
829 }
830
831 static struct drm_i915_private *
i915_driver_create(struct pci_dev * pdev,const struct pci_device_id * ent)832 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
833 {
834 const struct intel_device_info *match_info =
835 (struct intel_device_info *)ent->driver_data;
836 struct intel_device_info *device_info;
837 struct intel_runtime_info *runtime;
838 struct drm_i915_private *i915;
839
840 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
841 struct drm_i915_private, drm);
842 if (IS_ERR(i915))
843 return i915;
844
845 pci_set_drvdata(pdev, i915);
846
847 /* Device parameters start as a copy of module parameters. */
848 i915_params_copy(&i915->params, &i915_modparams);
849
850 /* Setup the write-once "constant" device info */
851 device_info = mkwrite_device_info(i915);
852 memcpy(device_info, match_info, sizeof(*device_info));
853
854 /* Initialize initial runtime info from static const data and pdev. */
855 runtime = RUNTIME_INFO(i915);
856 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
857 runtime->device_id = pdev->device;
858
859 return i915;
860 }
861
862 /**
863 * i915_driver_probe - setup chip and create an initial config
864 * @pdev: PCI device
865 * @ent: matching PCI ID entry
866 *
867 * The driver probe routine has to do several things:
868 * - drive output discovery via intel_modeset_init()
869 * - initialize the memory manager
870 * - allocate initial config memory
871 * - setup the DRM framebuffer with the allocated memory
872 */
i915_driver_probe(struct pci_dev * pdev,const struct pci_device_id * ent)873 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
874 {
875 struct drm_i915_private *i915;
876 int ret;
877
878 i915 = i915_driver_create(pdev, ent);
879 if (IS_ERR(i915))
880 return PTR_ERR(i915);
881
882 /* Disable nuclear pageflip by default on pre-ILK */
883 if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5)
884 i915->drm.driver_features &= ~DRIVER_ATOMIC;
885
886 ret = pci_enable_device(pdev);
887 if (ret)
888 goto out_fini;
889
890 ret = i915_driver_early_probe(i915);
891 if (ret < 0)
892 goto out_pci_disable;
893
894 disable_rpm_wakeref_asserts(&i915->runtime_pm);
895
896 intel_vgpu_detect(i915);
897
898 ret = intel_gt_probe_all(i915);
899 if (ret < 0)
900 goto out_runtime_pm_put;
901
902 ret = i915_driver_mmio_probe(i915);
903 if (ret < 0)
904 goto out_runtime_pm_put;
905
906 ret = i915_driver_hw_probe(i915);
907 if (ret < 0)
908 goto out_cleanup_mmio;
909
910 ret = intel_modeset_init_noirq(i915);
911 if (ret < 0)
912 goto out_cleanup_hw;
913
914 ret = intel_irq_install(i915);
915 if (ret)
916 goto out_cleanup_modeset;
917
918 ret = intel_modeset_init_nogem(i915);
919 if (ret)
920 goto out_cleanup_irq;
921
922 ret = i915_gem_init(i915);
923 if (ret)
924 goto out_cleanup_modeset2;
925
926 ret = intel_modeset_init(i915);
927 if (ret)
928 goto out_cleanup_gem;
929
930 i915_driver_register(i915);
931
932 enable_rpm_wakeref_asserts(&i915->runtime_pm);
933
934 i915_welcome_messages(i915);
935
936 i915->do_release = true;
937
938 return 0;
939
940 out_cleanup_gem:
941 i915_gem_suspend(i915);
942 i915_gem_driver_remove(i915);
943 i915_gem_driver_release(i915);
944 out_cleanup_modeset2:
945 /* FIXME clean up the error path */
946 intel_modeset_driver_remove(i915);
947 intel_irq_uninstall(i915);
948 intel_modeset_driver_remove_noirq(i915);
949 goto out_cleanup_modeset;
950 out_cleanup_irq:
951 intel_irq_uninstall(i915);
952 out_cleanup_modeset:
953 intel_modeset_driver_remove_nogem(i915);
954 out_cleanup_hw:
955 i915_driver_hw_remove(i915);
956 intel_memory_regions_driver_release(i915);
957 i915_ggtt_driver_release(i915);
958 i915_gem_drain_freed_objects(i915);
959 i915_ggtt_driver_late_release(i915);
960 out_cleanup_mmio:
961 i915_driver_mmio_release(i915);
962 out_runtime_pm_put:
963 enable_rpm_wakeref_asserts(&i915->runtime_pm);
964 i915_driver_late_release(i915);
965 out_pci_disable:
966 pci_disable_device(pdev);
967 out_fini:
968 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
969 return ret;
970 }
971
i915_driver_remove(struct drm_i915_private * i915)972 void i915_driver_remove(struct drm_i915_private *i915)
973 {
974 intel_wakeref_t wakeref;
975
976 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
977
978 i915_driver_unregister(i915);
979
980 /* Flush any external code that still may be under the RCU lock */
981 synchronize_rcu();
982
983 i915_gem_suspend(i915);
984
985 intel_gvt_driver_remove(i915);
986
987 intel_modeset_driver_remove(i915);
988
989 intel_irq_uninstall(i915);
990
991 intel_modeset_driver_remove_noirq(i915);
992
993 i915_reset_error_state(i915);
994 i915_gem_driver_remove(i915);
995
996 intel_modeset_driver_remove_nogem(i915);
997
998 i915_driver_hw_remove(i915);
999
1000 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1001 }
1002
i915_driver_release(struct drm_device * dev)1003 static void i915_driver_release(struct drm_device *dev)
1004 {
1005 struct drm_i915_private *dev_priv = to_i915(dev);
1006 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1007 intel_wakeref_t wakeref;
1008
1009 if (!dev_priv->do_release)
1010 return;
1011
1012 wakeref = intel_runtime_pm_get(rpm);
1013
1014 i915_gem_driver_release(dev_priv);
1015
1016 intel_memory_regions_driver_release(dev_priv);
1017 i915_ggtt_driver_release(dev_priv);
1018 i915_gem_drain_freed_objects(dev_priv);
1019 i915_ggtt_driver_late_release(dev_priv);
1020
1021 i915_driver_mmio_release(dev_priv);
1022
1023 intel_runtime_pm_put(rpm, wakeref);
1024
1025 intel_runtime_pm_driver_release(rpm);
1026
1027 i915_driver_late_release(dev_priv);
1028 }
1029
i915_driver_open(struct drm_device * dev,struct drm_file * file)1030 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1031 {
1032 struct drm_i915_private *i915 = to_i915(dev);
1033 int ret;
1034
1035 ret = i915_gem_open(i915, file);
1036 if (ret)
1037 return ret;
1038
1039 return 0;
1040 }
1041
1042 /**
1043 * i915_driver_lastclose - clean up after all DRM clients have exited
1044 * @dev: DRM device
1045 *
1046 * Take care of cleaning up after all DRM clients have exited. In the
1047 * mode setting case, we want to restore the kernel's initial mode (just
1048 * in case the last client left us in a bad state).
1049 *
1050 * Additionally, in the non-mode setting case, we'll tear down the GTT
1051 * and DMA structures, since the kernel won't be using them, and clea
1052 * up any GEM state.
1053 */
i915_driver_lastclose(struct drm_device * dev)1054 static void i915_driver_lastclose(struct drm_device *dev)
1055 {
1056 intel_fbdev_restore_mode(dev);
1057
1058 vga_switcheroo_process_delayed_switch();
1059 }
1060
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)1061 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1062 {
1063 struct drm_i915_file_private *file_priv = file->driver_priv;
1064
1065 i915_gem_context_close(file);
1066 i915_drm_client_put(file_priv->client);
1067
1068 kfree_rcu(file_priv, rcu);
1069
1070 /* Catch up with all the deferred frees from "this" client */
1071 i915_gem_flush_free_objects(to_i915(dev));
1072 }
1073
intel_suspend_encoders(struct drm_i915_private * dev_priv)1074 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1075 {
1076 struct drm_device *dev = &dev_priv->drm;
1077 struct intel_encoder *encoder;
1078
1079 if (!HAS_DISPLAY(dev_priv))
1080 return;
1081
1082 drm_modeset_lock_all(dev);
1083 for_each_intel_encoder(dev, encoder)
1084 if (encoder->suspend)
1085 encoder->suspend(encoder);
1086 drm_modeset_unlock_all(dev);
1087 }
1088
intel_shutdown_encoders(struct drm_i915_private * dev_priv)1089 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1090 {
1091 struct drm_device *dev = &dev_priv->drm;
1092 struct intel_encoder *encoder;
1093
1094 if (!HAS_DISPLAY(dev_priv))
1095 return;
1096
1097 drm_modeset_lock_all(dev);
1098 for_each_intel_encoder(dev, encoder)
1099 if (encoder->shutdown)
1100 encoder->shutdown(encoder);
1101 drm_modeset_unlock_all(dev);
1102 }
1103
i915_driver_shutdown(struct drm_i915_private * i915)1104 void i915_driver_shutdown(struct drm_i915_private *i915)
1105 {
1106 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1107 intel_runtime_pm_disable(&i915->runtime_pm);
1108 intel_power_domains_disable(i915);
1109
1110 if (HAS_DISPLAY(i915)) {
1111 drm_kms_helper_poll_disable(&i915->drm);
1112
1113 drm_atomic_helper_shutdown(&i915->drm);
1114 }
1115
1116 intel_dp_mst_suspend(i915);
1117
1118 intel_runtime_pm_disable_interrupts(i915);
1119 intel_hpd_cancel_work(i915);
1120
1121 intel_suspend_encoders(i915);
1122 intel_shutdown_encoders(i915);
1123
1124 intel_dmc_ucode_suspend(i915);
1125
1126 i915_gem_suspend(i915);
1127
1128 /*
1129 * The only requirement is to reboot with display DC states disabled,
1130 * for now leaving all display power wells in the INIT power domain
1131 * enabled.
1132 *
1133 * TODO:
1134 * - unify the pci_driver::shutdown sequence here with the
1135 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1136 * - unify the driver remove and system/runtime suspend sequences with
1137 * the above unified shutdown/poweroff sequence.
1138 */
1139 intel_power_domains_driver_remove(i915);
1140 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1141
1142 intel_runtime_pm_driver_release(&i915->runtime_pm);
1143 }
1144
suspend_to_idle(struct drm_i915_private * dev_priv)1145 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1146 {
1147 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1148 if (acpi_target_system_state() < ACPI_STATE_S3)
1149 return true;
1150 #endif
1151 return false;
1152 }
1153
i915_drm_prepare(struct drm_device * dev)1154 static int i915_drm_prepare(struct drm_device *dev)
1155 {
1156 struct drm_i915_private *i915 = to_i915(dev);
1157
1158 /*
1159 * NB intel_display_suspend() may issue new requests after we've
1160 * ostensibly marked the GPU as ready-to-sleep here. We need to
1161 * split out that work and pull it forward so that after point,
1162 * the GPU is not woken again.
1163 */
1164 return i915_gem_backup_suspend(i915);
1165 }
1166
i915_drm_suspend(struct drm_device * dev)1167 static int i915_drm_suspend(struct drm_device *dev)
1168 {
1169 struct drm_i915_private *dev_priv = to_i915(dev);
1170 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1171 pci_power_t opregion_target_state;
1172
1173 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1174
1175 /* We do a lot of poking in a lot of registers, make sure they work
1176 * properly. */
1177 intel_power_domains_disable(dev_priv);
1178 if (HAS_DISPLAY(dev_priv))
1179 drm_kms_helper_poll_disable(dev);
1180
1181 pci_save_state(pdev);
1182
1183 intel_display_suspend(dev);
1184
1185 intel_dp_mst_suspend(dev_priv);
1186
1187 intel_runtime_pm_disable_interrupts(dev_priv);
1188 intel_hpd_cancel_work(dev_priv);
1189
1190 intel_suspend_encoders(dev_priv);
1191
1192 intel_suspend_hw(dev_priv);
1193
1194 /* Must be called before GGTT is suspended. */
1195 intel_dpt_suspend(dev_priv);
1196 i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1197
1198 i915_save_display(dev_priv);
1199
1200 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1201 intel_opregion_suspend(dev_priv, opregion_target_state);
1202
1203 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1204
1205 dev_priv->suspend_count++;
1206
1207 intel_dmc_ucode_suspend(dev_priv);
1208
1209 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1210
1211 i915_gem_drain_freed_objects(dev_priv);
1212
1213 return 0;
1214 }
1215
1216 static enum i915_drm_suspend_mode
get_suspend_mode(struct drm_i915_private * dev_priv,bool hibernate)1217 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1218 {
1219 if (hibernate)
1220 return I915_DRM_SUSPEND_HIBERNATE;
1221
1222 if (suspend_to_idle(dev_priv))
1223 return I915_DRM_SUSPEND_IDLE;
1224
1225 return I915_DRM_SUSPEND_MEM;
1226 }
1227
i915_drm_suspend_late(struct drm_device * dev,bool hibernation)1228 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1229 {
1230 struct drm_i915_private *dev_priv = to_i915(dev);
1231 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1232 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1233 struct intel_gt *gt;
1234 int ret, i;
1235
1236 disable_rpm_wakeref_asserts(rpm);
1237
1238 i915_gem_suspend_late(dev_priv);
1239
1240 for_each_gt(gt, dev_priv, i)
1241 intel_uncore_suspend(gt->uncore);
1242
1243 intel_power_domains_suspend(dev_priv,
1244 get_suspend_mode(dev_priv, hibernation));
1245
1246 intel_display_power_suspend_late(dev_priv);
1247
1248 ret = vlv_suspend_complete(dev_priv);
1249 if (ret) {
1250 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1251 intel_power_domains_resume(dev_priv);
1252
1253 goto out;
1254 }
1255
1256 pci_disable_device(pdev);
1257 /*
1258 * During hibernation on some platforms the BIOS may try to access
1259 * the device even though it's already in D3 and hang the machine. So
1260 * leave the device in D0 on those platforms and hope the BIOS will
1261 * power down the device properly. The issue was seen on multiple old
1262 * GENs with different BIOS vendors, so having an explicit blacklist
1263 * is inpractical; apply the workaround on everything pre GEN6. The
1264 * platforms where the issue was seen:
1265 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1266 * Fujitsu FSC S7110
1267 * Acer Aspire 1830T
1268 */
1269 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1270 pci_set_power_state(pdev, PCI_D3hot);
1271
1272 out:
1273 enable_rpm_wakeref_asserts(rpm);
1274 if (!dev_priv->uncore.user_forcewake_count)
1275 intel_runtime_pm_driver_release(rpm);
1276
1277 return ret;
1278 }
1279
i915_driver_suspend_switcheroo(struct drm_i915_private * i915,pm_message_t state)1280 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1281 pm_message_t state)
1282 {
1283 int error;
1284
1285 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1286 state.event != PM_EVENT_FREEZE))
1287 return -EINVAL;
1288
1289 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1290 return 0;
1291
1292 error = i915_drm_suspend(&i915->drm);
1293 if (error)
1294 return error;
1295
1296 return i915_drm_suspend_late(&i915->drm, false);
1297 }
1298
i915_drm_resume(struct drm_device * dev)1299 static int i915_drm_resume(struct drm_device *dev)
1300 {
1301 struct drm_i915_private *dev_priv = to_i915(dev);
1302 int ret;
1303
1304 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1305
1306 ret = i915_pcode_init(dev_priv);
1307 if (ret)
1308 return ret;
1309
1310 sanitize_gpu(dev_priv);
1311
1312 ret = i915_ggtt_enable_hw(dev_priv);
1313 if (ret)
1314 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1315
1316 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1317 /* Must be called after GGTT is resumed. */
1318 intel_dpt_resume(dev_priv);
1319
1320 intel_dmc_ucode_resume(dev_priv);
1321
1322 i915_restore_display(dev_priv);
1323 intel_pps_unlock_regs_wa(dev_priv);
1324
1325 intel_init_pch_refclk(dev_priv);
1326
1327 /*
1328 * Interrupts have to be enabled before any batches are run. If not the
1329 * GPU will hang. i915_gem_init_hw() will initiate batches to
1330 * update/restore the context.
1331 *
1332 * drm_mode_config_reset() needs AUX interrupts.
1333 *
1334 * Modeset enabling in intel_modeset_init_hw() also needs working
1335 * interrupts.
1336 */
1337 intel_runtime_pm_enable_interrupts(dev_priv);
1338
1339 if (HAS_DISPLAY(dev_priv))
1340 drm_mode_config_reset(dev);
1341
1342 i915_gem_resume(dev_priv);
1343
1344 intel_modeset_init_hw(dev_priv);
1345 intel_init_clock_gating(dev_priv);
1346 intel_hpd_init(dev_priv);
1347
1348 /* MST sideband requires HPD interrupts enabled */
1349 intel_dp_mst_resume(dev_priv);
1350 intel_display_resume(dev);
1351
1352 intel_hpd_poll_disable(dev_priv);
1353 if (HAS_DISPLAY(dev_priv))
1354 drm_kms_helper_poll_enable(dev);
1355
1356 intel_opregion_resume(dev_priv);
1357
1358 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1359
1360 intel_power_domains_enable(dev_priv);
1361
1362 intel_gvt_resume(dev_priv);
1363
1364 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1365
1366 return 0;
1367 }
1368
i915_drm_resume_early(struct drm_device * dev)1369 static int i915_drm_resume_early(struct drm_device *dev)
1370 {
1371 struct drm_i915_private *dev_priv = to_i915(dev);
1372 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1373 struct intel_gt *gt;
1374 int ret, i;
1375
1376 /*
1377 * We have a resume ordering issue with the snd-hda driver also
1378 * requiring our device to be power up. Due to the lack of a
1379 * parent/child relationship we currently solve this with an early
1380 * resume hook.
1381 *
1382 * FIXME: This should be solved with a special hdmi sink device or
1383 * similar so that power domains can be employed.
1384 */
1385
1386 /*
1387 * Note that we need to set the power state explicitly, since we
1388 * powered off the device during freeze and the PCI core won't power
1389 * it back up for us during thaw. Powering off the device during
1390 * freeze is not a hard requirement though, and during the
1391 * suspend/resume phases the PCI core makes sure we get here with the
1392 * device powered on. So in case we change our freeze logic and keep
1393 * the device powered we can also remove the following set power state
1394 * call.
1395 */
1396 ret = pci_set_power_state(pdev, PCI_D0);
1397 if (ret) {
1398 drm_err(&dev_priv->drm,
1399 "failed to set PCI D0 power state (%d)\n", ret);
1400 return ret;
1401 }
1402
1403 /*
1404 * Note that pci_enable_device() first enables any parent bridge
1405 * device and only then sets the power state for this device. The
1406 * bridge enabling is a nop though, since bridge devices are resumed
1407 * first. The order of enabling power and enabling the device is
1408 * imposed by the PCI core as described above, so here we preserve the
1409 * same order for the freeze/thaw phases.
1410 *
1411 * TODO: eventually we should remove pci_disable_device() /
1412 * pci_enable_enable_device() from suspend/resume. Due to how they
1413 * depend on the device enable refcount we can't anyway depend on them
1414 * disabling/enabling the device.
1415 */
1416 if (pci_enable_device(pdev))
1417 return -EIO;
1418
1419 pci_set_master(pdev);
1420
1421 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1422
1423 ret = vlv_resume_prepare(dev_priv, false);
1424 if (ret)
1425 drm_err(&dev_priv->drm,
1426 "Resume prepare failed: %d, continuing anyway\n", ret);
1427
1428 for_each_gt(gt, dev_priv, i) {
1429 intel_uncore_resume_early(gt->uncore);
1430 intel_gt_check_and_clear_faults(gt);
1431 }
1432
1433 intel_display_power_resume_early(dev_priv);
1434
1435 intel_power_domains_resume(dev_priv);
1436
1437 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1438
1439 return ret;
1440 }
1441
i915_driver_resume_switcheroo(struct drm_i915_private * i915)1442 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1443 {
1444 int ret;
1445
1446 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1447 return 0;
1448
1449 ret = i915_drm_resume_early(&i915->drm);
1450 if (ret)
1451 return ret;
1452
1453 return i915_drm_resume(&i915->drm);
1454 }
1455
i915_pm_prepare(struct device * kdev)1456 static int i915_pm_prepare(struct device *kdev)
1457 {
1458 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1459
1460 if (!i915) {
1461 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1462 return -ENODEV;
1463 }
1464
1465 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1466 return 0;
1467
1468 return i915_drm_prepare(&i915->drm);
1469 }
1470
i915_pm_suspend(struct device * kdev)1471 static int i915_pm_suspend(struct device *kdev)
1472 {
1473 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1474
1475 if (!i915) {
1476 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1477 return -ENODEV;
1478 }
1479
1480 i915_ggtt_mark_pte_lost(i915, false);
1481
1482 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1483 return 0;
1484
1485 return i915_drm_suspend(&i915->drm);
1486 }
1487
i915_pm_suspend_late(struct device * kdev)1488 static int i915_pm_suspend_late(struct device *kdev)
1489 {
1490 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1491
1492 /*
1493 * We have a suspend ordering issue with the snd-hda driver also
1494 * requiring our device to be power up. Due to the lack of a
1495 * parent/child relationship we currently solve this with an late
1496 * suspend hook.
1497 *
1498 * FIXME: This should be solved with a special hdmi sink device or
1499 * similar so that power domains can be employed.
1500 */
1501 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1502 return 0;
1503
1504 return i915_drm_suspend_late(&i915->drm, false);
1505 }
1506
i915_pm_poweroff_late(struct device * kdev)1507 static int i915_pm_poweroff_late(struct device *kdev)
1508 {
1509 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1510
1511 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1512 return 0;
1513
1514 return i915_drm_suspend_late(&i915->drm, true);
1515 }
1516
i915_pm_resume_early(struct device * kdev)1517 static int i915_pm_resume_early(struct device *kdev)
1518 {
1519 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1520
1521 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1522 return 0;
1523
1524 return i915_drm_resume_early(&i915->drm);
1525 }
1526
i915_pm_resume(struct device * kdev)1527 static int i915_pm_resume(struct device *kdev)
1528 {
1529 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1530
1531 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1532 return 0;
1533
1534 /*
1535 * If IRST is enabled, or if we can't detect whether it's enabled,
1536 * then we must assume we lost the GGTT page table entries, since
1537 * they are not retained if IRST decided to enter S4.
1538 */
1539 if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1))
1540 i915_ggtt_mark_pte_lost(i915, true);
1541
1542 return i915_drm_resume(&i915->drm);
1543 }
1544
1545 /* freeze: before creating the hibernation_image */
i915_pm_freeze(struct device * kdev)1546 static int i915_pm_freeze(struct device *kdev)
1547 {
1548 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1549 int ret;
1550
1551 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1552 ret = i915_drm_suspend(&i915->drm);
1553 if (ret)
1554 return ret;
1555 }
1556
1557 ret = i915_gem_freeze(i915);
1558 if (ret)
1559 return ret;
1560
1561 return 0;
1562 }
1563
i915_pm_freeze_late(struct device * kdev)1564 static int i915_pm_freeze_late(struct device *kdev)
1565 {
1566 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1567 int ret;
1568
1569 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1570 ret = i915_drm_suspend_late(&i915->drm, true);
1571 if (ret)
1572 return ret;
1573 }
1574
1575 ret = i915_gem_freeze_late(i915);
1576 if (ret)
1577 return ret;
1578
1579 return 0;
1580 }
1581
1582 /* thaw: called after creating the hibernation image, but before turning off. */
i915_pm_thaw_early(struct device * kdev)1583 static int i915_pm_thaw_early(struct device *kdev)
1584 {
1585 return i915_pm_resume_early(kdev);
1586 }
1587
i915_pm_thaw(struct device * kdev)1588 static int i915_pm_thaw(struct device *kdev)
1589 {
1590 return i915_pm_resume(kdev);
1591 }
1592
1593 /* restore: called after loading the hibernation image. */
i915_pm_restore_early(struct device * kdev)1594 static int i915_pm_restore_early(struct device *kdev)
1595 {
1596 return i915_pm_resume_early(kdev);
1597 }
1598
i915_pm_restore(struct device * kdev)1599 static int i915_pm_restore(struct device *kdev)
1600 {
1601 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1602
1603 i915_ggtt_mark_pte_lost(i915, true);
1604 return i915_pm_resume(kdev);
1605 }
1606
intel_runtime_suspend(struct device * kdev)1607 static int intel_runtime_suspend(struct device *kdev)
1608 {
1609 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1610 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1611 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1612 struct pci_dev *root_pdev;
1613 struct intel_gt *gt;
1614 int ret, i;
1615
1616 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1617 return -ENODEV;
1618
1619 drm_dbg(&dev_priv->drm, "Suspending device\n");
1620
1621 disable_rpm_wakeref_asserts(rpm);
1622
1623 /*
1624 * We are safe here against re-faults, since the fault handler takes
1625 * an RPM reference.
1626 */
1627 i915_gem_runtime_suspend(dev_priv);
1628
1629 for_each_gt(gt, dev_priv, i)
1630 intel_gt_runtime_suspend(gt);
1631
1632 intel_runtime_pm_disable_interrupts(dev_priv);
1633
1634 for_each_gt(gt, dev_priv, i)
1635 intel_uncore_suspend(gt->uncore);
1636
1637 intel_display_power_suspend(dev_priv);
1638
1639 ret = vlv_suspend_complete(dev_priv);
1640 if (ret) {
1641 drm_err(&dev_priv->drm,
1642 "Runtime suspend failed, disabling it (%d)\n", ret);
1643 intel_uncore_runtime_resume(&dev_priv->uncore);
1644
1645 intel_runtime_pm_enable_interrupts(dev_priv);
1646
1647 for_each_gt(gt, dev_priv, i)
1648 intel_gt_runtime_resume(gt);
1649
1650 enable_rpm_wakeref_asserts(rpm);
1651
1652 return ret;
1653 }
1654
1655 enable_rpm_wakeref_asserts(rpm);
1656 intel_runtime_pm_driver_release(rpm);
1657
1658 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1659 drm_err(&dev_priv->drm,
1660 "Unclaimed access detected prior to suspending\n");
1661
1662 /*
1663 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1664 * This should be totally removed when we handle the pci states properly
1665 * on runtime PM.
1666 */
1667 root_pdev = pcie_find_root_port(pdev);
1668 if (root_pdev)
1669 pci_d3cold_disable(root_pdev);
1670
1671 rpm->suspended = true;
1672
1673 /*
1674 * FIXME: We really should find a document that references the arguments
1675 * used below!
1676 */
1677 if (IS_BROADWELL(dev_priv)) {
1678 /*
1679 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1680 * being detected, and the call we do at intel_runtime_resume()
1681 * won't be able to restore them. Since PCI_D3hot matches the
1682 * actual specification and appears to be working, use it.
1683 */
1684 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1685 } else {
1686 /*
1687 * current versions of firmware which depend on this opregion
1688 * notification have repurposed the D1 definition to mean
1689 * "runtime suspended" vs. what you would normally expect (D3)
1690 * to distinguish it from notifications that might be sent via
1691 * the suspend path.
1692 */
1693 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1694 }
1695
1696 assert_forcewakes_inactive(&dev_priv->uncore);
1697
1698 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1699 intel_hpd_poll_enable(dev_priv);
1700
1701 drm_dbg(&dev_priv->drm, "Device suspended\n");
1702 return 0;
1703 }
1704
intel_runtime_resume(struct device * kdev)1705 static int intel_runtime_resume(struct device *kdev)
1706 {
1707 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1708 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1709 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1710 struct pci_dev *root_pdev;
1711 struct intel_gt *gt;
1712 int ret, i;
1713
1714 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1715 return -ENODEV;
1716
1717 drm_dbg(&dev_priv->drm, "Resuming device\n");
1718
1719 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1720 disable_rpm_wakeref_asserts(rpm);
1721
1722 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1723 rpm->suspended = false;
1724
1725 root_pdev = pcie_find_root_port(pdev);
1726 if (root_pdev)
1727 pci_d3cold_enable(root_pdev);
1728
1729 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1730 drm_dbg(&dev_priv->drm,
1731 "Unclaimed access during suspend, bios?\n");
1732
1733 intel_display_power_resume(dev_priv);
1734
1735 ret = vlv_resume_prepare(dev_priv, true);
1736
1737 for_each_gt(gt, dev_priv, i)
1738 intel_uncore_runtime_resume(gt->uncore);
1739
1740 intel_runtime_pm_enable_interrupts(dev_priv);
1741
1742 /*
1743 * No point of rolling back things in case of an error, as the best
1744 * we can do is to hope that things will still work (and disable RPM).
1745 */
1746 for_each_gt(gt, dev_priv, i)
1747 intel_gt_runtime_resume(gt);
1748
1749 /*
1750 * On VLV/CHV display interrupts are part of the display
1751 * power well, so hpd is reinitialized from there. For
1752 * everyone else do it here.
1753 */
1754 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1755 intel_hpd_init(dev_priv);
1756 intel_hpd_poll_disable(dev_priv);
1757 }
1758
1759 skl_watermark_ipc_update(dev_priv);
1760
1761 enable_rpm_wakeref_asserts(rpm);
1762
1763 if (ret)
1764 drm_err(&dev_priv->drm,
1765 "Runtime resume failed, disabling it (%d)\n", ret);
1766 else
1767 drm_dbg(&dev_priv->drm, "Device resumed\n");
1768
1769 return ret;
1770 }
1771
1772 const struct dev_pm_ops i915_pm_ops = {
1773 /*
1774 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1775 * PMSG_RESUME]
1776 */
1777 .prepare = i915_pm_prepare,
1778 .suspend = i915_pm_suspend,
1779 .suspend_late = i915_pm_suspend_late,
1780 .resume_early = i915_pm_resume_early,
1781 .resume = i915_pm_resume,
1782
1783 /*
1784 * S4 event handlers
1785 * @freeze, @freeze_late : called (1) before creating the
1786 * hibernation image [PMSG_FREEZE] and
1787 * (2) after rebooting, before restoring
1788 * the image [PMSG_QUIESCE]
1789 * @thaw, @thaw_early : called (1) after creating the hibernation
1790 * image, before writing it [PMSG_THAW]
1791 * and (2) after failing to create or
1792 * restore the image [PMSG_RECOVER]
1793 * @poweroff, @poweroff_late: called after writing the hibernation
1794 * image, before rebooting [PMSG_HIBERNATE]
1795 * @restore, @restore_early : called after rebooting and restoring the
1796 * hibernation image [PMSG_RESTORE]
1797 */
1798 .freeze = i915_pm_freeze,
1799 .freeze_late = i915_pm_freeze_late,
1800 .thaw_early = i915_pm_thaw_early,
1801 .thaw = i915_pm_thaw,
1802 .poweroff = i915_pm_suspend,
1803 .poweroff_late = i915_pm_poweroff_late,
1804 .restore_early = i915_pm_restore_early,
1805 .restore = i915_pm_restore,
1806
1807 /* S0ix (via runtime suspend) event handlers */
1808 .runtime_suspend = intel_runtime_suspend,
1809 .runtime_resume = intel_runtime_resume,
1810 };
1811
1812 static const struct file_operations i915_driver_fops = {
1813 .owner = THIS_MODULE,
1814 .open = drm_open,
1815 .release = drm_release_noglobal,
1816 .unlocked_ioctl = drm_ioctl,
1817 .mmap = i915_gem_mmap,
1818 .poll = drm_poll,
1819 .read = drm_read,
1820 .compat_ioctl = i915_ioc32_compat_ioctl,
1821 .llseek = noop_llseek,
1822 #ifdef CONFIG_PROC_FS
1823 .show_fdinfo = i915_drm_client_fdinfo,
1824 #endif
1825 };
1826
1827 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1828 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1829 struct drm_file *file)
1830 {
1831 return -ENODEV;
1832 }
1833
1834 static const struct drm_ioctl_desc i915_ioctls[] = {
1835 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1836 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1837 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1838 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1839 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1840 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1841 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1842 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1843 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1844 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1845 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1846 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1847 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1848 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1849 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1850 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1851 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1852 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1853 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1854 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1855 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1856 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1857 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1858 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1859 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1860 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1861 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1862 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1863 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1864 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1865 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1866 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1867 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1868 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1869 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1870 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1871 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1872 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1873 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1874 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1875 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1876 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1877 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1878 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1879 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1880 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1881 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1882 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1883 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1884 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1885 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1886 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1887 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1888 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1889 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1890 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1891 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1892 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1893 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1894 };
1895
1896 /*
1897 * Interface history:
1898 *
1899 * 1.1: Original.
1900 * 1.2: Add Power Management
1901 * 1.3: Add vblank support
1902 * 1.4: Fix cmdbuffer path, add heap destroy
1903 * 1.5: Add vblank pipe configuration
1904 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1905 * - Support vertical blank on secondary display pipe
1906 */
1907 #define DRIVER_MAJOR 1
1908 #define DRIVER_MINOR 6
1909 #define DRIVER_PATCHLEVEL 0
1910
1911 static const struct drm_driver i915_drm_driver = {
1912 /* Don't use MTRRs here; the Xserver or userspace app should
1913 * deal with them for Intel hardware.
1914 */
1915 .driver_features =
1916 DRIVER_GEM |
1917 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1918 DRIVER_SYNCOBJ_TIMELINE,
1919 .release = i915_driver_release,
1920 .open = i915_driver_open,
1921 .lastclose = i915_driver_lastclose,
1922 .postclose = i915_driver_postclose,
1923
1924 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1925 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1926 .gem_prime_import = i915_gem_prime_import,
1927
1928 .dumb_create = i915_gem_dumb_create,
1929 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1930
1931 .ioctls = i915_ioctls,
1932 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1933 .fops = &i915_driver_fops,
1934 .name = DRIVER_NAME,
1935 .desc = DRIVER_DESC,
1936 .date = DRIVER_DATE,
1937 .major = DRIVER_MAJOR,
1938 .minor = DRIVER_MINOR,
1939 .patchlevel = DRIVER_PATCHLEVEL,
1940 };
1941