1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_hem.h"
43
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u32 port,const u8 * addr)44 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
45 const u8 *addr)
46 {
47 u8 phy_port;
48 u32 i;
49
50 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
51 return 0;
52
53 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
54 return 0;
55
56 for (i = 0; i < ETH_ALEN; i++)
57 hr_dev->dev_addr[port][i] = addr[i];
58
59 phy_port = hr_dev->iboe.phy_port[port];
60 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
61 }
62
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
64 {
65 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
66 u32 port = attr->port_num - 1;
67 int ret;
68
69 if (port >= hr_dev->caps.num_ports)
70 return -EINVAL;
71
72 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
73
74 return ret;
75 }
76
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
78 {
79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
80 u32 port = attr->port_num - 1;
81 int ret;
82
83 if (port >= hr_dev->caps.num_ports)
84 return -EINVAL;
85
86 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
87
88 return ret;
89 }
90
handle_en_event(struct hns_roce_dev * hr_dev,u32 port,unsigned long event)91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
92 unsigned long event)
93 {
94 struct device *dev = hr_dev->dev;
95 struct net_device *netdev;
96 int ret = 0;
97
98 netdev = hr_dev->iboe.netdevs[port];
99 if (!netdev) {
100 dev_err(dev, "can't find netdev on port(%u)!\n", port);
101 return -ENODEV;
102 }
103
104 switch (event) {
105 case NETDEV_UP:
106 case NETDEV_CHANGE:
107 case NETDEV_REGISTER:
108 case NETDEV_CHANGEADDR:
109 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
110 break;
111 case NETDEV_DOWN:
112 /*
113 * In v1 engine, only support all ports closed together.
114 */
115 break;
116 default:
117 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
118 break;
119 }
120
121 return ret;
122 }
123
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)124 static int hns_roce_netdev_event(struct notifier_block *self,
125 unsigned long event, void *ptr)
126 {
127 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
128 struct hns_roce_ib_iboe *iboe = NULL;
129 struct hns_roce_dev *hr_dev = NULL;
130 int ret;
131 u32 port;
132
133 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
134 iboe = &hr_dev->iboe;
135
136 for (port = 0; port < hr_dev->caps.num_ports; port++) {
137 if (dev == iboe->netdevs[port]) {
138 ret = handle_en_event(hr_dev, port, event);
139 if (ret)
140 return NOTIFY_DONE;
141 break;
142 }
143 }
144
145 return NOTIFY_DONE;
146 }
147
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
149 {
150 int ret;
151 u8 i;
152
153 for (i = 0; i < hr_dev->caps.num_ports; i++) {
154 ret = hns_roce_set_mac(hr_dev, i,
155 hr_dev->iboe.netdevs[i]->dev_addr);
156 if (ret)
157 return ret;
158 }
159
160 return 0;
161 }
162
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)163 static int hns_roce_query_device(struct ib_device *ib_dev,
164 struct ib_device_attr *props,
165 struct ib_udata *uhw)
166 {
167 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
168
169 memset(props, 0, sizeof(*props));
170
171 props->fw_ver = hr_dev->caps.fw_ver;
172 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
173 props->max_mr_size = (u64)(~(0ULL));
174 props->page_size_cap = hr_dev->caps.page_size_cap;
175 props->vendor_id = hr_dev->vendor_id;
176 props->vendor_part_id = hr_dev->vendor_part_id;
177 props->hw_ver = hr_dev->hw_rev;
178 props->max_qp = hr_dev->caps.num_qps;
179 props->max_qp_wr = hr_dev->caps.max_wqes;
180 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
181 IB_DEVICE_RC_RNR_NAK_GEN;
182 props->max_send_sge = hr_dev->caps.max_sq_sg;
183 props->max_recv_sge = hr_dev->caps.max_rq_sg;
184 props->max_sge_rd = 1;
185 props->max_cq = hr_dev->caps.num_cqs;
186 props->max_cqe = hr_dev->caps.max_cqes;
187 props->max_mr = hr_dev->caps.num_mtpts;
188 props->max_pd = hr_dev->caps.num_pds;
189 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
190 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
191 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
192 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
193 props->max_pkeys = 1;
194 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
195 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
196 props->max_srq = hr_dev->caps.num_srqs;
197 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
198 props->max_srq_sge = hr_dev->caps.max_srq_sges;
199 }
200
201 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
202 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
203 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
204 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
205 }
206
207 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
208 props->device_cap_flags |= IB_DEVICE_XRC;
209
210 return 0;
211 }
212
hns_roce_query_port(struct ib_device * ib_dev,u32 port_num,struct ib_port_attr * props)213 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
214 struct ib_port_attr *props)
215 {
216 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
217 struct device *dev = hr_dev->dev;
218 struct net_device *net_dev;
219 unsigned long flags;
220 enum ib_mtu mtu;
221 u32 port;
222 int ret;
223
224 port = port_num - 1;
225
226 /* props being zeroed by the caller, avoid zeroing it here */
227
228 props->max_mtu = hr_dev->caps.max_mtu;
229 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
230 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
231 IB_PORT_VENDOR_CLASS_SUP |
232 IB_PORT_BOOT_MGMT_SUP;
233 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
234 props->pkey_tbl_len = 1;
235 ret = ib_get_eth_speed(ib_dev, port_num, &props->active_speed,
236 &props->active_width);
237 if (ret)
238 ibdev_warn(ib_dev, "failed to get speed, ret = %d.\n", ret);
239
240 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
241
242 net_dev = hr_dev->iboe.netdevs[port];
243 if (!net_dev) {
244 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
245 dev_err(dev, "find netdev %u failed!\n", port);
246 return -EINVAL;
247 }
248
249 mtu = iboe_get_mtu(net_dev->mtu);
250 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
251 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
252 IB_PORT_ACTIVE :
253 IB_PORT_DOWN;
254 props->phys_state = props->state == IB_PORT_ACTIVE ?
255 IB_PORT_PHYS_STATE_LINK_UP :
256 IB_PORT_PHYS_STATE_DISABLED;
257
258 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
259
260 return 0;
261 }
262
hns_roce_get_link_layer(struct ib_device * device,u32 port_num)263 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
264 u32 port_num)
265 {
266 return IB_LINK_LAYER_ETHERNET;
267 }
268
hns_roce_query_pkey(struct ib_device * ib_dev,u32 port,u16 index,u16 * pkey)269 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
270 u16 *pkey)
271 {
272 if (index > 0)
273 return -EINVAL;
274
275 *pkey = PKEY_ID;
276
277 return 0;
278 }
279
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)280 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
281 struct ib_device_modify *props)
282 {
283 unsigned long flags;
284
285 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
286 return -EOPNOTSUPP;
287
288 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
289 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
290 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
291 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
292 }
293
294 return 0;
295 }
296
297 struct hns_user_mmap_entry *
hns_roce_user_mmap_entry_insert(struct ib_ucontext * ucontext,u64 address,size_t length,enum hns_roce_mmap_type mmap_type)298 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
299 size_t length,
300 enum hns_roce_mmap_type mmap_type)
301 {
302 struct hns_user_mmap_entry *entry;
303 int ret;
304
305 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
306 if (!entry)
307 return NULL;
308
309 entry->address = address;
310 entry->mmap_type = mmap_type;
311
312 switch (mmap_type) {
313 /* pgoff 0 must be used by DB for compatibility */
314 case HNS_ROCE_MMAP_TYPE_DB:
315 ret = rdma_user_mmap_entry_insert_exact(
316 ucontext, &entry->rdma_entry, length, 0);
317 break;
318 case HNS_ROCE_MMAP_TYPE_DWQE:
319 ret = rdma_user_mmap_entry_insert_range(
320 ucontext, &entry->rdma_entry, length, 1,
321 U32_MAX);
322 break;
323 default:
324 ret = -EINVAL;
325 break;
326 }
327
328 if (ret) {
329 kfree(entry);
330 return NULL;
331 }
332
333 return entry;
334 }
335
hns_roce_dealloc_uar_entry(struct hns_roce_ucontext * context)336 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
337 {
338 if (context->db_mmap_entry)
339 rdma_user_mmap_entry_remove(
340 &context->db_mmap_entry->rdma_entry);
341 }
342
hns_roce_alloc_uar_entry(struct ib_ucontext * uctx)343 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
344 {
345 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
346 u64 address;
347
348 address = context->uar.pfn << PAGE_SHIFT;
349 context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
350 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
351 if (!context->db_mmap_entry)
352 return -ENOMEM;
353
354 return 0;
355 }
356
hns_roce_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)357 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
358 struct ib_udata *udata)
359 {
360 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
361 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
362 struct hns_roce_ib_alloc_ucontext_resp resp = {};
363 struct hns_roce_ib_alloc_ucontext ucmd = {};
364 int ret;
365
366 if (!hr_dev->active)
367 return -EAGAIN;
368
369 resp.qp_tab_size = hr_dev->caps.num_qps;
370 resp.srq_tab_size = hr_dev->caps.num_srqs;
371
372 ret = ib_copy_from_udata(&ucmd, udata,
373 min(udata->inlen, sizeof(ucmd)));
374 if (ret)
375 return ret;
376
377 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
378 context->config = ucmd.config & HNS_ROCE_EXSGE_FLAGS;
379
380 if (context->config & HNS_ROCE_EXSGE_FLAGS) {
381 resp.config |= HNS_ROCE_RSP_EXSGE_FLAGS;
382 resp.max_inline_data = hr_dev->caps.max_sq_inline;
383 }
384
385 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
386 if (ret)
387 goto error_fail_uar_alloc;
388
389 ret = hns_roce_alloc_uar_entry(uctx);
390 if (ret)
391 goto error_fail_uar_entry;
392
393 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
394 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
395 INIT_LIST_HEAD(&context->page_list);
396 mutex_init(&context->page_mutex);
397 }
398
399 resp.cqe_size = hr_dev->caps.cqe_sz;
400
401 ret = ib_copy_to_udata(udata, &resp,
402 min(udata->outlen, sizeof(resp)));
403 if (ret)
404 goto error_fail_copy_to_udata;
405
406 return 0;
407
408 error_fail_copy_to_udata:
409 hns_roce_dealloc_uar_entry(context);
410
411 error_fail_uar_entry:
412 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
413
414 error_fail_uar_alloc:
415 return ret;
416 }
417
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)418 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
419 {
420 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
421 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
422
423 hns_roce_dealloc_uar_entry(context);
424
425 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
426 }
427
hns_roce_mmap(struct ib_ucontext * uctx,struct vm_area_struct * vma)428 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
429 {
430 struct rdma_user_mmap_entry *rdma_entry;
431 struct hns_user_mmap_entry *entry;
432 phys_addr_t pfn;
433 pgprot_t prot;
434 int ret;
435
436 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
437 if (!rdma_entry)
438 return -EINVAL;
439
440 entry = to_hns_mmap(rdma_entry);
441 pfn = entry->address >> PAGE_SHIFT;
442
443 switch (entry->mmap_type) {
444 case HNS_ROCE_MMAP_TYPE_DB:
445 case HNS_ROCE_MMAP_TYPE_DWQE:
446 prot = pgprot_device(vma->vm_page_prot);
447 break;
448 default:
449 ret = -EINVAL;
450 goto out;
451 }
452
453 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
454 prot, rdma_entry);
455
456 out:
457 rdma_user_mmap_entry_put(rdma_entry);
458 return ret;
459 }
460
hns_roce_free_mmap(struct rdma_user_mmap_entry * rdma_entry)461 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
462 {
463 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
464
465 kfree(entry);
466 }
467
hns_roce_port_immutable(struct ib_device * ib_dev,u32 port_num,struct ib_port_immutable * immutable)468 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
469 struct ib_port_immutable *immutable)
470 {
471 struct ib_port_attr attr;
472 int ret;
473
474 ret = ib_query_port(ib_dev, port_num, &attr);
475 if (ret)
476 return ret;
477
478 immutable->pkey_tbl_len = attr.pkey_tbl_len;
479 immutable->gid_tbl_len = attr.gid_tbl_len;
480
481 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
482 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
483 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
484 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
485
486 return 0;
487 }
488
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)489 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
490 {
491 }
492
hns_roce_get_fw_ver(struct ib_device * device,char * str)493 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
494 {
495 u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
496 unsigned int major, minor, sub_minor;
497
498 major = upper_32_bits(fw_ver);
499 minor = high_16_bits(lower_32_bits(fw_ver));
500 sub_minor = low_16_bits(fw_ver);
501
502 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
503 sub_minor);
504 }
505
hns_roce_unregister_device(struct hns_roce_dev * hr_dev)506 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
507 {
508 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
509
510 hr_dev->active = false;
511 unregister_netdevice_notifier(&iboe->nb);
512 ib_unregister_device(&hr_dev->ib_dev);
513 }
514
515 static const struct ib_device_ops hns_roce_dev_ops = {
516 .owner = THIS_MODULE,
517 .driver_id = RDMA_DRIVER_HNS,
518 .uverbs_abi_ver = 1,
519 .uverbs_no_driver_id_binding = 1,
520
521 .get_dev_fw_str = hns_roce_get_fw_ver,
522 .add_gid = hns_roce_add_gid,
523 .alloc_pd = hns_roce_alloc_pd,
524 .alloc_ucontext = hns_roce_alloc_ucontext,
525 .create_ah = hns_roce_create_ah,
526 .create_user_ah = hns_roce_create_ah,
527 .create_cq = hns_roce_create_cq,
528 .create_qp = hns_roce_create_qp,
529 .dealloc_pd = hns_roce_dealloc_pd,
530 .dealloc_ucontext = hns_roce_dealloc_ucontext,
531 .del_gid = hns_roce_del_gid,
532 .dereg_mr = hns_roce_dereg_mr,
533 .destroy_ah = hns_roce_destroy_ah,
534 .destroy_cq = hns_roce_destroy_cq,
535 .disassociate_ucontext = hns_roce_disassociate_ucontext,
536 .get_dma_mr = hns_roce_get_dma_mr,
537 .get_link_layer = hns_roce_get_link_layer,
538 .get_port_immutable = hns_roce_port_immutable,
539 .mmap = hns_roce_mmap,
540 .mmap_free = hns_roce_free_mmap,
541 .modify_device = hns_roce_modify_device,
542 .modify_qp = hns_roce_modify_qp,
543 .query_ah = hns_roce_query_ah,
544 .query_device = hns_roce_query_device,
545 .query_pkey = hns_roce_query_pkey,
546 .query_port = hns_roce_query_port,
547 .reg_user_mr = hns_roce_reg_user_mr,
548
549 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
550 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
551 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
552 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
553 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
554 };
555
556 static const struct ib_device_ops hns_roce_dev_mr_ops = {
557 .rereg_user_mr = hns_roce_rereg_user_mr,
558 };
559
560 static const struct ib_device_ops hns_roce_dev_mw_ops = {
561 .alloc_mw = hns_roce_alloc_mw,
562 .dealloc_mw = hns_roce_dealloc_mw,
563
564 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
565 };
566
567 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
568 .alloc_mr = hns_roce_alloc_mr,
569 .map_mr_sg = hns_roce_map_mr_sg,
570 };
571
572 static const struct ib_device_ops hns_roce_dev_srq_ops = {
573 .create_srq = hns_roce_create_srq,
574 .destroy_srq = hns_roce_destroy_srq,
575
576 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
577 };
578
579 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
580 .alloc_xrcd = hns_roce_alloc_xrcd,
581 .dealloc_xrcd = hns_roce_dealloc_xrcd,
582
583 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
584 };
585
586 static const struct ib_device_ops hns_roce_dev_restrack_ops = {
587 .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
588 .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw,
589 .fill_res_qp_entry = hns_roce_fill_res_qp_entry,
590 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw,
591 .fill_res_mr_entry = hns_roce_fill_res_mr_entry,
592 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw,
593 };
594
hns_roce_register_device(struct hns_roce_dev * hr_dev)595 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
596 {
597 int ret;
598 struct hns_roce_ib_iboe *iboe = NULL;
599 struct ib_device *ib_dev = NULL;
600 struct device *dev = hr_dev->dev;
601 unsigned int i;
602
603 iboe = &hr_dev->iboe;
604 spin_lock_init(&iboe->lock);
605
606 ib_dev = &hr_dev->ib_dev;
607
608 ib_dev->node_type = RDMA_NODE_IB_CA;
609 ib_dev->dev.parent = dev;
610
611 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
612 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
613 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
614
615 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
616 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
617
618 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
619 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
620
621 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
622 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
623
624 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
625 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
626 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
627 }
628
629 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
630 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
631
632 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
633 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
634 ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops);
635 for (i = 0; i < hr_dev->caps.num_ports; i++) {
636 if (!hr_dev->iboe.netdevs[i])
637 continue;
638
639 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
640 i + 1);
641 if (ret)
642 return ret;
643 }
644 dma_set_max_seg_size(dev, UINT_MAX);
645 ret = ib_register_device(ib_dev, "hns_%d", dev);
646 if (ret) {
647 dev_err(dev, "ib_register_device failed!\n");
648 return ret;
649 }
650
651 ret = hns_roce_setup_mtu_mac(hr_dev);
652 if (ret) {
653 dev_err(dev, "setup_mtu_mac failed!\n");
654 goto error_failed_setup_mtu_mac;
655 }
656
657 iboe->nb.notifier_call = hns_roce_netdev_event;
658 ret = register_netdevice_notifier(&iboe->nb);
659 if (ret) {
660 dev_err(dev, "register_netdevice_notifier failed!\n");
661 goto error_failed_setup_mtu_mac;
662 }
663
664 hr_dev->active = true;
665 return 0;
666
667 error_failed_setup_mtu_mac:
668 ib_unregister_device(ib_dev);
669
670 return ret;
671 }
672
hns_roce_init_hem(struct hns_roce_dev * hr_dev)673 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
674 {
675 struct device *dev = hr_dev->dev;
676 int ret;
677
678 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
679 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
680 hr_dev->caps.num_mtpts);
681 if (ret) {
682 dev_err(dev, "failed to init MTPT context memory, aborting.\n");
683 return ret;
684 }
685
686 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
687 HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
688 hr_dev->caps.num_qps);
689 if (ret) {
690 dev_err(dev, "failed to init QP context memory, aborting.\n");
691 goto err_unmap_dmpt;
692 }
693
694 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
695 HEM_TYPE_IRRL,
696 hr_dev->caps.irrl_entry_sz *
697 hr_dev->caps.max_qp_init_rdma,
698 hr_dev->caps.num_qps);
699 if (ret) {
700 dev_err(dev, "failed to init irrl_table memory, aborting.\n");
701 goto err_unmap_qp;
702 }
703
704 if (hr_dev->caps.trrl_entry_sz) {
705 ret = hns_roce_init_hem_table(hr_dev,
706 &hr_dev->qp_table.trrl_table,
707 HEM_TYPE_TRRL,
708 hr_dev->caps.trrl_entry_sz *
709 hr_dev->caps.max_qp_dest_rdma,
710 hr_dev->caps.num_qps);
711 if (ret) {
712 dev_err(dev,
713 "failed to init trrl_table memory, aborting.\n");
714 goto err_unmap_irrl;
715 }
716 }
717
718 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
719 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
720 hr_dev->caps.num_cqs);
721 if (ret) {
722 dev_err(dev, "failed to init CQ context memory, aborting.\n");
723 goto err_unmap_trrl;
724 }
725
726 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
727 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
728 HEM_TYPE_SRQC,
729 hr_dev->caps.srqc_entry_sz,
730 hr_dev->caps.num_srqs);
731 if (ret) {
732 dev_err(dev,
733 "failed to init SRQ context memory, aborting.\n");
734 goto err_unmap_cq;
735 }
736 }
737
738 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
739 ret = hns_roce_init_hem_table(hr_dev,
740 &hr_dev->qp_table.sccc_table,
741 HEM_TYPE_SCCC,
742 hr_dev->caps.sccc_sz,
743 hr_dev->caps.num_qps);
744 if (ret) {
745 dev_err(dev,
746 "failed to init SCC context memory, aborting.\n");
747 goto err_unmap_srq;
748 }
749 }
750
751 if (hr_dev->caps.qpc_timer_entry_sz) {
752 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
753 HEM_TYPE_QPC_TIMER,
754 hr_dev->caps.qpc_timer_entry_sz,
755 hr_dev->caps.qpc_timer_bt_num);
756 if (ret) {
757 dev_err(dev,
758 "failed to init QPC timer memory, aborting.\n");
759 goto err_unmap_ctx;
760 }
761 }
762
763 if (hr_dev->caps.cqc_timer_entry_sz) {
764 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
765 HEM_TYPE_CQC_TIMER,
766 hr_dev->caps.cqc_timer_entry_sz,
767 hr_dev->caps.cqc_timer_bt_num);
768 if (ret) {
769 dev_err(dev,
770 "failed to init CQC timer memory, aborting.\n");
771 goto err_unmap_qpc_timer;
772 }
773 }
774
775 if (hr_dev->caps.gmv_entry_sz) {
776 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
777 HEM_TYPE_GMV,
778 hr_dev->caps.gmv_entry_sz,
779 hr_dev->caps.gmv_entry_num);
780 if (ret) {
781 dev_err(dev,
782 "failed to init gmv table memory, ret = %d\n",
783 ret);
784 goto err_unmap_cqc_timer;
785 }
786 }
787
788 return 0;
789
790 err_unmap_cqc_timer:
791 if (hr_dev->caps.cqc_timer_entry_sz)
792 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
793
794 err_unmap_qpc_timer:
795 if (hr_dev->caps.qpc_timer_entry_sz)
796 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
797
798 err_unmap_ctx:
799 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
800 hns_roce_cleanup_hem_table(hr_dev,
801 &hr_dev->qp_table.sccc_table);
802 err_unmap_srq:
803 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
804 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
805
806 err_unmap_cq:
807 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
808
809 err_unmap_trrl:
810 if (hr_dev->caps.trrl_entry_sz)
811 hns_roce_cleanup_hem_table(hr_dev,
812 &hr_dev->qp_table.trrl_table);
813
814 err_unmap_irrl:
815 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
816
817 err_unmap_qp:
818 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
819
820 err_unmap_dmpt:
821 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
822
823 return ret;
824 }
825
826 /**
827 * hns_roce_setup_hca - setup host channel adapter
828 * @hr_dev: pointer to hns roce device
829 * Return : int
830 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)831 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
832 {
833 struct device *dev = hr_dev->dev;
834 int ret;
835
836 spin_lock_init(&hr_dev->sm_lock);
837
838 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
839 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
840 INIT_LIST_HEAD(&hr_dev->pgdir_list);
841 mutex_init(&hr_dev->pgdir_mutex);
842 }
843
844 hns_roce_init_uar_table(hr_dev);
845
846 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
847 if (ret) {
848 dev_err(dev, "failed to allocate priv_uar.\n");
849 goto err_uar_table_free;
850 }
851
852 ret = hns_roce_init_qp_table(hr_dev);
853 if (ret) {
854 dev_err(dev, "failed to init qp_table.\n");
855 goto err_uar_table_free;
856 }
857
858 hns_roce_init_pd_table(hr_dev);
859
860 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
861 hns_roce_init_xrcd_table(hr_dev);
862
863 hns_roce_init_mr_table(hr_dev);
864
865 hns_roce_init_cq_table(hr_dev);
866
867 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
868 hns_roce_init_srq_table(hr_dev);
869
870 return 0;
871
872 err_uar_table_free:
873 ida_destroy(&hr_dev->uar_ida.ida);
874 return ret;
875 }
876
check_and_get_armed_cq(struct list_head * cq_list,struct ib_cq * cq)877 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
878 {
879 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
880 unsigned long flags;
881
882 spin_lock_irqsave(&hr_cq->lock, flags);
883 if (cq->comp_handler) {
884 if (!hr_cq->is_armed) {
885 hr_cq->is_armed = 1;
886 list_add_tail(&hr_cq->node, cq_list);
887 }
888 }
889 spin_unlock_irqrestore(&hr_cq->lock, flags);
890 }
891
hns_roce_handle_device_err(struct hns_roce_dev * hr_dev)892 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
893 {
894 struct hns_roce_qp *hr_qp;
895 struct hns_roce_cq *hr_cq;
896 struct list_head cq_list;
897 unsigned long flags_qp;
898 unsigned long flags;
899
900 INIT_LIST_HEAD(&cq_list);
901
902 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
903 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
904 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
905 if (hr_qp->sq.tail != hr_qp->sq.head)
906 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
907 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
908
909 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
910 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
911 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
912 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
913 }
914
915 list_for_each_entry(hr_cq, &cq_list, node)
916 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
917
918 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
919 }
920
hns_roce_init(struct hns_roce_dev * hr_dev)921 int hns_roce_init(struct hns_roce_dev *hr_dev)
922 {
923 struct device *dev = hr_dev->dev;
924 int ret;
925
926 hr_dev->is_reset = false;
927
928 if (hr_dev->hw->cmq_init) {
929 ret = hr_dev->hw->cmq_init(hr_dev);
930 if (ret) {
931 dev_err(dev, "init RoCE Command Queue failed!\n");
932 return ret;
933 }
934 }
935
936 ret = hr_dev->hw->hw_profile(hr_dev);
937 if (ret) {
938 dev_err(dev, "get RoCE engine profile failed!\n");
939 goto error_failed_cmd_init;
940 }
941
942 ret = hns_roce_cmd_init(hr_dev);
943 if (ret) {
944 dev_err(dev, "cmd init failed!\n");
945 goto error_failed_cmd_init;
946 }
947
948 /* EQ depends on poll mode, event mode depends on EQ */
949 ret = hr_dev->hw->init_eq(hr_dev);
950 if (ret) {
951 dev_err(dev, "eq init failed!\n");
952 goto error_failed_eq_table;
953 }
954
955 if (hr_dev->cmd_mod) {
956 ret = hns_roce_cmd_use_events(hr_dev);
957 if (ret)
958 dev_warn(dev,
959 "Cmd event mode failed, set back to poll!\n");
960 }
961
962 ret = hns_roce_init_hem(hr_dev);
963 if (ret) {
964 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
965 goto error_failed_init_hem;
966 }
967
968 ret = hns_roce_setup_hca(hr_dev);
969 if (ret) {
970 dev_err(dev, "setup hca failed!\n");
971 goto error_failed_setup_hca;
972 }
973
974 if (hr_dev->hw->hw_init) {
975 ret = hr_dev->hw->hw_init(hr_dev);
976 if (ret) {
977 dev_err(dev, "hw_init failed!\n");
978 goto error_failed_engine_init;
979 }
980 }
981
982 INIT_LIST_HEAD(&hr_dev->qp_list);
983 spin_lock_init(&hr_dev->qp_list_lock);
984 INIT_LIST_HEAD(&hr_dev->dip_list);
985 spin_lock_init(&hr_dev->dip_list_lock);
986
987 ret = hns_roce_register_device(hr_dev);
988 if (ret)
989 goto error_failed_register_device;
990
991 return 0;
992
993 error_failed_register_device:
994 if (hr_dev->hw->hw_exit)
995 hr_dev->hw->hw_exit(hr_dev);
996
997 error_failed_engine_init:
998 hns_roce_cleanup_bitmap(hr_dev);
999
1000 error_failed_setup_hca:
1001 hns_roce_cleanup_hem(hr_dev);
1002
1003 error_failed_init_hem:
1004 if (hr_dev->cmd_mod)
1005 hns_roce_cmd_use_polling(hr_dev);
1006 hr_dev->hw->cleanup_eq(hr_dev);
1007
1008 error_failed_eq_table:
1009 hns_roce_cmd_cleanup(hr_dev);
1010
1011 error_failed_cmd_init:
1012 if (hr_dev->hw->cmq_exit)
1013 hr_dev->hw->cmq_exit(hr_dev);
1014
1015 return ret;
1016 }
1017
hns_roce_exit(struct hns_roce_dev * hr_dev)1018 void hns_roce_exit(struct hns_roce_dev *hr_dev)
1019 {
1020 hns_roce_unregister_device(hr_dev);
1021
1022 if (hr_dev->hw->hw_exit)
1023 hr_dev->hw->hw_exit(hr_dev);
1024 hns_roce_cleanup_bitmap(hr_dev);
1025 hns_roce_cleanup_hem(hr_dev);
1026
1027 if (hr_dev->cmd_mod)
1028 hns_roce_cmd_use_polling(hr_dev);
1029
1030 hr_dev->hw->cleanup_eq(hr_dev);
1031 hns_roce_cmd_cleanup(hr_dev);
1032 if (hr_dev->hw->cmq_exit)
1033 hr_dev->hw->cmq_exit(hr_dev);
1034 }
1035
1036 MODULE_LICENSE("Dual BSD/GPL");
1037 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1038 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1039 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1040 MODULE_DESCRIPTION("HNS RoCE Driver");
1041