1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /***************************************************************************
3 * Copyright (C) 2006-2010 by Marin Mitov *
4 * mitov@issp.bas.bg *
5 * *
6 * *
7 ***************************************************************************/
8
9 #include <linux/module.h>
10 #include <linux/stringify.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/slab.h>
14 #include <media/v4l2-dev.h>
15 #include <media/v4l2-ioctl.h>
16 #include <media/v4l2-common.h>
17 #include <media/videobuf2-dma-contig.h>
18
19 #include "dt3155.h"
20
21 #define DT3155_DEVICE_ID 0x1223
22
23 /**
24 * read_i2c_reg - reads an internal i2c register
25 *
26 * @addr: dt3155 mmio base address
27 * @index: index (internal address) of register to read
28 * @data: pointer to byte the read data will be placed in
29 *
30 * returns: zero on success or error code
31 *
32 * This function starts reading the specified (by index) register
33 * and busy waits for the process to finish. The result is placed
34 * in a byte pointed by data.
35 */
read_i2c_reg(void __iomem * addr,u8 index,u8 * data)36 static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
37 {
38 u32 tmp = index;
39
40 iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2);
41 udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
42 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
43 return -EIO; /* error: NEW_CYCLE not cleared */
44 tmp = ioread32(addr + IIC_CSR1);
45 if (tmp & DIRECT_ABORT) {
46 /* reset DIRECT_ABORT bit */
47 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
48 return -EIO; /* error: DIRECT_ABORT set */
49 }
50 *data = tmp >> 24;
51 return 0;
52 }
53
54 /**
55 * write_i2c_reg - writes to an internal i2c register
56 *
57 * @addr: dt3155 mmio base address
58 * @index: index (internal address) of register to read
59 * @data: data to be written
60 *
61 * returns: zero on success or error code
62 *
63 * This function starts writing the specified (by index) register
64 * and busy waits for the process to finish.
65 */
write_i2c_reg(void __iomem * addr,u8 index,u8 data)66 static int write_i2c_reg(void __iomem *addr, u8 index, u8 data)
67 {
68 u32 tmp = index;
69
70 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
71 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
72 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
73 return -EIO; /* error: NEW_CYCLE not cleared */
74 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
75 /* reset DIRECT_ABORT bit */
76 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
77 return -EIO; /* error: DIRECT_ABORT set */
78 }
79 return 0;
80 }
81
82 /**
83 * write_i2c_reg_nowait - writes to an internal i2c register
84 *
85 * @addr: dt3155 mmio base address
86 * @index: index (internal address) of register to read
87 * @data: data to be written
88 *
89 * This function starts writing the specified (by index) register
90 * and then returns.
91 */
write_i2c_reg_nowait(void __iomem * addr,u8 index,u8 data)92 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
93 {
94 u32 tmp = index;
95
96 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
97 }
98
99 /**
100 * wait_i2c_reg - waits the read/write to finish
101 *
102 * @addr: dt3155 mmio base address
103 *
104 * returns: zero on success or error code
105 *
106 * This function waits reading/writing to finish.
107 */
wait_i2c_reg(void __iomem * addr)108 static int wait_i2c_reg(void __iomem *addr)
109 {
110 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
111 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
112 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
113 return -EIO; /* error: NEW_CYCLE not cleared */
114 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
115 /* reset DIRECT_ABORT bit */
116 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
117 return -EIO; /* error: DIRECT_ABORT set */
118 }
119 return 0;
120 }
121
122 static int
dt3155_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])123 dt3155_queue_setup(struct vb2_queue *vq,
124 unsigned int *nbuffers, unsigned int *num_planes,
125 unsigned int sizes[], struct device *alloc_devs[])
126
127 {
128 struct dt3155_priv *pd = vb2_get_drv_priv(vq);
129 unsigned size = pd->width * pd->height;
130
131 if (vq->num_buffers + *nbuffers < 2)
132 *nbuffers = 2 - vq->num_buffers;
133 if (*num_planes)
134 return sizes[0] < size ? -EINVAL : 0;
135 *num_planes = 1;
136 sizes[0] = size;
137 return 0;
138 }
139
dt3155_buf_prepare(struct vb2_buffer * vb)140 static int dt3155_buf_prepare(struct vb2_buffer *vb)
141 {
142 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
143
144 vb2_set_plane_payload(vb, 0, pd->width * pd->height);
145 return 0;
146 }
147
dt3155_start_streaming(struct vb2_queue * q,unsigned count)148 static int dt3155_start_streaming(struct vb2_queue *q, unsigned count)
149 {
150 struct dt3155_priv *pd = vb2_get_drv_priv(q);
151 struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;
152 dma_addr_t dma_addr;
153
154 pd->sequence = 0;
155 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
156 iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
157 iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
158 iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
159 iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
160 /* enable interrupts, clear all irq flags */
161 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
162 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
163 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
164 FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
165 pd->regs + CSR1);
166 wait_i2c_reg(pd->regs);
167 write_i2c_reg(pd->regs, CONFIG, pd->config);
168 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
169 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
170
171 /* start the board */
172 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
173 return 0;
174 }
175
dt3155_stop_streaming(struct vb2_queue * q)176 static void dt3155_stop_streaming(struct vb2_queue *q)
177 {
178 struct dt3155_priv *pd = vb2_get_drv_priv(q);
179 struct vb2_buffer *vb;
180
181 spin_lock_irq(&pd->lock);
182 /* stop the board */
183 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
184 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
185 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
186 /* disable interrupts, clear all irq flags */
187 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
188 spin_unlock_irq(&pd->lock);
189
190 /*
191 * It is not clear whether the DMA stops at once or whether it
192 * will finish the current frame or field first. To be on the
193 * safe side we wait a bit.
194 */
195 msleep(45);
196
197 spin_lock_irq(&pd->lock);
198 if (pd->curr_buf) {
199 vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR);
200 pd->curr_buf = NULL;
201 }
202
203 while (!list_empty(&pd->dmaq)) {
204 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
205 list_del(&vb->done_entry);
206 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
207 }
208 spin_unlock_irq(&pd->lock);
209 }
210
dt3155_buf_queue(struct vb2_buffer * vb)211 static void dt3155_buf_queue(struct vb2_buffer *vb)
212 {
213 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
214 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
215
216 /* pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked */
217 spin_lock_irq(&pd->lock);
218 if (pd->curr_buf)
219 list_add_tail(&vb->done_entry, &pd->dmaq);
220 else
221 pd->curr_buf = vbuf;
222 spin_unlock_irq(&pd->lock);
223 }
224
225 static const struct vb2_ops q_ops = {
226 .queue_setup = dt3155_queue_setup,
227 .wait_prepare = vb2_ops_wait_prepare,
228 .wait_finish = vb2_ops_wait_finish,
229 .buf_prepare = dt3155_buf_prepare,
230 .start_streaming = dt3155_start_streaming,
231 .stop_streaming = dt3155_stop_streaming,
232 .buf_queue = dt3155_buf_queue,
233 };
234
dt3155_irq_handler_even(int irq,void * dev_id)235 static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id)
236 {
237 struct dt3155_priv *ipd = dev_id;
238 struct vb2_buffer *ivb;
239 dma_addr_t dma_addr;
240 u32 tmp;
241
242 tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
243 if (!tmp)
244 return IRQ_NONE; /* not our irq */
245 if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
246 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
247 ipd->regs + INT_CSR);
248 return IRQ_HANDLED; /* start of field irq */
249 }
250 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
251 if (tmp) {
252 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
253 FLD_DN_ODD | FLD_DN_EVEN |
254 CAP_CONT_EVEN | CAP_CONT_ODD,
255 ipd->regs + CSR1);
256 }
257
258 spin_lock(&ipd->lock);
259 if (ipd->curr_buf && !list_empty(&ipd->dmaq)) {
260 ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns();
261 ipd->curr_buf->sequence = ipd->sequence++;
262 ipd->curr_buf->field = V4L2_FIELD_NONE;
263 vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE);
264
265 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
266 list_del(&ivb->done_entry);
267 ipd->curr_buf = to_vb2_v4l2_buffer(ivb);
268 dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
269 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
270 iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);
271 iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);
272 iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);
273 }
274
275 /* enable interrupts, clear all irq flags */
276 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
277 FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
278 spin_unlock(&ipd->lock);
279 return IRQ_HANDLED;
280 }
281
282 static const struct v4l2_file_operations dt3155_fops = {
283 .owner = THIS_MODULE,
284 .open = v4l2_fh_open,
285 .release = vb2_fop_release,
286 .unlocked_ioctl = video_ioctl2,
287 .read = vb2_fop_read,
288 .mmap = vb2_fop_mmap,
289 .poll = vb2_fop_poll
290 };
291
dt3155_querycap(struct file * filp,void * p,struct v4l2_capability * cap)292 static int dt3155_querycap(struct file *filp, void *p,
293 struct v4l2_capability *cap)
294 {
295 strscpy(cap->driver, DT3155_NAME, sizeof(cap->driver));
296 strscpy(cap->card, DT3155_NAME " frame grabber", sizeof(cap->card));
297 return 0;
298 }
299
dt3155_enum_fmt_vid_cap(struct file * filp,void * p,struct v4l2_fmtdesc * f)300 static int dt3155_enum_fmt_vid_cap(struct file *filp,
301 void *p, struct v4l2_fmtdesc *f)
302 {
303 if (f->index)
304 return -EINVAL;
305 f->pixelformat = V4L2_PIX_FMT_GREY;
306 return 0;
307 }
308
dt3155_fmt_vid_cap(struct file * filp,void * p,struct v4l2_format * f)309 static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
310 {
311 struct dt3155_priv *pd = video_drvdata(filp);
312
313 f->fmt.pix.width = pd->width;
314 f->fmt.pix.height = pd->height;
315 f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
316 f->fmt.pix.field = V4L2_FIELD_NONE;
317 f->fmt.pix.bytesperline = f->fmt.pix.width;
318 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
319 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
320 return 0;
321 }
322
dt3155_g_std(struct file * filp,void * p,v4l2_std_id * norm)323 static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm)
324 {
325 struct dt3155_priv *pd = video_drvdata(filp);
326
327 *norm = pd->std;
328 return 0;
329 }
330
dt3155_s_std(struct file * filp,void * p,v4l2_std_id norm)331 static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm)
332 {
333 struct dt3155_priv *pd = video_drvdata(filp);
334
335 if (pd->std == norm)
336 return 0;
337 if (vb2_is_busy(&pd->vidq))
338 return -EBUSY;
339 pd->std = norm;
340 if (pd->std & V4L2_STD_525_60) {
341 pd->csr2 = VT_60HZ;
342 pd->width = 640;
343 pd->height = 480;
344 } else {
345 pd->csr2 = VT_50HZ;
346 pd->width = 768;
347 pd->height = 576;
348 }
349 return 0;
350 }
351
dt3155_enum_input(struct file * filp,void * p,struct v4l2_input * input)352 static int dt3155_enum_input(struct file *filp, void *p,
353 struct v4l2_input *input)
354 {
355 if (input->index > 3)
356 return -EINVAL;
357 if (input->index)
358 snprintf(input->name, sizeof(input->name), "VID%d",
359 input->index);
360 else
361 strscpy(input->name, "J2/VID0", sizeof(input->name));
362 input->type = V4L2_INPUT_TYPE_CAMERA;
363 input->std = V4L2_STD_ALL;
364 input->status = 0;
365 return 0;
366 }
367
dt3155_g_input(struct file * filp,void * p,unsigned int * i)368 static int dt3155_g_input(struct file *filp, void *p, unsigned int *i)
369 {
370 struct dt3155_priv *pd = video_drvdata(filp);
371
372 *i = pd->input;
373 return 0;
374 }
375
dt3155_s_input(struct file * filp,void * p,unsigned int i)376 static int dt3155_s_input(struct file *filp, void *p, unsigned int i)
377 {
378 struct dt3155_priv *pd = video_drvdata(filp);
379
380 if (i > 3)
381 return -EINVAL;
382 pd->input = i;
383 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
384 write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
385 return 0;
386 }
387
388 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
389 .vidioc_querycap = dt3155_querycap,
390 .vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap,
391 .vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap,
392 .vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap,
393 .vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap,
394 .vidioc_reqbufs = vb2_ioctl_reqbufs,
395 .vidioc_create_bufs = vb2_ioctl_create_bufs,
396 .vidioc_querybuf = vb2_ioctl_querybuf,
397 .vidioc_expbuf = vb2_ioctl_expbuf,
398 .vidioc_qbuf = vb2_ioctl_qbuf,
399 .vidioc_dqbuf = vb2_ioctl_dqbuf,
400 .vidioc_streamon = vb2_ioctl_streamon,
401 .vidioc_streamoff = vb2_ioctl_streamoff,
402 .vidioc_g_std = dt3155_g_std,
403 .vidioc_s_std = dt3155_s_std,
404 .vidioc_enum_input = dt3155_enum_input,
405 .vidioc_g_input = dt3155_g_input,
406 .vidioc_s_input = dt3155_s_input,
407 };
408
dt3155_init_board(struct dt3155_priv * pd)409 static int dt3155_init_board(struct dt3155_priv *pd)
410 {
411 struct pci_dev *pdev = pd->pdev;
412 int i;
413 u8 tmp = 0;
414
415 pci_set_master(pdev); /* dt3155 needs it */
416
417 /* resetting the adapter */
418 iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN |
419 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
420 msleep(20);
421
422 /* initializing adapter registers */
423 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
424 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
425 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
426 iowrite32(0x00000020, pd->regs + FIFO_TRIGGER);
427 iowrite32(0x00000103, pd->regs + XFER_MODE);
428 iowrite32(0, pd->regs + RETRY_WAIT_CNT);
429 iowrite32(0, pd->regs + INT_CSR);
430 iowrite32(1, pd->regs + EVEN_FLD_MASK);
431 iowrite32(1, pd->regs + ODD_FLD_MASK);
432 iowrite32(0, pd->regs + MASK_LENGTH);
433 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
434 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
435
436 /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
437 read_i2c_reg(pd->regs, DT_ID, &tmp);
438 if (tmp != DT3155_ID)
439 return -ENODEV;
440
441 /* initialize AD LUT */
442 write_i2c_reg(pd->regs, AD_ADDR, 0);
443 for (i = 0; i < 256; i++)
444 write_i2c_reg(pd->regs, AD_LUT, i);
445
446 /* initialize ADC references */
447 /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
448 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
449 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
450 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
451 write_i2c_reg(pd->regs, AD_CMD, 34);
452 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
453 write_i2c_reg(pd->regs, AD_CMD, 0);
454
455 /* initialize PM LUT */
456 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
457 for (i = 0; i < 256; i++) {
458 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
459 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
460 }
461 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
462 for (i = 0; i < 256; i++) {
463 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
464 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
465 }
466 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
467
468 /* select channel 1 for input and set sync level */
469 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
470 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
471
472 /* disable all irqs, clear all irq flags */
473 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
474 pd->regs + INT_CSR);
475
476 return 0;
477 }
478
479 static const struct video_device dt3155_vdev = {
480 .name = DT3155_NAME,
481 .fops = &dt3155_fops,
482 .ioctl_ops = &dt3155_ioctl_ops,
483 .minor = -1,
484 .release = video_device_release_empty,
485 .tvnorms = V4L2_STD_ALL,
486 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
487 V4L2_CAP_READWRITE,
488 };
489
dt3155_probe(struct pci_dev * pdev,const struct pci_device_id * id)490 static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
491 {
492 int err;
493 struct dt3155_priv *pd;
494
495 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
496 if (err)
497 return -ENODEV;
498 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
499 if (!pd)
500 return -ENOMEM;
501
502 err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
503 if (err)
504 return err;
505 pd->vdev = dt3155_vdev;
506 pd->vdev.v4l2_dev = &pd->v4l2_dev;
507 video_set_drvdata(&pd->vdev, pd); /* for use in video_fops */
508 pd->pdev = pdev;
509 pd->std = V4L2_STD_625_50;
510 pd->csr2 = VT_50HZ;
511 pd->width = 768;
512 pd->height = 576;
513 INIT_LIST_HEAD(&pd->dmaq);
514 mutex_init(&pd->mux);
515 pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
516 pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
517 pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
518 pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
519 pd->vidq.ops = &q_ops;
520 pd->vidq.mem_ops = &vb2_dma_contig_memops;
521 pd->vidq.drv_priv = pd;
522 pd->vidq.min_buffers_needed = 2;
523 pd->vidq.gfp_flags = GFP_DMA32;
524 pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */
525 pd->vidq.dev = &pdev->dev;
526 pd->vdev.queue = &pd->vidq;
527 err = vb2_queue_init(&pd->vidq);
528 if (err < 0)
529 goto err_v4l2_dev_unreg;
530 spin_lock_init(&pd->lock);
531 pd->config = ACQ_MODE_EVEN;
532 err = pci_enable_device(pdev);
533 if (err)
534 goto err_v4l2_dev_unreg;
535 err = pci_request_region(pdev, 0, pci_name(pdev));
536 if (err)
537 goto err_pci_disable;
538 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
539 if (!pd->regs) {
540 err = -ENOMEM;
541 goto err_free_reg;
542 }
543 err = dt3155_init_board(pd);
544 if (err)
545 goto err_iounmap;
546 err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
547 IRQF_SHARED, DT3155_NAME, pd);
548 if (err)
549 goto err_iounmap;
550 err = video_register_device(&pd->vdev, VFL_TYPE_VIDEO, -1);
551 if (err)
552 goto err_free_irq;
553 dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
554 return 0; /* success */
555
556 err_free_irq:
557 free_irq(pd->pdev->irq, pd);
558 err_iounmap:
559 pci_iounmap(pdev, pd->regs);
560 err_free_reg:
561 pci_release_region(pdev, 0);
562 err_pci_disable:
563 pci_disable_device(pdev);
564 err_v4l2_dev_unreg:
565 v4l2_device_unregister(&pd->v4l2_dev);
566 return err;
567 }
568
dt3155_remove(struct pci_dev * pdev)569 static void dt3155_remove(struct pci_dev *pdev)
570 {
571 struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
572 struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
573 v4l2_dev);
574
575 vb2_video_unregister_device(&pd->vdev);
576 free_irq(pd->pdev->irq, pd);
577 v4l2_device_unregister(&pd->v4l2_dev);
578 pci_iounmap(pdev, pd->regs);
579 pci_release_region(pdev, 0);
580 pci_disable_device(pdev);
581 }
582
583 static const struct pci_device_id pci_ids[] = {
584 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
585 { 0, /* zero marks the end */ },
586 };
587 MODULE_DEVICE_TABLE(pci, pci_ids);
588
589 static struct pci_driver pci_driver = {
590 .name = DT3155_NAME,
591 .id_table = pci_ids,
592 .probe = dt3155_probe,
593 .remove = dt3155_remove,
594 };
595
596 module_pci_driver(pci_driver);
597
598 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
599 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
600 MODULE_VERSION(DT3155_VERSION);
601 MODULE_LICENSE("GPL");
602