1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: PC Chen <pc.chen@mediatek.com>
5 * Tiffany Lin <tiffany.lin@mediatek.com>
6 */
7
8 #ifndef _MTK_VCODEC_DRV_H_
9 #define _MTK_VCODEC_DRV_H_
10
11 #include <linux/platform_device.h>
12 #include <linux/videodev2.h>
13 #include <media/v4l2-ctrls.h>
14 #include <media/v4l2-device.h>
15 #include <media/v4l2-ioctl.h>
16 #include <media/v4l2-mem2mem.h>
17 #include <media/videobuf2-core.h>
18
19 #include "mtk_vcodec_util.h"
20 #include "vdec_msg_queue.h"
21
22 #define MTK_VCODEC_DEC_NAME "mtk-vcodec-dec"
23 #define MTK_VCODEC_ENC_NAME "mtk-vcodec-enc"
24
25 #define MTK_VCODEC_MAX_PLANES 3
26 #define MTK_V4L2_BENCHMARK 0
27 #define WAIT_INTR_TIMEOUT_MS 1000
28 #define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >= MTK_VDEC_LAT_SINGLE_CORE)
29 #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_RACING)
30
31 /*
32 * enum mtk_hw_reg_idx - MTK hw register base index
33 */
34 enum mtk_hw_reg_idx {
35 VDEC_SYS,
36 VDEC_MISC,
37 VDEC_LD,
38 VDEC_TOP,
39 VDEC_CM,
40 VDEC_AD,
41 VDEC_AV,
42 VDEC_PP,
43 VDEC_HWD,
44 VDEC_HWQ,
45 VDEC_HWB,
46 VDEC_HWG,
47 NUM_MAX_VDEC_REG_BASE,
48 /* h264 encoder */
49 VENC_SYS = NUM_MAX_VDEC_REG_BASE,
50 /* vp8 encoder */
51 VENC_LT_SYS,
52 NUM_MAX_VCODEC_REG_BASE
53 };
54
55 /*
56 * enum mtk_instance_type - The type of an MTK Vcodec instance.
57 */
58 enum mtk_instance_type {
59 MTK_INST_DECODER = 0,
60 MTK_INST_ENCODER = 1,
61 };
62
63 /**
64 * enum mtk_instance_state - The state of an MTK Vcodec instance.
65 * @MTK_STATE_FREE: default state when instance is created
66 * @MTK_STATE_INIT: vcodec instance is initialized
67 * @MTK_STATE_HEADER: vdec had sps/pps header parsed or venc
68 * had sps/pps header encoded
69 * @MTK_STATE_FLUSH: vdec is flushing. Only used by decoder
70 * @MTK_STATE_ABORT: vcodec should be aborted
71 */
72 enum mtk_instance_state {
73 MTK_STATE_FREE = 0,
74 MTK_STATE_INIT = 1,
75 MTK_STATE_HEADER = 2,
76 MTK_STATE_FLUSH = 3,
77 MTK_STATE_ABORT = 4,
78 };
79
80 /*
81 * enum mtk_encode_param - General encoding parameters type
82 */
83 enum mtk_encode_param {
84 MTK_ENCODE_PARAM_NONE = 0,
85 MTK_ENCODE_PARAM_BITRATE = (1 << 0),
86 MTK_ENCODE_PARAM_FRAMERATE = (1 << 1),
87 MTK_ENCODE_PARAM_INTRA_PERIOD = (1 << 2),
88 MTK_ENCODE_PARAM_FORCE_INTRA = (1 << 3),
89 MTK_ENCODE_PARAM_GOP_SIZE = (1 << 4),
90 };
91
92 enum mtk_fmt_type {
93 MTK_FMT_DEC = 0,
94 MTK_FMT_ENC = 1,
95 MTK_FMT_FRAME = 2,
96 };
97
98 /*
99 * enum mtk_vdec_hw_id - Hardware index used to separate
100 * different hardware
101 */
102 enum mtk_vdec_hw_id {
103 MTK_VDEC_CORE,
104 MTK_VDEC_LAT0,
105 MTK_VDEC_LAT1,
106 MTK_VDEC_LAT_SOC,
107 MTK_VDEC_HW_MAX,
108 };
109
110 /*
111 * enum mtk_vdec_hw_count - Supported hardware count
112 */
113 enum mtk_vdec_hw_count {
114 MTK_VDEC_NO_HW = 0,
115 MTK_VDEC_ONE_CORE,
116 MTK_VDEC_ONE_LAT_ONE_CORE,
117 MTK_VDEC_MAX_HW_COUNT,
118 };
119
120 /*
121 * struct mtk_video_fmt - Structure used to store information about pixelformats
122 */
123 struct mtk_video_fmt {
124 u32 fourcc;
125 enum mtk_fmt_type type;
126 u32 num_planes;
127 u32 flags;
128 struct v4l2_frmsize_stepwise frmsize;
129 };
130
131 /*
132 * enum mtk_q_type - Type of queue
133 */
134 enum mtk_q_type {
135 MTK_Q_DATA_SRC = 0,
136 MTK_Q_DATA_DST = 1,
137 };
138
139 /*
140 * struct mtk_q_data - Structure used to store information about queue
141 */
142 struct mtk_q_data {
143 unsigned int visible_width;
144 unsigned int visible_height;
145 unsigned int coded_width;
146 unsigned int coded_height;
147 enum v4l2_field field;
148 unsigned int bytesperline[MTK_VCODEC_MAX_PLANES];
149 unsigned int sizeimage[MTK_VCODEC_MAX_PLANES];
150 const struct mtk_video_fmt *fmt;
151 };
152
153 /**
154 * struct mtk_enc_params - General encoding parameters
155 * @bitrate: target bitrate in bits per second
156 * @num_b_frame: number of b frames between p-frame
157 * @rc_frame: frame based rate control
158 * @rc_mb: macroblock based rate control
159 * @seq_hdr_mode: H.264 sequence header is encoded separately or joined
160 * with the first frame
161 * @intra_period: I frame period
162 * @gop_size: group of picture size, it's used as the intra frame period
163 * @framerate_num: frame rate numerator. ex: framerate_num=30 and
164 * framerate_denom=1 means FPS is 30
165 * @framerate_denom: frame rate denominator. ex: framerate_num=30 and
166 * framerate_denom=1 means FPS is 30
167 * @h264_max_qp: Max value for H.264 quantization parameter
168 * @h264_profile: V4L2 defined H.264 profile
169 * @h264_level: V4L2 defined H.264 level
170 * @force_intra: force/insert intra frame
171 */
172 struct mtk_enc_params {
173 unsigned int bitrate;
174 unsigned int num_b_frame;
175 unsigned int rc_frame;
176 unsigned int rc_mb;
177 unsigned int seq_hdr_mode;
178 unsigned int intra_period;
179 unsigned int gop_size;
180 unsigned int framerate_num;
181 unsigned int framerate_denom;
182 unsigned int h264_max_qp;
183 unsigned int h264_profile;
184 unsigned int h264_level;
185 unsigned int force_intra;
186 };
187
188 /*
189 * struct mtk_vcodec_clk_info - Structure used to store clock name
190 */
191 struct mtk_vcodec_clk_info {
192 const char *clk_name;
193 struct clk *vcodec_clk;
194 };
195
196 /*
197 * struct mtk_vcodec_clk - Structure used to store vcodec clock information
198 */
199 struct mtk_vcodec_clk {
200 struct mtk_vcodec_clk_info *clk_info;
201 int clk_num;
202 };
203
204 /*
205 * struct mtk_vcodec_pm - Power management data structure
206 */
207 struct mtk_vcodec_pm {
208 struct mtk_vcodec_clk vdec_clk;
209 struct mtk_vcodec_clk venc_clk;
210 struct device *dev;
211 };
212
213 /**
214 * struct vdec_pic_info - picture size information
215 * @pic_w: picture width
216 * @pic_h: picture height
217 * @buf_w: picture buffer width (64 aligned up from pic_w)
218 * @buf_h: picture buffer heiht (64 aligned up from pic_h)
219 * @fb_sz: bitstream size of each plane
220 * E.g. suppose picture size is 176x144,
221 * buffer size will be aligned to 176x160.
222 * @cap_fourcc: fourcc number(may changed when resolution change)
223 * @reserved: align struct to 64-bit in order to adjust 32-bit and 64-bit os.
224 */
225 struct vdec_pic_info {
226 unsigned int pic_w;
227 unsigned int pic_h;
228 unsigned int buf_w;
229 unsigned int buf_h;
230 unsigned int fb_sz[VIDEO_MAX_PLANES];
231 unsigned int cap_fourcc;
232 unsigned int reserved;
233 };
234
235 /**
236 * struct mtk_vcodec_ctx - Context (instance) private data.
237 *
238 * @type: type of the instance - decoder or encoder
239 * @dev: pointer to the mtk_vcodec_dev of the device
240 * @list: link to ctx_list of mtk_vcodec_dev
241 * @fh: struct v4l2_fh
242 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
243 * @q_data: store information of input and output queue
244 * of the context
245 * @id: index of the context that this structure describes
246 * @state: state of the context
247 * @param_change: indicate encode parameter type
248 * @enc_params: encoding parameters
249 * @dec_if: hooked decoder driver interface
250 * @enc_if: hooked encoder driver interface
251 * @drv_handle: driver handle for specific decode/encode instance
252 *
253 * @picinfo: store picture info after header parsing
254 * @dpb_size: store dpb count after header parsing
255 * @int_cond: variable used by the waitqueue
256 * @int_type: type of the last interrupt
257 * @queue: waitqueue that can be used to wait for this context to
258 * finish
259 * @irq_status: irq status
260 *
261 * @ctrl_hdl: handler for v4l2 framework
262 * @decode_work: worker for the decoding
263 * @encode_work: worker for the encoding
264 * @last_decoded_picinfo: pic information get from latest decode
265 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush. Only
266 * to be used with encoder and stateful decoder.
267 * @is_flushing: set to true if flushing is in progress.
268 * @current_codec: current set input codec, in V4L2 pixel format
269 * @capture_fourcc: capture queue type in V4L2 pixel format
270 *
271 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
272 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
273 * @quantization: enum v4l2_quantization, colorspace quantization
274 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
275 * @decoded_frame_cnt: number of decoded frames
276 * @lock: protect variables accessed by V4L2 threads and worker thread such as
277 * mtk_video_dec_buf.
278 * @hw_id: hardware index used to identify different hardware.
279 *
280 * @msg_queue: msg queue used to store lat buffer information.
281 * @q_mutex: vb2_queue mutex.
282 */
283 struct mtk_vcodec_ctx {
284 enum mtk_instance_type type;
285 struct mtk_vcodec_dev *dev;
286 struct list_head list;
287
288 struct v4l2_fh fh;
289 struct v4l2_m2m_ctx *m2m_ctx;
290 struct mtk_q_data q_data[2];
291 int id;
292 enum mtk_instance_state state;
293 enum mtk_encode_param param_change;
294 struct mtk_enc_params enc_params;
295
296 const struct vdec_common_if *dec_if;
297 const struct venc_common_if *enc_if;
298 void *drv_handle;
299
300 struct vdec_pic_info picinfo;
301 int dpb_size;
302
303 int int_cond[MTK_VDEC_HW_MAX];
304 int int_type[MTK_VDEC_HW_MAX];
305 wait_queue_head_t queue[MTK_VDEC_HW_MAX];
306 unsigned int irq_status;
307
308 struct v4l2_ctrl_handler ctrl_hdl;
309 struct work_struct decode_work;
310 struct work_struct encode_work;
311 struct vdec_pic_info last_decoded_picinfo;
312 struct v4l2_m2m_buffer empty_flush_buf;
313 bool is_flushing;
314
315 u32 current_codec;
316 u32 capture_fourcc;
317
318 enum v4l2_colorspace colorspace;
319 enum v4l2_ycbcr_encoding ycbcr_enc;
320 enum v4l2_quantization quantization;
321 enum v4l2_xfer_func xfer_func;
322
323 int decoded_frame_cnt;
324 struct mutex lock;
325 int hw_id;
326
327 struct vdec_msg_queue msg_queue;
328
329 struct mutex q_mutex;
330 };
331
332 /*
333 * enum mtk_vdec_hw_arch - Used to separate different hardware architecture
334 */
335 enum mtk_vdec_hw_arch {
336 MTK_VDEC_PURE_SINGLE_CORE,
337 MTK_VDEC_LAT_SINGLE_CORE,
338 };
339
340 /*
341 * struct mtk_vdec_format_types - Structure used to get supported
342 * format types according to decoder capability
343 */
344 enum mtk_vdec_format_types {
345 MTK_VDEC_FORMAT_MM21 = 0x20,
346 MTK_VDEC_FORMAT_MT21C = 0x40,
347 MTK_VDEC_FORMAT_H264_SLICE = 0x100,
348 MTK_VDEC_FORMAT_VP8_FRAME = 0x200,
349 MTK_VDEC_FORMAT_VP9_FRAME = 0x400,
350 MTK_VCODEC_INNER_RACING = 0x20000,
351 };
352
353 /**
354 * struct mtk_vcodec_dec_pdata - compatible data for each IC
355 * @init_vdec_params: init vdec params
356 * @ctrls_setup: init vcodec dec ctrls
357 * @worker: worker to start a decode job
358 * @flush_decoder: function that flushes the decoder
359 * @get_cap_buffer: get capture buffer from capture queue
360 * @cap_to_disp: put capture buffer to disp list for lat and core arch
361 * @vdec_vb2_ops: struct vb2_ops
362 *
363 * @vdec_formats: supported video decoder formats
364 * @num_formats: count of video decoder formats
365 * @default_out_fmt: default output buffer format
366 * @default_cap_fmt: default capture buffer format
367 *
368 * @hw_arch: hardware arch is used to separate pure_sin_core and lat_sin_core
369 *
370 * @is_subdev_supported: whether support parent-node architecture(subdev)
371 * @uses_stateless_api: whether the decoder uses the stateless API with requests
372 */
373
374 struct mtk_vcodec_dec_pdata {
375 void (*init_vdec_params)(struct mtk_vcodec_ctx *ctx);
376 int (*ctrls_setup)(struct mtk_vcodec_ctx *ctx);
377 void (*worker)(struct work_struct *work);
378 int (*flush_decoder)(struct mtk_vcodec_ctx *ctx);
379 struct vdec_fb *(*get_cap_buffer)(struct mtk_vcodec_ctx *ctx);
380 void (*cap_to_disp)(struct mtk_vcodec_ctx *ctx, int error,
381 struct media_request *src_buf_req);
382
383 struct vb2_ops *vdec_vb2_ops;
384
385 const struct mtk_video_fmt *vdec_formats;
386 const int *num_formats;
387 const struct mtk_video_fmt *default_out_fmt;
388 const struct mtk_video_fmt *default_cap_fmt;
389
390 enum mtk_vdec_hw_arch hw_arch;
391
392 bool is_subdev_supported;
393 bool uses_stateless_api;
394 };
395
396 /**
397 * struct mtk_vcodec_enc_pdata - compatible data for each IC
398 *
399 * @uses_ext: whether the encoder uses the extended firmware messaging format
400 * @min_bitrate: minimum supported encoding bitrate
401 * @max_bitrate: maximum supported encoding bitrate
402 * @capture_formats: array of supported capture formats
403 * @num_capture_formats: number of entries in capture_formats
404 * @output_formats: array of supported output formats
405 * @num_output_formats: number of entries in output_formats
406 * @core_id: stand for h264 or vp8 encode index
407 * @uses_34bit: whether the encoder uses 34-bit iova
408 */
409 struct mtk_vcodec_enc_pdata {
410 bool uses_ext;
411 unsigned long min_bitrate;
412 unsigned long max_bitrate;
413 const struct mtk_video_fmt *capture_formats;
414 size_t num_capture_formats;
415 const struct mtk_video_fmt *output_formats;
416 size_t num_output_formats;
417 int core_id;
418 bool uses_34bit;
419 };
420
421 #define MTK_ENC_CTX_IS_EXT(ctx) ((ctx)->dev->venc_pdata->uses_ext)
422 #define MTK_ENC_IOVA_IS_34BIT(ctx) ((ctx)->dev->venc_pdata->uses_34bit)
423
424 /**
425 * struct mtk_vcodec_dev - driver data
426 * @v4l2_dev: V4L2 device to register video devices for.
427 * @vfd_dec: Video device for decoder
428 * @mdev_dec: Media device for decoder
429 * @vfd_enc: Video device for encoder.
430 *
431 * @m2m_dev_dec: m2m device for decoder
432 * @m2m_dev_enc: m2m device for encoder.
433 * @plat_dev: platform device
434 * @ctx_list: list of struct mtk_vcodec_ctx
435 * @irqlock: protect data access by irq handler and work thread
436 * @curr_ctx: The context that is waiting for codec hardware
437 *
438 * @reg_base: Mapped address of MTK Vcodec registers.
439 * @vdec_pdata: decoder IC-specific data
440 * @venc_pdata: encoder IC-specific data
441 *
442 * @fw_handler: used to communicate with the firmware.
443 * @id_counter: used to identify current opened instance
444 *
445 * @decode_workqueue: decode work queue
446 * @encode_workqueue: encode work queue
447 *
448 * @int_cond: used to identify interrupt condition happen
449 * @int_type: used to identify what kind of interrupt condition happen
450 * @dev_mutex: video_device lock
451 * @queue: waitqueue for waiting for completion of device commands
452 *
453 * @dec_irq: decoder irq resource
454 * @enc_irq: h264 encoder irq resource
455 *
456 * @dec_mutex: decoder hardware lock
457 * @enc_mutex: encoder hardware lock.
458 *
459 * @pm: power management control
460 * @dec_capability: used to identify decode capability, ex: 4k
461 * @enc_capability: used to identify encode capability
462 *
463 * @core_workqueue: queue used for core hardware decode
464 * @msg_queue_core_ctx: msg queue context used for core workqueue
465 *
466 * @subdev_dev: subdev hardware device
467 * @subdev_prob_done: check whether all used hw device is prob done
468 * @subdev_bitmap: used to record hardware is ready or not
469 *
470 * @dec_active_cnt: used to mark whether need to record register value
471 * @vdec_racing_info: record register value
472 * @dec_racing_info_mutex: mutex lock used for inner racing mode
473 */
474 struct mtk_vcodec_dev {
475 struct v4l2_device v4l2_dev;
476 struct video_device *vfd_dec;
477 struct media_device mdev_dec;
478 struct video_device *vfd_enc;
479
480 struct v4l2_m2m_dev *m2m_dev_dec;
481 struct v4l2_m2m_dev *m2m_dev_enc;
482 struct platform_device *plat_dev;
483 struct list_head ctx_list;
484 spinlock_t irqlock;
485 struct mtk_vcodec_ctx *curr_ctx;
486 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
487 const struct mtk_vcodec_dec_pdata *vdec_pdata;
488 const struct mtk_vcodec_enc_pdata *venc_pdata;
489
490 struct mtk_vcodec_fw *fw_handler;
491
492 unsigned long id_counter;
493
494 struct workqueue_struct *decode_workqueue;
495 struct workqueue_struct *encode_workqueue;
496 int int_cond;
497 int int_type;
498 struct mutex dev_mutex;
499 wait_queue_head_t queue;
500
501 int dec_irq;
502 int enc_irq;
503
504 /* decoder hardware mutex lock */
505 struct mutex dec_mutex[MTK_VDEC_HW_MAX];
506 struct mutex enc_mutex;
507
508 struct mtk_vcodec_pm pm;
509 unsigned int dec_capability;
510 unsigned int enc_capability;
511
512 struct workqueue_struct *core_workqueue;
513 struct vdec_msg_queue_ctx msg_queue_core_ctx;
514
515 void *subdev_dev[MTK_VDEC_HW_MAX];
516 int (*subdev_prob_done)(struct mtk_vcodec_dev *vdec_dev);
517 DECLARE_BITMAP(subdev_bitmap, MTK_VDEC_HW_MAX);
518
519 atomic_t dec_active_cnt;
520 u32 vdec_racing_info[132];
521 /* Protects access to vdec_racing_info data */
522 struct mutex dec_racing_info_mutex;
523 };
524
fh_to_ctx(struct v4l2_fh * fh)525 static inline struct mtk_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
526 {
527 return container_of(fh, struct mtk_vcodec_ctx, fh);
528 }
529
ctrl_to_ctx(struct v4l2_ctrl * ctrl)530 static inline struct mtk_vcodec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
531 {
532 return container_of(ctrl->handler, struct mtk_vcodec_ctx, ctrl_hdl);
533 }
534
535 /* Wake up context wait_queue */
536 static inline void
wake_up_ctx(struct mtk_vcodec_ctx * ctx,unsigned int reason,unsigned int hw_id)537 wake_up_ctx(struct mtk_vcodec_ctx *ctx, unsigned int reason, unsigned int hw_id)
538 {
539 ctx->int_cond[hw_id] = 1;
540 ctx->int_type[hw_id] = reason;
541 wake_up_interruptible(&ctx->queue[hw_id]);
542 }
543
544 #endif /* _MTK_VCODEC_DRV_H_ */
545