1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
4 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
5 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/netdevice.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/pci.h>
15 #include <linux/can/dev.h>
16 #include <linux/io.h>
17
18 #include "sja1000.h"
19
20 #define DRV_NAME "ems_pci"
21
22 MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
23 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
24 MODULE_LICENSE("GPL v2");
25
26 #define EMS_PCI_V1_MAX_CHAN 2
27 #define EMS_PCI_V2_MAX_CHAN 4
28 #define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN
29
30 struct ems_pci_card {
31 int version;
32 int channels;
33
34 struct pci_dev *pci_dev;
35 struct net_device *net_dev[EMS_PCI_MAX_CHAN];
36
37 void __iomem *conf_addr;
38 void __iomem *base_addr;
39 };
40
41 #define EMS_PCI_CAN_CLOCK (16000000 / 2)
42
43 /*
44 * Register definitions and descriptions are from LinCAN 0.3.3.
45 *
46 * PSB4610 PITA-2 bridge control registers
47 */
48 #define PITA2_ICR 0x00 /* Interrupt Control Register */
49 #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
50 #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
51
52 #define PITA2_MISC 0x1c /* Miscellaneous Register */
53 #define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
54
55 /*
56 * Register definitions for the PLX 9030
57 */
58 #define PLX_ICSR 0x4c /* Interrupt Control/Status register */
59 #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
60 #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
61 #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
62 #define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
63 PLX_ICSR_LINTI1_CLR)
64
65 /*
66 * The board configuration is probably following:
67 * RX1 is connected to ground.
68 * TX1 is not connected.
69 * CLKO is not connected.
70 * Setting the OCR register to 0xDA is a good idea.
71 * This means normal output mode, push-pull and the correct polarity.
72 */
73 #define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
74
75 /*
76 * In the CDR register, you should set CBP to 1.
77 * You will probably also want to set the clock divider value to 7
78 * (meaning direct oscillator output) because the second SJA1000 chip
79 * is driven by the first one CLKOUT output.
80 */
81 #define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
82
83 #define EMS_PCI_V1_BASE_BAR 1
84 #define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */
85 #define EMS_PCI_V2_BASE_BAR 2
86 #define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */
87 #define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
88 #define EMS_PCI_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
89
90 #define EMS_PCI_BASE_SIZE 4096 /* size of controller area */
91
92 static const struct pci_device_id ems_pci_tbl[] = {
93 /* CPC-PCI v1 */
94 {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
95 /* CPC-PCI v2 */
96 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
97 /* CPC-104P v2 */
98 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
99 {0,}
100 };
101 MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
102
103 /*
104 * Helper to read internal registers from card logic (not CAN)
105 */
ems_pci_v1_readb(struct ems_pci_card * card,unsigned int port)106 static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
107 {
108 return readb(card->base_addr + (port * 4));
109 }
110
ems_pci_v1_read_reg(const struct sja1000_priv * priv,int port)111 static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
112 {
113 return readb(priv->reg_base + (port * 4));
114 }
115
ems_pci_v1_write_reg(const struct sja1000_priv * priv,int port,u8 val)116 static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
117 int port, u8 val)
118 {
119 writeb(val, priv->reg_base + (port * 4));
120 }
121
ems_pci_v1_post_irq(const struct sja1000_priv * priv)122 static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
123 {
124 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
125
126 /* reset int flag of pita */
127 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
128 card->conf_addr + PITA2_ICR);
129 }
130
ems_pci_v2_read_reg(const struct sja1000_priv * priv,int port)131 static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
132 {
133 return readb(priv->reg_base + port);
134 }
135
ems_pci_v2_write_reg(const struct sja1000_priv * priv,int port,u8 val)136 static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
137 int port, u8 val)
138 {
139 writeb(val, priv->reg_base + port);
140 }
141
ems_pci_v2_post_irq(const struct sja1000_priv * priv)142 static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
143 {
144 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
145
146 writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
147 }
148
149 /*
150 * Check if a CAN controller is present at the specified location
151 * by trying to set 'em into the PeliCAN mode
152 */
ems_pci_check_chan(const struct sja1000_priv * priv)153 static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
154 {
155 unsigned char res;
156
157 /* Make sure SJA1000 is in reset mode */
158 priv->write_reg(priv, SJA1000_MOD, 1);
159
160 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
161
162 /* read reset-values */
163 res = priv->read_reg(priv, SJA1000_CDR);
164
165 if (res == CDR_PELICAN)
166 return 1;
167
168 return 0;
169 }
170
ems_pci_del_card(struct pci_dev * pdev)171 static void ems_pci_del_card(struct pci_dev *pdev)
172 {
173 struct ems_pci_card *card = pci_get_drvdata(pdev);
174 struct net_device *dev;
175 int i = 0;
176
177 for (i = 0; i < card->channels; i++) {
178 dev = card->net_dev[i];
179
180 if (!dev)
181 continue;
182
183 dev_info(&pdev->dev, "Removing %s.\n", dev->name);
184 unregister_sja1000dev(dev);
185 free_sja1000dev(dev);
186 }
187
188 if (card->base_addr != NULL)
189 pci_iounmap(card->pci_dev, card->base_addr);
190
191 if (card->conf_addr != NULL)
192 pci_iounmap(card->pci_dev, card->conf_addr);
193
194 kfree(card);
195
196 pci_disable_device(pdev);
197 }
198
ems_pci_card_reset(struct ems_pci_card * card)199 static void ems_pci_card_reset(struct ems_pci_card *card)
200 {
201 /* Request board reset */
202 writeb(0, card->base_addr);
203 }
204
205 /*
206 * Probe PCI device for EMS CAN signature and register each available
207 * CAN channel to SJA1000 Socket-CAN subsystem.
208 */
ems_pci_add_card(struct pci_dev * pdev,const struct pci_device_id * ent)209 static int ems_pci_add_card(struct pci_dev *pdev,
210 const struct pci_device_id *ent)
211 {
212 struct sja1000_priv *priv;
213 struct net_device *dev;
214 struct ems_pci_card *card;
215 int max_chan, conf_size, base_bar;
216 int err, i;
217
218 /* Enabling PCI device */
219 if (pci_enable_device(pdev) < 0) {
220 dev_err(&pdev->dev, "Enabling PCI device failed\n");
221 return -ENODEV;
222 }
223
224 /* Allocating card structures to hold addresses, ... */
225 card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
226 if (card == NULL) {
227 pci_disable_device(pdev);
228 return -ENOMEM;
229 }
230
231 pci_set_drvdata(pdev, card);
232
233 card->pci_dev = pdev;
234
235 card->channels = 0;
236
237 if (pdev->vendor == PCI_VENDOR_ID_PLX) {
238 card->version = 2; /* CPC-PCI v2 */
239 max_chan = EMS_PCI_V2_MAX_CHAN;
240 base_bar = EMS_PCI_V2_BASE_BAR;
241 conf_size = EMS_PCI_V2_CONF_SIZE;
242 } else {
243 card->version = 1; /* CPC-PCI v1 */
244 max_chan = EMS_PCI_V1_MAX_CHAN;
245 base_bar = EMS_PCI_V1_BASE_BAR;
246 conf_size = EMS_PCI_V1_CONF_SIZE;
247 }
248
249 /* Remap configuration space and controller memory area */
250 card->conf_addr = pci_iomap(pdev, 0, conf_size);
251 if (card->conf_addr == NULL) {
252 err = -ENOMEM;
253 goto failure_cleanup;
254 }
255
256 card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
257 if (card->base_addr == NULL) {
258 err = -ENOMEM;
259 goto failure_cleanup;
260 }
261
262 if (card->version == 1) {
263 /* Configure PITA-2 parallel interface (enable MUX) */
264 writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
265
266 /* Check for unique EMS CAN signature */
267 if (ems_pci_v1_readb(card, 0) != 0x55 ||
268 ems_pci_v1_readb(card, 1) != 0xAA ||
269 ems_pci_v1_readb(card, 2) != 0x01 ||
270 ems_pci_v1_readb(card, 3) != 0xCB ||
271 ems_pci_v1_readb(card, 4) != 0x11) {
272 dev_err(&pdev->dev,
273 "Not EMS Dr. Thomas Wuensche interface\n");
274 err = -ENODEV;
275 goto failure_cleanup;
276 }
277 }
278
279 ems_pci_card_reset(card);
280
281 /* Detect available channels */
282 for (i = 0; i < max_chan; i++) {
283 dev = alloc_sja1000dev(0);
284 if (dev == NULL) {
285 err = -ENOMEM;
286 goto failure_cleanup;
287 }
288
289 card->net_dev[i] = dev;
290 priv = netdev_priv(dev);
291 priv->priv = card;
292 priv->irq_flags = IRQF_SHARED;
293
294 dev->irq = pdev->irq;
295 priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
296 + (i * EMS_PCI_CAN_CTRL_SIZE);
297 if (card->version == 1) {
298 priv->read_reg = ems_pci_v1_read_reg;
299 priv->write_reg = ems_pci_v1_write_reg;
300 priv->post_irq = ems_pci_v1_post_irq;
301 } else {
302 priv->read_reg = ems_pci_v2_read_reg;
303 priv->write_reg = ems_pci_v2_write_reg;
304 priv->post_irq = ems_pci_v2_post_irq;
305 }
306
307 /* Check if channel is present */
308 if (ems_pci_check_chan(priv)) {
309 priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
310 priv->ocr = EMS_PCI_OCR;
311 priv->cdr = EMS_PCI_CDR;
312
313 SET_NETDEV_DEV(dev, &pdev->dev);
314 dev->dev_id = i;
315
316 if (card->version == 1)
317 /* reset int flag of pita */
318 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
319 card->conf_addr + PITA2_ICR);
320 else
321 /* enable IRQ in PLX 9030 */
322 writel(PLX_ICSR_ENA_CLR,
323 card->conf_addr + PLX_ICSR);
324
325 /* Register SJA1000 device */
326 err = register_sja1000dev(dev);
327 if (err) {
328 dev_err(&pdev->dev, "Registering device failed "
329 "(err=%d)\n", err);
330 free_sja1000dev(dev);
331 goto failure_cleanup;
332 }
333
334 card->channels++;
335
336 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
337 i + 1, priv->reg_base, dev->irq);
338 } else {
339 free_sja1000dev(dev);
340 }
341 }
342
343 return 0;
344
345 failure_cleanup:
346 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
347
348 ems_pci_del_card(pdev);
349
350 return err;
351 }
352
353 static struct pci_driver ems_pci_driver = {
354 .name = DRV_NAME,
355 .id_table = ems_pci_tbl,
356 .probe = ems_pci_add_card,
357 .remove = ems_pci_del_card,
358 };
359
360 module_pci_driver(ems_pci_driver);
361