1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2021 Maxlinear Corporation
3 * Copyright (C) 2020 Intel Corporation
4 *
5 * Drivers for Maxlinear Ethernet GPY
6 *
7 */
8
9 #include <linux/module.h>
10 #include <linux/bitfield.h>
11 #include <linux/hwmon.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/polynomial.h>
15 #include <linux/netdevice.h>
16
17 /* PHY ID */
18 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC
19 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9
20 #define PHY_ID_GPY2xx 0x67C9DC00
21 #define PHY_ID_GPY115B 0x67C9DF00
22 #define PHY_ID_GPY115C 0x67C9DF10
23 #define PHY_ID_GPY211B 0x67C9DE08
24 #define PHY_ID_GPY211C 0x67C9DE10
25 #define PHY_ID_GPY212B 0x67C9DE09
26 #define PHY_ID_GPY212C 0x67C9DE20
27 #define PHY_ID_GPY215B 0x67C9DF04
28 #define PHY_ID_GPY215C 0x67C9DF20
29 #define PHY_ID_GPY241B 0x67C9DE40
30 #define PHY_ID_GPY241BM 0x67C9DE80
31 #define PHY_ID_GPY245B 0x67C9DEC0
32
33 #define PHY_MIISTAT 0x18 /* MII state */
34 #define PHY_IMASK 0x19 /* interrupt mask */
35 #define PHY_ISTAT 0x1A /* interrupt status */
36 #define PHY_FWV 0x1E /* firmware version */
37
38 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
39 #define PHY_MIISTAT_DPX BIT(3)
40 #define PHY_MIISTAT_LS BIT(10)
41
42 #define PHY_MIISTAT_SPD_10 0
43 #define PHY_MIISTAT_SPD_100 1
44 #define PHY_MIISTAT_SPD_1000 2
45 #define PHY_MIISTAT_SPD_2500 4
46
47 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
48 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
49 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
50 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */
51 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */
52 #define PHY_IMASK_LSTC BIT(0) /* Link state change */
53 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \
54 PHY_IMASK_LSPC | \
55 PHY_IMASK_DXMC | \
56 PHY_IMASK_ADSC | \
57 PHY_IMASK_ANC)
58
59 #define PHY_FWV_REL_MASK BIT(15)
60 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8)
61 #define PHY_FWV_MINOR_MASK GENMASK(7, 0)
62
63 /* SGMII */
64 #define VSPEC1_SGMII_CTRL 0x08
65 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
66 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
67 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
68 VSPEC1_SGMII_CTRL_ANRS)
69
70 /* Temperature sensor */
71 #define VPSPEC1_TEMP_STA 0x0E
72 #define VPSPEC1_TEMP_STA_DATA GENMASK(9, 0)
73
74 /* Mailbox */
75 #define VSPEC1_MBOX_DATA 0x5
76 #define VSPEC1_MBOX_ADDRLO 0x6
77 #define VSPEC1_MBOX_CMD 0x7
78 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)
79 #define VSPEC1_MBOX_CMD_RD (0 << 8)
80 #define VSPEC1_MBOX_CMD_READY BIT(15)
81
82 /* WoL */
83 #define VPSPEC2_WOL_CTL 0x0E06
84 #define VPSPEC2_WOL_AD01 0x0E08
85 #define VPSPEC2_WOL_AD23 0x0E09
86 #define VPSPEC2_WOL_AD45 0x0E0A
87 #define WOL_EN BIT(0)
88
89 /* Internal registers, access via mbox */
90 #define REG_GPIO0_OUT 0xd3ce00
91
92 struct gpy_priv {
93 /* serialize mailbox acesses */
94 struct mutex mbox_lock;
95
96 u8 fw_major;
97 u8 fw_minor;
98 };
99
100 static const struct {
101 int major;
102 int minor;
103 } ver_need_sgmii_reaneg[] = {
104 {7, 0x6D},
105 {8, 0x6D},
106 {9, 0x73},
107 };
108
109 #if IS_ENABLED(CONFIG_HWMON)
110 /* The original translation formulae of the temperature (in degrees of Celsius)
111 * are as follows:
112 *
113 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
114 * 3.0762e-1*(N^1) + -5.2156e1
115 *
116 * where [-52.156, 137.961]C and N = [0, 1023].
117 *
118 * They must be accordingly altered to be suitable for the integer arithmetics.
119 * The technique is called 'factor redistribution', which just makes sure the
120 * multiplications and divisions are made so to have a result of the operations
121 * within the integer numbers limit. In addition we need to translate the
122 * formulae to accept millidegrees of Celsius. Here what it looks like after
123 * the alterations:
124 *
125 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
126 * 307620e-3*(N^1) + -52156
127 *
128 * where T = [-52156, 137961]mC and N = [0, 1023].
129 */
130 static const struct polynomial poly_N_to_temp = {
131 .terms = {
132 {4, -25761, 1000, 1},
133 {3, 97332, 1000, 1},
134 {2, -191650, 1000, 1},
135 {1, 307620, 1000, 1},
136 {0, -52156, 1, 1}
137 }
138 };
139
gpy_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)140 static int gpy_hwmon_read(struct device *dev,
141 enum hwmon_sensor_types type,
142 u32 attr, int channel, long *value)
143 {
144 struct phy_device *phydev = dev_get_drvdata(dev);
145 int ret;
146
147 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VPSPEC1_TEMP_STA);
148 if (ret < 0)
149 return ret;
150 if (!ret)
151 return -ENODATA;
152
153 *value = polynomial_calc(&poly_N_to_temp,
154 FIELD_GET(VPSPEC1_TEMP_STA_DATA, ret));
155
156 return 0;
157 }
158
gpy_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)159 static umode_t gpy_hwmon_is_visible(const void *data,
160 enum hwmon_sensor_types type,
161 u32 attr, int channel)
162 {
163 return 0444;
164 }
165
166 static const struct hwmon_channel_info *gpy_hwmon_info[] = {
167 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
168 NULL
169 };
170
171 static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
172 .is_visible = gpy_hwmon_is_visible,
173 .read = gpy_hwmon_read,
174 };
175
176 static const struct hwmon_chip_info gpy_hwmon_chip_info = {
177 .ops = &gpy_hwmon_hwmon_ops,
178 .info = gpy_hwmon_info,
179 };
180
gpy_hwmon_register(struct phy_device * phydev)181 static int gpy_hwmon_register(struct phy_device *phydev)
182 {
183 struct device *dev = &phydev->mdio.dev;
184 struct device *hwmon_dev;
185 char *hwmon_name;
186
187 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
188 if (IS_ERR(hwmon_name))
189 return PTR_ERR(hwmon_name);
190
191 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
192 phydev,
193 &gpy_hwmon_chip_info,
194 NULL);
195
196 return PTR_ERR_OR_ZERO(hwmon_dev);
197 }
198 #else
gpy_hwmon_register(struct phy_device * phydev)199 static int gpy_hwmon_register(struct phy_device *phydev)
200 {
201 return 0;
202 }
203 #endif
204
gpy_mbox_read(struct phy_device * phydev,u32 addr)205 static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
206 {
207 struct gpy_priv *priv = phydev->priv;
208 int val, ret;
209 u16 cmd;
210
211 mutex_lock(&priv->mbox_lock);
212
213 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
214 addr);
215 if (ret)
216 goto out;
217
218 cmd = VSPEC1_MBOX_CMD_RD;
219 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16);
220
221 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
222 if (ret)
223 goto out;
224
225 /* The mbox read is used in the interrupt workaround. It was observed
226 * that a read might take up to 2.5ms. This is also the time for which
227 * the interrupt line is stuck low. To be on the safe side, poll the
228 * ready bit for 10ms.
229 */
230 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
231 VSPEC1_MBOX_CMD, val,
232 (val & VSPEC1_MBOX_CMD_READY),
233 500, 10000, false);
234 if (ret)
235 goto out;
236
237 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
238
239 out:
240 mutex_unlock(&priv->mbox_lock);
241 return ret;
242 }
243
gpy_config_init(struct phy_device * phydev)244 static int gpy_config_init(struct phy_device *phydev)
245 {
246 int ret;
247
248 /* Mask all interrupts */
249 ret = phy_write(phydev, PHY_IMASK, 0);
250 if (ret)
251 return ret;
252
253 /* Clear all pending interrupts */
254 ret = phy_read(phydev, PHY_ISTAT);
255 return ret < 0 ? ret : 0;
256 }
257
gpy_has_broken_mdint(struct phy_device * phydev)258 static bool gpy_has_broken_mdint(struct phy_device *phydev)
259 {
260 /* At least these PHYs are known to have broken interrupt handling */
261 return phydev->drv->phy_id == PHY_ID_GPY215B ||
262 phydev->drv->phy_id == PHY_ID_GPY215C;
263 }
264
gpy_probe(struct phy_device * phydev)265 static int gpy_probe(struct phy_device *phydev)
266 {
267 struct device *dev = &phydev->mdio.dev;
268 struct gpy_priv *priv;
269 int fw_version;
270 int ret;
271
272 if (!phydev->is_c45) {
273 ret = phy_get_c45_ids(phydev);
274 if (ret < 0)
275 return ret;
276 }
277
278 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
279 if (!priv)
280 return -ENOMEM;
281 phydev->priv = priv;
282 mutex_init(&priv->mbox_lock);
283
284 fw_version = phy_read(phydev, PHY_FWV);
285 if (fw_version < 0)
286 return fw_version;
287 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version);
288 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
289
290 ret = gpy_hwmon_register(phydev);
291 if (ret)
292 return ret;
293
294 /* Show GPY PHY FW version in dmesg */
295 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
296 priv->fw_major, priv->fw_minor, fw_version,
297 fw_version & PHY_FWV_REL_MASK ? "" : " test version");
298
299 return 0;
300 }
301
gpy_sgmii_need_reaneg(struct phy_device * phydev)302 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
303 {
304 struct gpy_priv *priv = phydev->priv;
305 size_t i;
306
307 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
308 if (priv->fw_major != ver_need_sgmii_reaneg[i].major)
309 continue;
310 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
311 return true;
312 break;
313 }
314
315 return false;
316 }
317
gpy_2500basex_chk(struct phy_device * phydev)318 static bool gpy_2500basex_chk(struct phy_device *phydev)
319 {
320 int ret;
321
322 ret = phy_read(phydev, PHY_MIISTAT);
323 if (ret < 0) {
324 phydev_err(phydev, "Error: MDIO register access failed: %d\n",
325 ret);
326 return false;
327 }
328
329 if (!(ret & PHY_MIISTAT_LS) ||
330 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
331 return false;
332
333 phydev->speed = SPEED_2500;
334 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
335 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
336 VSPEC1_SGMII_CTRL_ANEN, 0);
337 return true;
338 }
339
gpy_sgmii_aneg_en(struct phy_device * phydev)340 static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
341 {
342 int ret;
343
344 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
345 if (ret < 0) {
346 phydev_err(phydev, "Error: MMD register access failed: %d\n",
347 ret);
348 return true;
349 }
350
351 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
352 }
353
gpy_config_aneg(struct phy_device * phydev)354 static int gpy_config_aneg(struct phy_device *phydev)
355 {
356 bool changed = false;
357 u32 adv;
358 int ret;
359
360 if (phydev->autoneg == AUTONEG_DISABLE) {
361 /* Configure half duplex with genphy_setup_forced,
362 * because genphy_c45_pma_setup_forced does not support.
363 */
364 return phydev->duplex != DUPLEX_FULL
365 ? genphy_setup_forced(phydev)
366 : genphy_c45_pma_setup_forced(phydev);
367 }
368
369 ret = genphy_c45_an_config_aneg(phydev);
370 if (ret < 0)
371 return ret;
372 if (ret > 0)
373 changed = true;
374
375 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
376 ret = phy_modify_changed(phydev, MII_CTRL1000,
377 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
378 adv);
379 if (ret < 0)
380 return ret;
381 if (ret > 0)
382 changed = true;
383
384 ret = genphy_c45_check_and_restart_aneg(phydev, changed);
385 if (ret < 0)
386 return ret;
387
388 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
389 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
390 return 0;
391
392 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
393 * disabled.
394 */
395 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
396 !gpy_sgmii_aneg_en(phydev))
397 return 0;
398
399 /* There is a design constraint in GPY2xx device where SGMII AN is
400 * only triggered when there is change of speed. If, PHY link
401 * partner`s speed is still same even after PHY TPI is down and up
402 * again, SGMII AN is not triggered and hence no new in-band message
403 * from GPY to MAC side SGMII.
404 * This could cause an issue during power up, when PHY is up prior to
405 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
406 * wouldn`t receive new in-band message from GPY with correct link
407 * status, speed and duplex info.
408 *
409 * 1) If PHY is already up and TPI link status is still down (such as
410 * hard reboot), TPI link status is polled for 4 seconds before
411 * retriggerring SGMII AN.
412 * 2) If PHY is already up and TPI link status is also up (such as soft
413 * reboot), polling of TPI link status is not needed and SGMII AN is
414 * immediately retriggered.
415 * 3) Other conditions such as PHY is down, speed change etc, skip
416 * retriggering SGMII AN. Note: in case of speed change, GPY FW will
417 * initiate SGMII AN.
418 */
419
420 if (phydev->state != PHY_UP)
421 return 0;
422
423 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
424 20000, 4000000, false);
425 if (ret == -ETIMEDOUT)
426 return 0;
427 else if (ret < 0)
428 return ret;
429
430 /* Trigger SGMII AN. */
431 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
432 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
433 }
434
gpy_update_interface(struct phy_device * phydev)435 static void gpy_update_interface(struct phy_device *phydev)
436 {
437 int ret;
438
439 /* Interface mode is fixed for USXGMII and integrated PHY */
440 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
441 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
442 return;
443
444 /* Automatically switch SERDES interface between SGMII and 2500-BaseX
445 * according to speed. Disable ANEG in 2500-BaseX mode.
446 */
447 switch (phydev->speed) {
448 case SPEED_2500:
449 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
450 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
451 VSPEC1_SGMII_CTRL_ANEN, 0);
452 if (ret < 0)
453 phydev_err(phydev,
454 "Error: Disable of SGMII ANEG failed: %d\n",
455 ret);
456 break;
457 case SPEED_1000:
458 case SPEED_100:
459 case SPEED_10:
460 phydev->interface = PHY_INTERFACE_MODE_SGMII;
461 if (gpy_sgmii_aneg_en(phydev))
462 break;
463 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
464 * if ANEG is disabled (in 2500-BaseX mode).
465 */
466 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
467 VSPEC1_SGMII_ANEN_ANRS,
468 VSPEC1_SGMII_ANEN_ANRS);
469 if (ret < 0)
470 phydev_err(phydev,
471 "Error: Enable of SGMII ANEG failed: %d\n",
472 ret);
473 break;
474 }
475
476 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000)
477 genphy_read_master_slave(phydev);
478 }
479
gpy_read_status(struct phy_device * phydev)480 static int gpy_read_status(struct phy_device *phydev)
481 {
482 int ret;
483
484 ret = genphy_update_link(phydev);
485 if (ret)
486 return ret;
487
488 phydev->speed = SPEED_UNKNOWN;
489 phydev->duplex = DUPLEX_UNKNOWN;
490 phydev->pause = 0;
491 phydev->asym_pause = 0;
492
493 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
494 ret = genphy_c45_read_lpa(phydev);
495 if (ret < 0)
496 return ret;
497
498 /* Read the link partner's 1G advertisement */
499 ret = phy_read(phydev, MII_STAT1000);
500 if (ret < 0)
501 return ret;
502 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
503 } else if (phydev->autoneg == AUTONEG_DISABLE) {
504 linkmode_zero(phydev->lp_advertising);
505 }
506
507 ret = phy_read(phydev, PHY_MIISTAT);
508 if (ret < 0)
509 return ret;
510
511 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
512 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
513 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
514 case PHY_MIISTAT_SPD_10:
515 phydev->speed = SPEED_10;
516 break;
517 case PHY_MIISTAT_SPD_100:
518 phydev->speed = SPEED_100;
519 break;
520 case PHY_MIISTAT_SPD_1000:
521 phydev->speed = SPEED_1000;
522 break;
523 case PHY_MIISTAT_SPD_2500:
524 phydev->speed = SPEED_2500;
525 break;
526 }
527
528 if (phydev->link)
529 gpy_update_interface(phydev);
530
531 return 0;
532 }
533
gpy_config_intr(struct phy_device * phydev)534 static int gpy_config_intr(struct phy_device *phydev)
535 {
536 u16 mask = 0;
537
538 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
539 mask = PHY_IMASK_MASK;
540
541 return phy_write(phydev, PHY_IMASK, mask);
542 }
543
gpy_handle_interrupt(struct phy_device * phydev)544 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
545 {
546 int reg;
547
548 reg = phy_read(phydev, PHY_ISTAT);
549 if (reg < 0) {
550 phy_error(phydev);
551 return IRQ_NONE;
552 }
553
554 if (!(reg & PHY_IMASK_MASK))
555 return IRQ_NONE;
556
557 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT
558 * is read. To avoid interrupt storms, delay the interrupt handling as
559 * long as the PHY drives the interrupt line. An internal bus read will
560 * stall as long as the interrupt line is asserted, thus just read a
561 * random register here.
562 * Because we cannot access the internal bus at all while the interrupt
563 * is driven by the PHY, there is no way to make the interrupt line
564 * unstuck (e.g. by changing the pinmux to GPIO input) during that time
565 * frame. Therefore, polling is the best we can do and won't do any more
566 * harm.
567 * It was observed that this bug happens on link state and link speed
568 * changes on a GPY215B and GYP215C independent of the firmware version
569 * (which doesn't mean that this list is exhaustive).
570 */
571 if (gpy_has_broken_mdint(phydev) &&
572 (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC))) {
573 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
574 if (reg < 0) {
575 phy_error(phydev);
576 return IRQ_NONE;
577 }
578 }
579
580 phy_trigger_machine(phydev);
581
582 return IRQ_HANDLED;
583 }
584
gpy_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)585 static int gpy_set_wol(struct phy_device *phydev,
586 struct ethtool_wolinfo *wol)
587 {
588 struct net_device *attach_dev = phydev->attached_dev;
589 int ret;
590
591 if (wol->wolopts & WAKE_MAGIC) {
592 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
593 * VPSPEC2_WOL_AD45 = Byte0:Byte1
594 * VPSPEC2_WOL_AD23 = Byte2:Byte3
595 * VPSPEC2_WOL_AD01 = Byte4:Byte5
596 */
597 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
598 VPSPEC2_WOL_AD45,
599 ((attach_dev->dev_addr[0] << 8) |
600 attach_dev->dev_addr[1]));
601 if (ret < 0)
602 return ret;
603
604 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
605 VPSPEC2_WOL_AD23,
606 ((attach_dev->dev_addr[2] << 8) |
607 attach_dev->dev_addr[3]));
608 if (ret < 0)
609 return ret;
610
611 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
612 VPSPEC2_WOL_AD01,
613 ((attach_dev->dev_addr[4] << 8) |
614 attach_dev->dev_addr[5]));
615 if (ret < 0)
616 return ret;
617
618 /* Enable the WOL interrupt */
619 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
620 if (ret < 0)
621 return ret;
622
623 /* Enable magic packet matching */
624 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
625 VPSPEC2_WOL_CTL,
626 WOL_EN);
627 if (ret < 0)
628 return ret;
629
630 /* Clear the interrupt status register.
631 * Only WoL is enabled so clear all.
632 */
633 ret = phy_read(phydev, PHY_ISTAT);
634 if (ret < 0)
635 return ret;
636 } else {
637 /* Disable magic packet matching */
638 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
639 VPSPEC2_WOL_CTL,
640 WOL_EN);
641 if (ret < 0)
642 return ret;
643 }
644
645 if (wol->wolopts & WAKE_PHY) {
646 /* Enable the link state change interrupt */
647 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
648 if (ret < 0)
649 return ret;
650
651 /* Clear the interrupt status register */
652 ret = phy_read(phydev, PHY_ISTAT);
653 if (ret < 0)
654 return ret;
655
656 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
657 phy_trigger_machine(phydev);
658
659 return 0;
660 }
661
662 /* Disable the link state change interrupt */
663 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
664 }
665
gpy_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)666 static void gpy_get_wol(struct phy_device *phydev,
667 struct ethtool_wolinfo *wol)
668 {
669 int ret;
670
671 wol->supported = WAKE_MAGIC | WAKE_PHY;
672 wol->wolopts = 0;
673
674 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL);
675 if (ret & WOL_EN)
676 wol->wolopts |= WAKE_MAGIC;
677
678 ret = phy_read(phydev, PHY_IMASK);
679 if (ret & PHY_IMASK_LSTC)
680 wol->wolopts |= WAKE_PHY;
681 }
682
gpy_loopback(struct phy_device * phydev,bool enable)683 static int gpy_loopback(struct phy_device *phydev, bool enable)
684 {
685 int ret;
686
687 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
688 enable ? BMCR_LOOPBACK : 0);
689 if (!ret) {
690 /* It takes some time for PHY device to switch
691 * into/out-of loopback mode.
692 */
693 msleep(100);
694 }
695
696 return ret;
697 }
698
gpy115_loopback(struct phy_device * phydev,bool enable)699 static int gpy115_loopback(struct phy_device *phydev, bool enable)
700 {
701 struct gpy_priv *priv = phydev->priv;
702
703 if (enable)
704 return gpy_loopback(phydev, enable);
705
706 if (priv->fw_minor > 0x76)
707 return gpy_loopback(phydev, 0);
708
709 return genphy_soft_reset(phydev);
710 }
711
712 static struct phy_driver gpy_drivers[] = {
713 {
714 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
715 .name = "Maxlinear Ethernet GPY2xx",
716 .get_features = genphy_c45_pma_read_abilities,
717 .config_init = gpy_config_init,
718 .probe = gpy_probe,
719 .suspend = genphy_suspend,
720 .resume = genphy_resume,
721 .config_aneg = gpy_config_aneg,
722 .aneg_done = genphy_c45_aneg_done,
723 .read_status = gpy_read_status,
724 .config_intr = gpy_config_intr,
725 .handle_interrupt = gpy_handle_interrupt,
726 .set_wol = gpy_set_wol,
727 .get_wol = gpy_get_wol,
728 .set_loopback = gpy_loopback,
729 },
730 {
731 .phy_id = PHY_ID_GPY115B,
732 .phy_id_mask = PHY_ID_GPYx15B_MASK,
733 .name = "Maxlinear Ethernet GPY115B",
734 .get_features = genphy_c45_pma_read_abilities,
735 .config_init = gpy_config_init,
736 .probe = gpy_probe,
737 .suspend = genphy_suspend,
738 .resume = genphy_resume,
739 .config_aneg = gpy_config_aneg,
740 .aneg_done = genphy_c45_aneg_done,
741 .read_status = gpy_read_status,
742 .config_intr = gpy_config_intr,
743 .handle_interrupt = gpy_handle_interrupt,
744 .set_wol = gpy_set_wol,
745 .get_wol = gpy_get_wol,
746 .set_loopback = gpy115_loopback,
747 },
748 {
749 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
750 .name = "Maxlinear Ethernet GPY115C",
751 .get_features = genphy_c45_pma_read_abilities,
752 .config_init = gpy_config_init,
753 .probe = gpy_probe,
754 .suspend = genphy_suspend,
755 .resume = genphy_resume,
756 .config_aneg = gpy_config_aneg,
757 .aneg_done = genphy_c45_aneg_done,
758 .read_status = gpy_read_status,
759 .config_intr = gpy_config_intr,
760 .handle_interrupt = gpy_handle_interrupt,
761 .set_wol = gpy_set_wol,
762 .get_wol = gpy_get_wol,
763 .set_loopback = gpy115_loopback,
764 },
765 {
766 .phy_id = PHY_ID_GPY211B,
767 .phy_id_mask = PHY_ID_GPY21xB_MASK,
768 .name = "Maxlinear Ethernet GPY211B",
769 .get_features = genphy_c45_pma_read_abilities,
770 .config_init = gpy_config_init,
771 .probe = gpy_probe,
772 .suspend = genphy_suspend,
773 .resume = genphy_resume,
774 .config_aneg = gpy_config_aneg,
775 .aneg_done = genphy_c45_aneg_done,
776 .read_status = gpy_read_status,
777 .config_intr = gpy_config_intr,
778 .handle_interrupt = gpy_handle_interrupt,
779 .set_wol = gpy_set_wol,
780 .get_wol = gpy_get_wol,
781 .set_loopback = gpy_loopback,
782 },
783 {
784 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
785 .name = "Maxlinear Ethernet GPY211C",
786 .get_features = genphy_c45_pma_read_abilities,
787 .config_init = gpy_config_init,
788 .probe = gpy_probe,
789 .suspend = genphy_suspend,
790 .resume = genphy_resume,
791 .config_aneg = gpy_config_aneg,
792 .aneg_done = genphy_c45_aneg_done,
793 .read_status = gpy_read_status,
794 .config_intr = gpy_config_intr,
795 .handle_interrupt = gpy_handle_interrupt,
796 .set_wol = gpy_set_wol,
797 .get_wol = gpy_get_wol,
798 .set_loopback = gpy_loopback,
799 },
800 {
801 .phy_id = PHY_ID_GPY212B,
802 .phy_id_mask = PHY_ID_GPY21xB_MASK,
803 .name = "Maxlinear Ethernet GPY212B",
804 .get_features = genphy_c45_pma_read_abilities,
805 .config_init = gpy_config_init,
806 .probe = gpy_probe,
807 .suspend = genphy_suspend,
808 .resume = genphy_resume,
809 .config_aneg = gpy_config_aneg,
810 .aneg_done = genphy_c45_aneg_done,
811 .read_status = gpy_read_status,
812 .config_intr = gpy_config_intr,
813 .handle_interrupt = gpy_handle_interrupt,
814 .set_wol = gpy_set_wol,
815 .get_wol = gpy_get_wol,
816 .set_loopback = gpy_loopback,
817 },
818 {
819 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
820 .name = "Maxlinear Ethernet GPY212C",
821 .get_features = genphy_c45_pma_read_abilities,
822 .config_init = gpy_config_init,
823 .probe = gpy_probe,
824 .suspend = genphy_suspend,
825 .resume = genphy_resume,
826 .config_aneg = gpy_config_aneg,
827 .aneg_done = genphy_c45_aneg_done,
828 .read_status = gpy_read_status,
829 .config_intr = gpy_config_intr,
830 .handle_interrupt = gpy_handle_interrupt,
831 .set_wol = gpy_set_wol,
832 .get_wol = gpy_get_wol,
833 .set_loopback = gpy_loopback,
834 },
835 {
836 .phy_id = PHY_ID_GPY215B,
837 .phy_id_mask = PHY_ID_GPYx15B_MASK,
838 .name = "Maxlinear Ethernet GPY215B",
839 .get_features = genphy_c45_pma_read_abilities,
840 .config_init = gpy_config_init,
841 .probe = gpy_probe,
842 .suspend = genphy_suspend,
843 .resume = genphy_resume,
844 .config_aneg = gpy_config_aneg,
845 .aneg_done = genphy_c45_aneg_done,
846 .read_status = gpy_read_status,
847 .config_intr = gpy_config_intr,
848 .handle_interrupt = gpy_handle_interrupt,
849 .set_wol = gpy_set_wol,
850 .get_wol = gpy_get_wol,
851 .set_loopback = gpy_loopback,
852 },
853 {
854 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
855 .name = "Maxlinear Ethernet GPY215C",
856 .get_features = genphy_c45_pma_read_abilities,
857 .config_init = gpy_config_init,
858 .probe = gpy_probe,
859 .suspend = genphy_suspend,
860 .resume = genphy_resume,
861 .config_aneg = gpy_config_aneg,
862 .aneg_done = genphy_c45_aneg_done,
863 .read_status = gpy_read_status,
864 .config_intr = gpy_config_intr,
865 .handle_interrupt = gpy_handle_interrupt,
866 .set_wol = gpy_set_wol,
867 .get_wol = gpy_get_wol,
868 .set_loopback = gpy_loopback,
869 },
870 {
871 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
872 .name = "Maxlinear Ethernet GPY241B",
873 .get_features = genphy_c45_pma_read_abilities,
874 .config_init = gpy_config_init,
875 .probe = gpy_probe,
876 .suspend = genphy_suspend,
877 .resume = genphy_resume,
878 .config_aneg = gpy_config_aneg,
879 .aneg_done = genphy_c45_aneg_done,
880 .read_status = gpy_read_status,
881 .config_intr = gpy_config_intr,
882 .handle_interrupt = gpy_handle_interrupt,
883 .set_wol = gpy_set_wol,
884 .get_wol = gpy_get_wol,
885 .set_loopback = gpy_loopback,
886 },
887 {
888 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
889 .name = "Maxlinear Ethernet GPY241BM",
890 .get_features = genphy_c45_pma_read_abilities,
891 .config_init = gpy_config_init,
892 .probe = gpy_probe,
893 .suspend = genphy_suspend,
894 .resume = genphy_resume,
895 .config_aneg = gpy_config_aneg,
896 .aneg_done = genphy_c45_aneg_done,
897 .read_status = gpy_read_status,
898 .config_intr = gpy_config_intr,
899 .handle_interrupt = gpy_handle_interrupt,
900 .set_wol = gpy_set_wol,
901 .get_wol = gpy_get_wol,
902 .set_loopback = gpy_loopback,
903 },
904 {
905 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
906 .name = "Maxlinear Ethernet GPY245B",
907 .get_features = genphy_c45_pma_read_abilities,
908 .config_init = gpy_config_init,
909 .probe = gpy_probe,
910 .suspend = genphy_suspend,
911 .resume = genphy_resume,
912 .config_aneg = gpy_config_aneg,
913 .aneg_done = genphy_c45_aneg_done,
914 .read_status = gpy_read_status,
915 .config_intr = gpy_config_intr,
916 .handle_interrupt = gpy_handle_interrupt,
917 .set_wol = gpy_set_wol,
918 .get_wol = gpy_get_wol,
919 .set_loopback = gpy_loopback,
920 },
921 };
922 module_phy_driver(gpy_drivers);
923
924 static struct mdio_device_id __maybe_unused gpy_tbl[] = {
925 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
926 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
927 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
928 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
929 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
930 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
931 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
932 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
933 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
934 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
935 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
936 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
937 { }
938 };
939 MODULE_DEVICE_TABLE(mdio, gpy_tbl);
940
941 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
942 MODULE_AUTHOR("Xu Liang");
943 MODULE_LICENSE("GPL");
944