1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014-2017 Broadcom
3
4 /*
5 * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
6 * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
7 * pull up/down, slew and drive strength are also supported in this driver.
8 *
9 * Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
10 * through the interaction with the NSP IOMUX controller.
11 */
12
13 #include <linux/gpio/driver.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/kernel.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/slab.h>
25
26 #include "../pinctrl-utils.h"
27
28 #define NSP_CHIP_A_INT_STATUS 0x00
29 #define NSP_CHIP_A_INT_MASK 0x04
30 #define NSP_GPIO_DATA_IN 0x40
31 #define NSP_GPIO_DATA_OUT 0x44
32 #define NSP_GPIO_OUT_EN 0x48
33 #define NSP_GPIO_INT_POLARITY 0x50
34 #define NSP_GPIO_INT_MASK 0x54
35 #define NSP_GPIO_EVENT 0x58
36 #define NSP_GPIO_EVENT_INT_MASK 0x5c
37 #define NSP_GPIO_EVENT_INT_POLARITY 0x64
38 #define NSP_CHIP_A_GPIO_INT_BIT 0x01
39
40 /* I/O parameters offset for chipcommon A GPIO */
41 #define NSP_GPIO_DRV_CTRL 0x00
42 #define NSP_GPIO_HYSTERESIS_EN 0x10
43 #define NSP_GPIO_SLEW_RATE_EN 0x14
44 #define NSP_PULL_UP_EN 0x18
45 #define NSP_PULL_DOWN_EN 0x1c
46 #define GPIO_DRV_STRENGTH_BITS 0x03
47
48 /*
49 * nsp GPIO core
50 *
51 * @dev: pointer to device
52 * @base: I/O register base for nsp GPIO controller
53 * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
54 * @gc: GPIO chip
55 * @pctl: pointer to pinctrl_dev
56 * @pctldesc: pinctrl descriptor
57 * @lock: lock to protect access to I/O registers
58 */
59 struct nsp_gpio {
60 struct device *dev;
61 void __iomem *base;
62 void __iomem *io_ctrl;
63 struct irq_chip irqchip;
64 struct gpio_chip gc;
65 struct pinctrl_dev *pctl;
66 struct pinctrl_desc pctldesc;
67 raw_spinlock_t lock;
68 };
69
70 enum base_type {
71 REG,
72 IO_CTRL
73 };
74
75 /*
76 * Mapping from PINCONF pins to GPIO pins is 1-to-1
77 */
nsp_pin_to_gpio(unsigned pin)78 static inline unsigned nsp_pin_to_gpio(unsigned pin)
79 {
80 return pin;
81 }
82
83 /*
84 * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
85 * nsp GPIO register
86 *
87 * @nsp_gpio: nsp GPIO device
88 * @base_type: reg base to modify
89 * @reg: register offset
90 * @gpio: GPIO pin
91 * @set: set or clear
92 */
nsp_set_bit(struct nsp_gpio * chip,enum base_type address,unsigned int reg,unsigned gpio,bool set)93 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
94 unsigned int reg, unsigned gpio, bool set)
95 {
96 u32 val;
97 void __iomem *base_address;
98
99 if (address == IO_CTRL)
100 base_address = chip->io_ctrl;
101 else
102 base_address = chip->base;
103
104 val = readl(base_address + reg);
105 if (set)
106 val |= BIT(gpio);
107 else
108 val &= ~BIT(gpio);
109
110 writel(val, base_address + reg);
111 }
112
113 /*
114 * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
115 * nsp GPIO register
116 */
nsp_get_bit(struct nsp_gpio * chip,enum base_type address,unsigned int reg,unsigned gpio)117 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
118 unsigned int reg, unsigned gpio)
119 {
120 if (address == IO_CTRL)
121 return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
122 else
123 return !!(readl(chip->base + reg) & BIT(gpio));
124 }
125
nsp_gpio_irq_handler(int irq,void * data)126 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
127 {
128 struct gpio_chip *gc = (struct gpio_chip *)data;
129 struct nsp_gpio *chip = gpiochip_get_data(gc);
130 int bit;
131 unsigned long int_bits = 0;
132 u32 int_status;
133
134 /* go through the entire GPIOs and handle all interrupts */
135 int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
136 if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
137 unsigned int event, level;
138
139 /* Get level and edge interrupts */
140 event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
141 readl(chip->base + NSP_GPIO_EVENT);
142 level = readl(chip->base + NSP_GPIO_DATA_IN) ^
143 readl(chip->base + NSP_GPIO_INT_POLARITY);
144 level &= readl(chip->base + NSP_GPIO_INT_MASK);
145 int_bits = level | event;
146
147 for_each_set_bit(bit, &int_bits, gc->ngpio)
148 generic_handle_domain_irq(gc->irq.domain, bit);
149 }
150
151 return int_bits ? IRQ_HANDLED : IRQ_NONE;
152 }
153
nsp_gpio_irq_ack(struct irq_data * d)154 static void nsp_gpio_irq_ack(struct irq_data *d)
155 {
156 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
157 struct nsp_gpio *chip = gpiochip_get_data(gc);
158 unsigned gpio = d->hwirq;
159 u32 val = BIT(gpio);
160 u32 trigger_type;
161
162 trigger_type = irq_get_trigger_type(d->irq);
163 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
164 writel(val, chip->base + NSP_GPIO_EVENT);
165 }
166
167 /*
168 * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
169 *
170 * @d: IRQ chip data
171 * @unmask: mask/unmask GPIO interrupt
172 */
nsp_gpio_irq_set_mask(struct irq_data * d,bool unmask)173 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
174 {
175 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
176 struct nsp_gpio *chip = gpiochip_get_data(gc);
177 unsigned gpio = d->hwirq;
178 u32 trigger_type;
179
180 trigger_type = irq_get_trigger_type(d->irq);
181 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
182 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
183 else
184 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
185 }
186
nsp_gpio_irq_mask(struct irq_data * d)187 static void nsp_gpio_irq_mask(struct irq_data *d)
188 {
189 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
190 struct nsp_gpio *chip = gpiochip_get_data(gc);
191 unsigned long flags;
192
193 raw_spin_lock_irqsave(&chip->lock, flags);
194 nsp_gpio_irq_set_mask(d, false);
195 raw_spin_unlock_irqrestore(&chip->lock, flags);
196 }
197
nsp_gpio_irq_unmask(struct irq_data * d)198 static void nsp_gpio_irq_unmask(struct irq_data *d)
199 {
200 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
201 struct nsp_gpio *chip = gpiochip_get_data(gc);
202 unsigned long flags;
203
204 raw_spin_lock_irqsave(&chip->lock, flags);
205 nsp_gpio_irq_set_mask(d, true);
206 raw_spin_unlock_irqrestore(&chip->lock, flags);
207 }
208
nsp_gpio_irq_set_type(struct irq_data * d,unsigned int type)209 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
210 {
211 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
212 struct nsp_gpio *chip = gpiochip_get_data(gc);
213 unsigned gpio = d->hwirq;
214 bool level_low;
215 bool falling;
216 unsigned long flags;
217
218 raw_spin_lock_irqsave(&chip->lock, flags);
219 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
220 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
221
222 switch (type & IRQ_TYPE_SENSE_MASK) {
223 case IRQ_TYPE_EDGE_RISING:
224 falling = false;
225 break;
226
227 case IRQ_TYPE_EDGE_FALLING:
228 falling = true;
229 break;
230
231 case IRQ_TYPE_LEVEL_HIGH:
232 level_low = false;
233 break;
234
235 case IRQ_TYPE_LEVEL_LOW:
236 level_low = true;
237 break;
238
239 default:
240 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
241 type);
242 raw_spin_unlock_irqrestore(&chip->lock, flags);
243 return -EINVAL;
244 }
245
246 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
247 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
248
249 if (type & IRQ_TYPE_EDGE_BOTH)
250 irq_set_handler_locked(d, handle_edge_irq);
251 else
252 irq_set_handler_locked(d, handle_level_irq);
253
254 raw_spin_unlock_irqrestore(&chip->lock, flags);
255
256 dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
257 level_low ? "true" : "false", falling ? "true" : "false");
258 return 0;
259 }
260
nsp_gpio_direction_input(struct gpio_chip * gc,unsigned gpio)261 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
262 {
263 struct nsp_gpio *chip = gpiochip_get_data(gc);
264 unsigned long flags;
265
266 raw_spin_lock_irqsave(&chip->lock, flags);
267 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
268 raw_spin_unlock_irqrestore(&chip->lock, flags);
269
270 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
271 return 0;
272 }
273
nsp_gpio_direction_output(struct gpio_chip * gc,unsigned gpio,int val)274 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
275 int val)
276 {
277 struct nsp_gpio *chip = gpiochip_get_data(gc);
278 unsigned long flags;
279
280 raw_spin_lock_irqsave(&chip->lock, flags);
281 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
282 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
283 raw_spin_unlock_irqrestore(&chip->lock, flags);
284
285 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
286 return 0;
287 }
288
nsp_gpio_get_direction(struct gpio_chip * gc,unsigned gpio)289 static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
290 {
291 struct nsp_gpio *chip = gpiochip_get_data(gc);
292 unsigned long flags;
293 int val;
294
295 raw_spin_lock_irqsave(&chip->lock, flags);
296 val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
297 raw_spin_unlock_irqrestore(&chip->lock, flags);
298
299 return !val;
300 }
301
nsp_gpio_set(struct gpio_chip * gc,unsigned gpio,int val)302 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
303 {
304 struct nsp_gpio *chip = gpiochip_get_data(gc);
305 unsigned long flags;
306
307 raw_spin_lock_irqsave(&chip->lock, flags);
308 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
309 raw_spin_unlock_irqrestore(&chip->lock, flags);
310
311 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
312 }
313
nsp_gpio_get(struct gpio_chip * gc,unsigned gpio)314 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
315 {
316 struct nsp_gpio *chip = gpiochip_get_data(gc);
317
318 return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
319 }
320
nsp_get_groups_count(struct pinctrl_dev * pctldev)321 static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
322 {
323 return 1;
324 }
325
326 /*
327 * Only one group: "gpio_grp", since this local pinctrl device only performs
328 * GPIO specific PINCONF configurations
329 */
nsp_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)330 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
331 unsigned selector)
332 {
333 return "gpio_grp";
334 }
335
336 static const struct pinctrl_ops nsp_pctrl_ops = {
337 .get_groups_count = nsp_get_groups_count,
338 .get_group_name = nsp_get_group_name,
339 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
340 .dt_free_map = pinctrl_utils_free_map,
341 };
342
nsp_gpio_set_slew(struct nsp_gpio * chip,unsigned gpio,u32 slew)343 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
344 {
345 if (slew)
346 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
347 else
348 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
349
350 return 0;
351 }
352
nsp_gpio_set_pull(struct nsp_gpio * chip,unsigned gpio,bool pull_up,bool pull_down)353 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
354 bool pull_up, bool pull_down)
355 {
356 unsigned long flags;
357
358 raw_spin_lock_irqsave(&chip->lock, flags);
359 nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
360 nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
361 raw_spin_unlock_irqrestore(&chip->lock, flags);
362
363 dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
364 gpio, pull_up, pull_down);
365 return 0;
366 }
367
nsp_gpio_get_pull(struct nsp_gpio * chip,unsigned gpio,bool * pull_up,bool * pull_down)368 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
369 bool *pull_up, bool *pull_down)
370 {
371 unsigned long flags;
372
373 raw_spin_lock_irqsave(&chip->lock, flags);
374 *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
375 *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
376 raw_spin_unlock_irqrestore(&chip->lock, flags);
377 }
378
nsp_gpio_set_strength(struct nsp_gpio * chip,unsigned gpio,u32 strength)379 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
380 u32 strength)
381 {
382 u32 offset, shift, i;
383 u32 val;
384 unsigned long flags;
385
386 /* make sure drive strength is supported */
387 if (strength < 2 || strength > 16 || (strength % 2))
388 return -ENOTSUPP;
389
390 shift = gpio;
391 offset = NSP_GPIO_DRV_CTRL;
392 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
393 strength);
394 raw_spin_lock_irqsave(&chip->lock, flags);
395 strength = (strength / 2) - 1;
396 for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
397 val = readl(chip->io_ctrl + offset);
398 val &= ~BIT(shift);
399 val |= ((strength >> (i-1)) & 0x1) << shift;
400 writel(val, chip->io_ctrl + offset);
401 offset += 4;
402 }
403 raw_spin_unlock_irqrestore(&chip->lock, flags);
404
405 return 0;
406 }
407
nsp_gpio_get_strength(struct nsp_gpio * chip,unsigned gpio,u16 * strength)408 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
409 u16 *strength)
410 {
411 unsigned int offset, shift;
412 u32 val;
413 unsigned long flags;
414 int i;
415
416 offset = NSP_GPIO_DRV_CTRL;
417 shift = gpio;
418
419 raw_spin_lock_irqsave(&chip->lock, flags);
420 *strength = 0;
421 for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
422 val = readl(chip->io_ctrl + offset) & BIT(shift);
423 val >>= shift;
424 *strength += (val << i);
425 offset += 4;
426 }
427
428 /* convert to mA */
429 *strength = (*strength + 1) * 2;
430 raw_spin_unlock_irqrestore(&chip->lock, flags);
431
432 return 0;
433 }
434
nsp_pin_config_group_get(struct pinctrl_dev * pctldev,unsigned selector,unsigned long * config)435 static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
436 unsigned selector,
437 unsigned long *config)
438 {
439 return 0;
440 }
441
nsp_pin_config_group_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned long * configs,unsigned num_configs)442 static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
443 unsigned selector,
444 unsigned long *configs, unsigned num_configs)
445 {
446 return 0;
447 }
448
nsp_pin_config_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)449 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
450 unsigned long *config)
451 {
452 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
453 enum pin_config_param param = pinconf_to_config_param(*config);
454 unsigned int gpio;
455 u16 arg = 0;
456 bool pull_up, pull_down;
457 int ret;
458
459 gpio = nsp_pin_to_gpio(pin);
460 switch (param) {
461 case PIN_CONFIG_BIAS_DISABLE:
462 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
463 if ((pull_up == false) && (pull_down == false))
464 return 0;
465 else
466 return -EINVAL;
467
468 case PIN_CONFIG_BIAS_PULL_UP:
469 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
470 if (pull_up)
471 return 0;
472 else
473 return -EINVAL;
474
475 case PIN_CONFIG_BIAS_PULL_DOWN:
476 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
477 if (pull_down)
478 return 0;
479 else
480 return -EINVAL;
481
482 case PIN_CONFIG_DRIVE_STRENGTH:
483 ret = nsp_gpio_get_strength(chip, gpio, &arg);
484 if (ret)
485 return ret;
486 *config = pinconf_to_config_packed(param, arg);
487 return 0;
488
489 default:
490 return -ENOTSUPP;
491 }
492 }
493
nsp_pin_config_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * configs,unsigned num_configs)494 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
495 unsigned long *configs, unsigned num_configs)
496 {
497 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
498 enum pin_config_param param;
499 u32 arg;
500 unsigned int i, gpio;
501 int ret = -ENOTSUPP;
502
503 gpio = nsp_pin_to_gpio(pin);
504 for (i = 0; i < num_configs; i++) {
505 param = pinconf_to_config_param(configs[i]);
506 arg = pinconf_to_config_argument(configs[i]);
507
508 switch (param) {
509 case PIN_CONFIG_BIAS_DISABLE:
510 ret = nsp_gpio_set_pull(chip, gpio, false, false);
511 if (ret < 0)
512 goto out;
513 break;
514
515 case PIN_CONFIG_BIAS_PULL_UP:
516 ret = nsp_gpio_set_pull(chip, gpio, true, false);
517 if (ret < 0)
518 goto out;
519 break;
520
521 case PIN_CONFIG_BIAS_PULL_DOWN:
522 ret = nsp_gpio_set_pull(chip, gpio, false, true);
523 if (ret < 0)
524 goto out;
525 break;
526
527 case PIN_CONFIG_DRIVE_STRENGTH:
528 ret = nsp_gpio_set_strength(chip, gpio, arg);
529 if (ret < 0)
530 goto out;
531 break;
532
533 case PIN_CONFIG_SLEW_RATE:
534 ret = nsp_gpio_set_slew(chip, gpio, arg);
535 if (ret < 0)
536 goto out;
537 break;
538
539 default:
540 dev_err(chip->dev, "invalid configuration\n");
541 return -ENOTSUPP;
542 }
543 }
544
545 out:
546 return ret;
547 }
548
549 static const struct pinconf_ops nsp_pconf_ops = {
550 .is_generic = true,
551 .pin_config_get = nsp_pin_config_get,
552 .pin_config_set = nsp_pin_config_set,
553 .pin_config_group_get = nsp_pin_config_group_get,
554 .pin_config_group_set = nsp_pin_config_group_set,
555 };
556
557 /*
558 * NSP GPIO controller supports some PINCONF related configurations such as
559 * pull up, pull down, slew and drive strength, when the pin is configured
560 * to GPIO.
561 *
562 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
563 * local GPIO pins
564 */
nsp_gpio_register_pinconf(struct nsp_gpio * chip)565 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
566 {
567 struct pinctrl_desc *pctldesc = &chip->pctldesc;
568 struct pinctrl_pin_desc *pins;
569 struct gpio_chip *gc = &chip->gc;
570 int i;
571
572 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
573 if (!pins)
574 return -ENOMEM;
575 for (i = 0; i < gc->ngpio; i++) {
576 pins[i].number = i;
577 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
578 "gpio-%d", i);
579 if (!pins[i].name)
580 return -ENOMEM;
581 }
582 pctldesc->name = dev_name(chip->dev);
583 pctldesc->pctlops = &nsp_pctrl_ops;
584 pctldesc->pins = pins;
585 pctldesc->npins = gc->ngpio;
586 pctldesc->confops = &nsp_pconf_ops;
587
588 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
589 if (IS_ERR(chip->pctl)) {
590 dev_err(chip->dev, "unable to register pinctrl device\n");
591 return PTR_ERR(chip->pctl);
592 }
593
594 return 0;
595 }
596
597 static const struct of_device_id nsp_gpio_of_match[] = {
598 {.compatible = "brcm,nsp-gpio-a",},
599 {}
600 };
601
nsp_gpio_probe(struct platform_device * pdev)602 static int nsp_gpio_probe(struct platform_device *pdev)
603 {
604 struct device *dev = &pdev->dev;
605 struct nsp_gpio *chip;
606 struct gpio_chip *gc;
607 u32 val;
608 int irq, ret;
609
610 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
611 dev_err(&pdev->dev, "Missing ngpios OF property\n");
612 return -ENODEV;
613 }
614
615 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
616 if (!chip)
617 return -ENOMEM;
618
619 chip->dev = dev;
620 platform_set_drvdata(pdev, chip);
621
622 chip->base = devm_platform_ioremap_resource(pdev, 0);
623 if (IS_ERR(chip->base)) {
624 dev_err(dev, "unable to map I/O memory\n");
625 return PTR_ERR(chip->base);
626 }
627
628 chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
629 if (IS_ERR(chip->io_ctrl)) {
630 dev_err(dev, "unable to map I/O memory\n");
631 return PTR_ERR(chip->io_ctrl);
632 }
633
634 raw_spin_lock_init(&chip->lock);
635 gc = &chip->gc;
636 gc->base = -1;
637 gc->can_sleep = false;
638 gc->ngpio = val;
639 gc->label = dev_name(dev);
640 gc->parent = dev;
641 gc->request = gpiochip_generic_request;
642 gc->free = gpiochip_generic_free;
643 gc->direction_input = nsp_gpio_direction_input;
644 gc->direction_output = nsp_gpio_direction_output;
645 gc->get_direction = nsp_gpio_get_direction;
646 gc->set = nsp_gpio_set;
647 gc->get = nsp_gpio_get;
648
649 /* optional GPIO interrupt support */
650 irq = platform_get_irq(pdev, 0);
651 if (irq > 0) {
652 struct gpio_irq_chip *girq;
653 struct irq_chip *irqc;
654
655 irqc = &chip->irqchip;
656 irqc->name = "gpio-a";
657 irqc->irq_ack = nsp_gpio_irq_ack;
658 irqc->irq_mask = nsp_gpio_irq_mask;
659 irqc->irq_unmask = nsp_gpio_irq_unmask;
660 irqc->irq_set_type = nsp_gpio_irq_set_type;
661
662 val = readl(chip->base + NSP_CHIP_A_INT_MASK);
663 val = val | NSP_CHIP_A_GPIO_INT_BIT;
664 writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
665
666 /* Install ISR for this GPIO controller. */
667 ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
668 IRQF_SHARED, "gpio-a", &chip->gc);
669 if (ret) {
670 dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
671 irq, ret);
672 return ret;
673 }
674
675 girq = &chip->gc.irq;
676 girq->chip = irqc;
677 /* This will let us handle the parent IRQ in the driver */
678 girq->parent_handler = NULL;
679 girq->num_parents = 0;
680 girq->parents = NULL;
681 girq->default_type = IRQ_TYPE_NONE;
682 girq->handler = handle_bad_irq;
683 }
684
685 ret = devm_gpiochip_add_data(dev, gc, chip);
686 if (ret < 0) {
687 dev_err(dev, "unable to add GPIO chip\n");
688 return ret;
689 }
690
691 ret = nsp_gpio_register_pinconf(chip);
692 if (ret) {
693 dev_err(dev, "unable to register pinconf\n");
694 return ret;
695 }
696
697 return 0;
698 }
699
700 static struct platform_driver nsp_gpio_driver = {
701 .driver = {
702 .name = "nsp-gpio-a",
703 .of_match_table = nsp_gpio_of_match,
704 },
705 .probe = nsp_gpio_probe,
706 };
707
nsp_gpio_init(void)708 static int __init nsp_gpio_init(void)
709 {
710 return platform_driver_register(&nsp_gpio_driver);
711 }
712 arch_initcall_sync(nsp_gpio_init);
713