1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright 2021 NXP */
3
4 #include <dt-bindings/firmware/imx/rsrc.h>
5 #include <linux/arm-smccc.h>
6 #include <linux/clk.h>
7 #include <linux/err.h>
8 #include <linux/firmware.h>
9 #include <linux/firmware/imx/sci.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/mailbox_client.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_domain.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/remoteproc.h>
23 #include <linux/slab.h>
24
25 #include "imx_rproc.h"
26 #include "remoteproc_elf_helpers.h"
27 #include "remoteproc_internal.h"
28
29 #define DSP_RPROC_CLK_MAX 5
30
31 #define REMOTE_IS_READY BIT(0)
32 #define REMOTE_READY_WAIT_MAX_RETRIES 500
33
34 /* att flags */
35 /* DSP own area */
36 #define ATT_OWN BIT(31)
37 /* DSP instruction area */
38 #define ATT_IRAM BIT(30)
39
40 /* Definitions for i.MX8MP */
41 /* DAP registers */
42 #define IMX8M_DAP_DEBUG 0x28800000
43 #define IMX8M_DAP_DEBUG_SIZE (64 * 1024)
44 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)
45 #define IMX8M_PWRCTL_CORERESET BIT(16)
46
47 /* DSP audio mix registers */
48 #define IMX8M_AudioDSP_REG0 0x100
49 #define IMX8M_AudioDSP_REG1 0x104
50 #define IMX8M_AudioDSP_REG2 0x108
51 #define IMX8M_AudioDSP_REG3 0x10c
52
53 #define IMX8M_AudioDSP_REG2_RUNSTALL BIT(5)
54 #define IMX8M_AudioDSP_REG2_PWAITMODE BIT(1)
55
56 /* Definitions for i.MX8ULP */
57 #define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8
58 #define IMX8ULP_SYSCTRL0_DSP_DBG_RST BIT(25)
59 #define IMX8ULP_SYSCTRL0_DSP_PLAT_CLK_EN BIT(19)
60 #define IMX8ULP_SYSCTRL0_DSP_PBCLK_EN BIT(18)
61 #define IMX8ULP_SYSCTRL0_DSP_CLK_EN BIT(17)
62 #define IMX8ULP_SYSCTRL0_DSP_RST BIT(16)
63 #define IMX8ULP_SYSCTRL0_DSP_OCD_HALT BIT(14)
64 #define IMX8ULP_SYSCTRL0_DSP_STALL BIT(13)
65
66 #define IMX8ULP_SIP_HIFI_XRDC 0xc200000e
67
68 /*
69 * enum - Predefined Mailbox Messages
70 *
71 * @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor
72 *
73 * @RP_MBOX_SUSPEND_ACK: successful response from remote processor for a
74 * suspend request
75 *
76 * @RP_MBOX_RESUME_SYSTEM: system resume request for the remote processor
77 *
78 * @RP_MBOX_RESUME_ACK: successful response from remote processor for a
79 * resume request
80 */
81 enum imx_dsp_rp_mbox_messages {
82 RP_MBOX_SUSPEND_SYSTEM = 0xFF11,
83 RP_MBOX_SUSPEND_ACK = 0xFF12,
84 RP_MBOX_RESUME_SYSTEM = 0xFF13,
85 RP_MBOX_RESUME_ACK = 0xFF14,
86 };
87
88 /**
89 * struct imx_dsp_rproc - DSP remote processor state
90 * @regmap: regmap handler
91 * @rproc: rproc handler
92 * @dsp_dcfg: device configuration pointer
93 * @clks: clocks needed by this device
94 * @cl: mailbox client to request the mailbox channel
95 * @cl_rxdb: mailbox client to request the mailbox channel for doorbell
96 * @tx_ch: mailbox tx channel handle
97 * @rx_ch: mailbox rx channel handle
98 * @rxdb_ch: mailbox rx doorbell channel handle
99 * @pd_dev: power domain device
100 * @pd_dev_link: power domain device link
101 * @ipc_handle: System Control Unit ipc handle
102 * @rproc_work: work for processing virtio interrupts
103 * @pm_comp: completion primitive to sync for suspend response
104 * @num_domains: power domain number
105 * @flags: control flags
106 */
107 struct imx_dsp_rproc {
108 struct regmap *regmap;
109 struct rproc *rproc;
110 const struct imx_dsp_rproc_dcfg *dsp_dcfg;
111 struct clk_bulk_data clks[DSP_RPROC_CLK_MAX];
112 struct mbox_client cl;
113 struct mbox_client cl_rxdb;
114 struct mbox_chan *tx_ch;
115 struct mbox_chan *rx_ch;
116 struct mbox_chan *rxdb_ch;
117 struct device **pd_dev;
118 struct device_link **pd_dev_link;
119 struct imx_sc_ipc *ipc_handle;
120 struct work_struct rproc_work;
121 struct completion pm_comp;
122 int num_domains;
123 u32 flags;
124 };
125
126 /**
127 * struct imx_dsp_rproc_dcfg - DSP remote processor configuration
128 * @dcfg: imx_rproc_dcfg handler
129 * @reset: reset callback function
130 */
131 struct imx_dsp_rproc_dcfg {
132 const struct imx_rproc_dcfg *dcfg;
133 int (*reset)(struct imx_dsp_rproc *priv);
134 };
135
136 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qm[] = {
137 /* dev addr , sys addr , size , flags */
138 { 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN },
139 { 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN },
140 { 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM},
141 { 0x55700000, 0x55700000, 0x00070000, ATT_OWN },
142 /* DDR (Data) */
143 { 0x80000000, 0x80000000, 0x60000000, 0},
144 };
145
146 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qxp[] = {
147 /* dev addr , sys addr , size , flags */
148 { 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN },
149 { 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN },
150 { 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM},
151 { 0x59700000, 0x59700000, 0x00070000, ATT_OWN },
152 /* DDR (Data) */
153 { 0x80000000, 0x80000000, 0x60000000, 0},
154 };
155
156 static const struct imx_rproc_att imx_dsp_rproc_att_imx8mp[] = {
157 /* dev addr , sys addr , size , flags */
158 { 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN },
159 { 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN },
160 { 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM},
161 { 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN },
162 /* DDR (Data) */
163 { 0x40000000, 0x40000000, 0x80000000, 0},
164 };
165
166 static const struct imx_rproc_att imx_dsp_rproc_att_imx8ulp[] = {
167 /* dev addr , sys addr , size , flags */
168 { 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM},
169 { 0x21180000, 0x21180000, 0x00010000, ATT_OWN },
170 /* DDR (Data) */
171 { 0x0c000000, 0x80000000, 0x10000000, 0},
172 { 0x30000000, 0x90000000, 0x10000000, 0},
173 };
174
175 /* Reset function for DSP on i.MX8MP */
imx8mp_dsp_reset(struct imx_dsp_rproc * priv)176 static int imx8mp_dsp_reset(struct imx_dsp_rproc *priv)
177 {
178 void __iomem *dap = ioremap_wc(IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE);
179 int pwrctl;
180
181 /* Put DSP into reset and stall */
182 pwrctl = readl(dap + IMX8M_DAP_PWRCTL);
183 pwrctl |= IMX8M_PWRCTL_CORERESET;
184 writel(pwrctl, dap + IMX8M_DAP_PWRCTL);
185
186 /* Keep reset asserted for 10 cycles */
187 usleep_range(1, 2);
188
189 regmap_update_bits(priv->regmap, IMX8M_AudioDSP_REG2,
190 IMX8M_AudioDSP_REG2_RUNSTALL,
191 IMX8M_AudioDSP_REG2_RUNSTALL);
192
193 /* Take the DSP out of reset and keep stalled for FW loading */
194 pwrctl = readl(dap + IMX8M_DAP_PWRCTL);
195 pwrctl &= ~IMX8M_PWRCTL_CORERESET;
196 writel(pwrctl, dap + IMX8M_DAP_PWRCTL);
197
198 iounmap(dap);
199 return 0;
200 }
201
202 /* Reset function for DSP on i.MX8ULP */
imx8ulp_dsp_reset(struct imx_dsp_rproc * priv)203 static int imx8ulp_dsp_reset(struct imx_dsp_rproc *priv)
204 {
205 struct arm_smccc_res res;
206
207 /* Put DSP into reset and stall */
208 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
209 IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST);
210 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
211 IMX8ULP_SYSCTRL0_DSP_STALL,
212 IMX8ULP_SYSCTRL0_DSP_STALL);
213
214 /* Configure resources of DSP through TFA */
215 arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res);
216
217 /* Take the DSP out of reset and keep stalled for FW loading */
218 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
219 IMX8ULP_SYSCTRL0_DSP_RST, 0);
220 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
221 IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0);
222
223 return 0;
224 }
225
226 /* Specific configuration for i.MX8MP */
227 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = {
228 .src_reg = IMX8M_AudioDSP_REG2,
229 .src_mask = IMX8M_AudioDSP_REG2_RUNSTALL,
230 .src_start = 0,
231 .src_stop = IMX8M_AudioDSP_REG2_RUNSTALL,
232 .att = imx_dsp_rproc_att_imx8mp,
233 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp),
234 .method = IMX_RPROC_MMIO,
235 };
236
237 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = {
238 .dcfg = &dsp_rproc_cfg_imx8mp,
239 .reset = imx8mp_dsp_reset,
240 };
241
242 /* Specific configuration for i.MX8ULP */
243 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp = {
244 .src_reg = IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
245 .src_mask = IMX8ULP_SYSCTRL0_DSP_STALL,
246 .src_start = 0,
247 .src_stop = IMX8ULP_SYSCTRL0_DSP_STALL,
248 .att = imx_dsp_rproc_att_imx8ulp,
249 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp),
250 .method = IMX_RPROC_MMIO,
251 };
252
253 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8ulp = {
254 .dcfg = &dsp_rproc_cfg_imx8ulp,
255 .reset = imx8ulp_dsp_reset,
256 };
257
258 /* Specific configuration for i.MX8QXP */
259 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qxp = {
260 .att = imx_dsp_rproc_att_imx8qxp,
261 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qxp),
262 .method = IMX_RPROC_SCU_API,
263 };
264
265 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qxp = {
266 .dcfg = &dsp_rproc_cfg_imx8qxp,
267 };
268
269 /* Specific configuration for i.MX8QM */
270 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qm = {
271 .att = imx_dsp_rproc_att_imx8qm,
272 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qm),
273 .method = IMX_RPROC_SCU_API,
274 };
275
276 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qm = {
277 .dcfg = &dsp_rproc_cfg_imx8qm,
278 };
279
imx_dsp_rproc_ready(struct rproc * rproc)280 static int imx_dsp_rproc_ready(struct rproc *rproc)
281 {
282 struct imx_dsp_rproc *priv = rproc->priv;
283 int i;
284
285 if (!priv->rxdb_ch)
286 return 0;
287
288 for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) {
289 if (priv->flags & REMOTE_IS_READY)
290 return 0;
291 usleep_range(100, 200);
292 }
293
294 return -ETIMEDOUT;
295 }
296
297 /*
298 * Start function for rproc_ops
299 *
300 * There is a handshake for start procedure: when DSP starts, it
301 * will send a doorbell message to this driver, then the
302 * REMOTE_IS_READY flags is set, then driver will kick
303 * a message to DSP.
304 */
imx_dsp_rproc_start(struct rproc * rproc)305 static int imx_dsp_rproc_start(struct rproc *rproc)
306 {
307 struct imx_dsp_rproc *priv = rproc->priv;
308 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
309 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
310 struct device *dev = rproc->dev.parent;
311 int ret;
312
313 switch (dcfg->method) {
314 case IMX_RPROC_MMIO:
315 ret = regmap_update_bits(priv->regmap,
316 dcfg->src_reg,
317 dcfg->src_mask,
318 dcfg->src_start);
319 break;
320 case IMX_RPROC_SCU_API:
321 ret = imx_sc_pm_cpu_start(priv->ipc_handle,
322 IMX_SC_R_DSP,
323 true,
324 rproc->bootaddr);
325 break;
326 default:
327 return -EOPNOTSUPP;
328 }
329
330 if (ret)
331 dev_err(dev, "Failed to enable remote core!\n");
332 else
333 ret = imx_dsp_rproc_ready(rproc);
334
335 return ret;
336 }
337
338 /*
339 * Stop function for rproc_ops
340 * It clears the REMOTE_IS_READY flags
341 */
imx_dsp_rproc_stop(struct rproc * rproc)342 static int imx_dsp_rproc_stop(struct rproc *rproc)
343 {
344 struct imx_dsp_rproc *priv = rproc->priv;
345 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
346 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
347 struct device *dev = rproc->dev.parent;
348 int ret = 0;
349
350 if (rproc->state == RPROC_CRASHED) {
351 priv->flags &= ~REMOTE_IS_READY;
352 return 0;
353 }
354
355 switch (dcfg->method) {
356 case IMX_RPROC_MMIO:
357 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask,
358 dcfg->src_stop);
359 break;
360 case IMX_RPROC_SCU_API:
361 ret = imx_sc_pm_cpu_start(priv->ipc_handle,
362 IMX_SC_R_DSP,
363 false,
364 rproc->bootaddr);
365 break;
366 default:
367 return -EOPNOTSUPP;
368 }
369
370 if (ret)
371 dev_err(dev, "Failed to stop remote core\n");
372 else
373 priv->flags &= ~REMOTE_IS_READY;
374
375 return ret;
376 }
377
378 /**
379 * imx_dsp_rproc_sys_to_da() - internal memory translation helper
380 * @priv: private data pointer
381 * @sys: system address (DDR address)
382 * @len: length of the memory buffer
383 * @da: device address to translate
384 *
385 * Convert system address (DDR address) to device address (DSP)
386 * for there may be memory remap for device.
387 */
imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc * priv,u64 sys,size_t len,u64 * da)388 static int imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc *priv, u64 sys,
389 size_t len, u64 *da)
390 {
391 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
392 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
393 int i;
394
395 /* Parse address translation table */
396 for (i = 0; i < dcfg->att_size; i++) {
397 const struct imx_rproc_att *att = &dcfg->att[i];
398
399 if (sys >= att->sa && sys + len <= att->sa + att->size) {
400 unsigned int offset = sys - att->sa;
401
402 *da = att->da + offset;
403 return 0;
404 }
405 }
406
407 return -ENOENT;
408 }
409
410 /* Main virtqueue message work function
411 *
412 * This function is executed upon scheduling of the i.MX DSP remoteproc
413 * driver's workqueue. The workqueue is scheduled by the mailbox rx
414 * handler.
415 *
416 * This work function processes both the Tx and Rx virtqueue indices on
417 * every invocation. The rproc_vq_interrupt function can detect if there
418 * are new unprocessed messages or not (returns IRQ_NONE vs IRQ_HANDLED),
419 * but there is no need to check for these return values. The index 0
420 * triggering will process all pending Rx buffers, and the index 1 triggering
421 * will process all newly available Tx buffers and will wakeup any potentially
422 * blocked senders.
423 *
424 * NOTE:
425 * The current logic is based on an inherent design assumption of supporting
426 * only 2 vrings, but this can be changed if needed.
427 */
imx_dsp_rproc_vq_work(struct work_struct * work)428 static void imx_dsp_rproc_vq_work(struct work_struct *work)
429 {
430 struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc,
431 rproc_work);
432 struct rproc *rproc = priv->rproc;
433
434 mutex_lock(&rproc->lock);
435
436 if (rproc->state != RPROC_RUNNING)
437 goto unlock_mutex;
438
439 rproc_vq_interrupt(priv->rproc, 0);
440 rproc_vq_interrupt(priv->rproc, 1);
441
442 unlock_mutex:
443 mutex_unlock(&rproc->lock);
444 }
445
446 /**
447 * imx_dsp_rproc_rx_tx_callback() - inbound mailbox message handler
448 * @cl: mailbox client pointer used for requesting the mailbox channel
449 * @data: mailbox payload
450 *
451 * This handler is invoked by mailbox driver whenever a mailbox
452 * message is received. Usually, the SUSPEND and RESUME related messages
453 * are handled in this function, other messages are handled by remoteproc core
454 */
imx_dsp_rproc_rx_tx_callback(struct mbox_client * cl,void * data)455 static void imx_dsp_rproc_rx_tx_callback(struct mbox_client *cl, void *data)
456 {
457 struct rproc *rproc = dev_get_drvdata(cl->dev);
458 struct imx_dsp_rproc *priv = rproc->priv;
459 struct device *dev = rproc->dev.parent;
460 u32 message = (u32)(*(u32 *)data);
461
462 dev_dbg(dev, "mbox msg: 0x%x\n", message);
463
464 switch (message) {
465 case RP_MBOX_SUSPEND_ACK:
466 complete(&priv->pm_comp);
467 break;
468 case RP_MBOX_RESUME_ACK:
469 complete(&priv->pm_comp);
470 break;
471 default:
472 schedule_work(&priv->rproc_work);
473 break;
474 }
475 }
476
477 /**
478 * imx_dsp_rproc_rxdb_callback() - inbound mailbox message handler
479 * @cl: mailbox client pointer used for requesting the mailbox channel
480 * @data: mailbox payload
481 *
482 * For doorbell, there is no message specified, just set REMOTE_IS_READY
483 * flag.
484 */
imx_dsp_rproc_rxdb_callback(struct mbox_client * cl,void * data)485 static void imx_dsp_rproc_rxdb_callback(struct mbox_client *cl, void *data)
486 {
487 struct rproc *rproc = dev_get_drvdata(cl->dev);
488 struct imx_dsp_rproc *priv = rproc->priv;
489
490 /* Remote is ready after firmware is loaded and running */
491 priv->flags |= REMOTE_IS_READY;
492 }
493
494 /**
495 * imx_dsp_rproc_mbox_init() - request mailbox channels
496 * @priv: private data pointer
497 *
498 * Request three mailbox channels (tx, rx, rxdb).
499 */
imx_dsp_rproc_mbox_init(struct imx_dsp_rproc * priv)500 static int imx_dsp_rproc_mbox_init(struct imx_dsp_rproc *priv)
501 {
502 struct device *dev = priv->rproc->dev.parent;
503 struct mbox_client *cl;
504 int ret;
505
506 if (!of_get_property(dev->of_node, "mbox-names", NULL))
507 return 0;
508
509 cl = &priv->cl;
510 cl->dev = dev;
511 cl->tx_block = true;
512 cl->tx_tout = 100;
513 cl->knows_txdone = false;
514 cl->rx_callback = imx_dsp_rproc_rx_tx_callback;
515
516 /* Channel for sending message */
517 priv->tx_ch = mbox_request_channel_byname(cl, "tx");
518 if (IS_ERR(priv->tx_ch)) {
519 ret = PTR_ERR(priv->tx_ch);
520 dev_dbg(cl->dev, "failed to request tx mailbox channel: %d\n",
521 ret);
522 goto err_out;
523 }
524
525 /* Channel for receiving message */
526 priv->rx_ch = mbox_request_channel_byname(cl, "rx");
527 if (IS_ERR(priv->rx_ch)) {
528 ret = PTR_ERR(priv->rx_ch);
529 dev_dbg(cl->dev, "failed to request rx mailbox channel: %d\n",
530 ret);
531 goto err_out;
532 }
533
534 cl = &priv->cl_rxdb;
535 cl->dev = dev;
536 cl->rx_callback = imx_dsp_rproc_rxdb_callback;
537
538 /*
539 * RX door bell is used to receive the ready signal from remote
540 * after firmware loaded.
541 */
542 priv->rxdb_ch = mbox_request_channel_byname(cl, "rxdb");
543 if (IS_ERR(priv->rxdb_ch)) {
544 ret = PTR_ERR(priv->rxdb_ch);
545 dev_dbg(cl->dev, "failed to request mbox chan rxdb, ret %d\n",
546 ret);
547 goto err_out;
548 }
549
550 return 0;
551
552 err_out:
553 if (!IS_ERR(priv->tx_ch))
554 mbox_free_channel(priv->tx_ch);
555 if (!IS_ERR(priv->rx_ch))
556 mbox_free_channel(priv->rx_ch);
557 if (!IS_ERR(priv->rxdb_ch))
558 mbox_free_channel(priv->rxdb_ch);
559
560 return ret;
561 }
562
imx_dsp_rproc_free_mbox(struct imx_dsp_rproc * priv)563 static void imx_dsp_rproc_free_mbox(struct imx_dsp_rproc *priv)
564 {
565 mbox_free_channel(priv->tx_ch);
566 mbox_free_channel(priv->rx_ch);
567 mbox_free_channel(priv->rxdb_ch);
568 }
569
570 /**
571 * imx_dsp_rproc_add_carveout() - request mailbox channels
572 * @priv: private data pointer
573 *
574 * This function registers specified memory entry in @rproc carveouts list
575 * The carveouts can help to mapping the memory address for DSP.
576 */
imx_dsp_rproc_add_carveout(struct imx_dsp_rproc * priv)577 static int imx_dsp_rproc_add_carveout(struct imx_dsp_rproc *priv)
578 {
579 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
580 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
581 struct rproc *rproc = priv->rproc;
582 struct device *dev = rproc->dev.parent;
583 struct device_node *np = dev->of_node;
584 struct of_phandle_iterator it;
585 struct rproc_mem_entry *mem;
586 struct reserved_mem *rmem;
587 void __iomem *cpu_addr;
588 int a;
589 u64 da;
590
591 /* Remap required addresses */
592 for (a = 0; a < dcfg->att_size; a++) {
593 const struct imx_rproc_att *att = &dcfg->att[a];
594
595 if (!(att->flags & ATT_OWN))
596 continue;
597
598 if (imx_dsp_rproc_sys_to_da(priv, att->sa, att->size, &da))
599 return -EINVAL;
600
601 cpu_addr = devm_ioremap_wc(dev, att->sa, att->size);
602 if (!cpu_addr) {
603 dev_err(dev, "failed to map memory %p\n", &att->sa);
604 return -ENOMEM;
605 }
606
607 /* Register memory region */
608 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)att->sa,
609 att->size, da, NULL, NULL, "dsp_mem");
610
611 if (mem)
612 rproc_coredump_add_segment(rproc, da, att->size);
613 else
614 return -ENOMEM;
615
616 rproc_add_carveout(rproc, mem);
617 }
618
619 of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);
620 while (of_phandle_iterator_next(&it) == 0) {
621 /*
622 * Ignore the first memory region which will be used vdev buffer.
623 * No need to do extra handlings, rproc_add_virtio_dev will handle it.
624 */
625 if (!strcmp(it.node->name, "vdev0buffer"))
626 continue;
627
628 rmem = of_reserved_mem_lookup(it.node);
629 if (!rmem) {
630 of_node_put(it.node);
631 dev_err(dev, "unable to acquire memory-region\n");
632 return -EINVAL;
633 }
634
635 if (imx_dsp_rproc_sys_to_da(priv, rmem->base, rmem->size, &da)) {
636 of_node_put(it.node);
637 return -EINVAL;
638 }
639
640 cpu_addr = devm_ioremap_wc(dev, rmem->base, rmem->size);
641 if (!cpu_addr) {
642 of_node_put(it.node);
643 dev_err(dev, "failed to map memory %p\n", &rmem->base);
644 return -ENOMEM;
645 }
646
647 /* Register memory region */
648 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)rmem->base,
649 rmem->size, da, NULL, NULL, it.node->name);
650
651 if (mem) {
652 rproc_coredump_add_segment(rproc, da, rmem->size);
653 } else {
654 of_node_put(it.node);
655 return -ENOMEM;
656 }
657
658 rproc_add_carveout(rproc, mem);
659 }
660
661 return 0;
662 }
663
664 /* Prepare function for rproc_ops */
imx_dsp_rproc_prepare(struct rproc * rproc)665 static int imx_dsp_rproc_prepare(struct rproc *rproc)
666 {
667 struct imx_dsp_rproc *priv = rproc->priv;
668 struct device *dev = rproc->dev.parent;
669 struct rproc_mem_entry *carveout;
670 int ret;
671
672 ret = imx_dsp_rproc_add_carveout(priv);
673 if (ret) {
674 dev_err(dev, "failed on imx_dsp_rproc_add_carveout\n");
675 return ret;
676 }
677
678 pm_runtime_get_sync(dev);
679
680 /*
681 * Clear buffers after pm rumtime for internal ocram is not
682 * accessible if power and clock are not enabled.
683 */
684 list_for_each_entry(carveout, &rproc->carveouts, node) {
685 if (carveout->va)
686 memset(carveout->va, 0, carveout->len);
687 }
688
689 return 0;
690 }
691
692 /* Unprepare function for rproc_ops */
imx_dsp_rproc_unprepare(struct rproc * rproc)693 static int imx_dsp_rproc_unprepare(struct rproc *rproc)
694 {
695 pm_runtime_put_sync(rproc->dev.parent);
696
697 return 0;
698 }
699
700 /* Kick function for rproc_ops */
imx_dsp_rproc_kick(struct rproc * rproc,int vqid)701 static void imx_dsp_rproc_kick(struct rproc *rproc, int vqid)
702 {
703 struct imx_dsp_rproc *priv = rproc->priv;
704 struct device *dev = rproc->dev.parent;
705 int err;
706 __u32 mmsg;
707
708 if (!priv->tx_ch) {
709 dev_err(dev, "No initialized mbox tx channel\n");
710 return;
711 }
712
713 /*
714 * Send the index of the triggered virtqueue as the mu payload.
715 * Let remote processor know which virtqueue is used.
716 */
717 mmsg = vqid;
718
719 err = mbox_send_message(priv->tx_ch, (void *)&mmsg);
720 if (err < 0)
721 dev_err(dev, "%s: failed (%d, err:%d)\n", __func__, vqid, err);
722 }
723
724 /*
725 * Custom memory copy implementation for i.MX DSP Cores
726 *
727 * The IRAM is part of the HiFi DSP.
728 * According to hw specs only 32-bits writes are allowed.
729 */
imx_dsp_rproc_memcpy(void * dst,const void * src,size_t size)730 static int imx_dsp_rproc_memcpy(void *dst, const void *src, size_t size)
731 {
732 void __iomem *dest = (void __iomem *)dst;
733 const u8 *src_byte = src;
734 const u32 *source = src;
735 u32 affected_mask;
736 int i, q, r;
737 u32 tmp;
738
739 /* destination must be 32bit aligned */
740 if (!IS_ALIGNED((uintptr_t)dest, 4))
741 return -EINVAL;
742
743 q = size / 4;
744 r = size % 4;
745
746 /* copy data in units of 32 bits at a time */
747 for (i = 0; i < q; i++)
748 writel(source[i], dest + i * 4);
749
750 if (r) {
751 affected_mask = GENMASK(8 * r, 0);
752
753 /*
754 * first read the 32bit data of dest, then change affected
755 * bytes, and write back to dest.
756 * For unaffected bytes, it should not be changed
757 */
758 tmp = readl(dest + q * 4);
759 tmp &= ~affected_mask;
760
761 /* avoid reading after end of source */
762 for (i = 0; i < r; i++)
763 tmp |= (src_byte[q * 4 + i] << (8 * i));
764
765 writel(tmp, dest + q * 4);
766 }
767
768 return 0;
769 }
770
771 /*
772 * Custom memset implementation for i.MX DSP Cores
773 *
774 * The IRAM is part of the HiFi DSP.
775 * According to hw specs only 32-bits writes are allowed.
776 */
imx_dsp_rproc_memset(void * addr,u8 value,size_t size)777 static int imx_dsp_rproc_memset(void *addr, u8 value, size_t size)
778 {
779 void __iomem *tmp_dst = (void __iomem *)addr;
780 u32 tmp_val = value;
781 u32 affected_mask;
782 int q, r;
783 u32 tmp;
784
785 /* destination must be 32bit aligned */
786 if (!IS_ALIGNED((uintptr_t)addr, 4))
787 return -EINVAL;
788
789 tmp_val |= tmp_val << 8;
790 tmp_val |= tmp_val << 16;
791
792 q = size / 4;
793 r = size % 4;
794
795 while (q--)
796 writel(tmp_val, tmp_dst++);
797
798 if (r) {
799 affected_mask = GENMASK(8 * r, 0);
800
801 /*
802 * first read the 32bit data of addr, then change affected
803 * bytes, and write back to addr.
804 * For unaffected bytes, it should not be changed
805 */
806 tmp = readl(tmp_dst);
807 tmp &= ~affected_mask;
808
809 tmp |= (tmp_val & affected_mask);
810 writel(tmp, tmp_dst);
811 }
812
813 return 0;
814 }
815
816 /*
817 * imx_dsp_rproc_elf_load_segments() - load firmware segments to memory
818 * @rproc: remote processor which will be booted using these fw segments
819 * @fw: the ELF firmware image
820 *
821 * This function loads the firmware segments to memory, where the remote
822 * processor expects them.
823 *
824 * Return: 0 on success and an appropriate error code otherwise
825 */
imx_dsp_rproc_elf_load_segments(struct rproc * rproc,const struct firmware * fw)826 static int imx_dsp_rproc_elf_load_segments(struct rproc *rproc, const struct firmware *fw)
827 {
828 struct device *dev = &rproc->dev;
829 const void *ehdr, *phdr;
830 int i, ret = 0;
831 u16 phnum;
832 const u8 *elf_data = fw->data;
833 u8 class = fw_elf_get_class(fw);
834 u32 elf_phdr_get_size = elf_size_of_phdr(class);
835
836 ehdr = elf_data;
837 phnum = elf_hdr_get_e_phnum(class, ehdr);
838 phdr = elf_data + elf_hdr_get_e_phoff(class, ehdr);
839
840 /* go through the available ELF segments */
841 for (i = 0; i < phnum; i++, phdr += elf_phdr_get_size) {
842 u64 da = elf_phdr_get_p_paddr(class, phdr);
843 u64 memsz = elf_phdr_get_p_memsz(class, phdr);
844 u64 filesz = elf_phdr_get_p_filesz(class, phdr);
845 u64 offset = elf_phdr_get_p_offset(class, phdr);
846 u32 type = elf_phdr_get_p_type(class, phdr);
847 void *ptr;
848
849 if (type != PT_LOAD || !memsz)
850 continue;
851
852 dev_dbg(dev, "phdr: type %d da 0x%llx memsz 0x%llx filesz 0x%llx\n",
853 type, da, memsz, filesz);
854
855 if (filesz > memsz) {
856 dev_err(dev, "bad phdr filesz 0x%llx memsz 0x%llx\n",
857 filesz, memsz);
858 ret = -EINVAL;
859 break;
860 }
861
862 if (offset + filesz > fw->size) {
863 dev_err(dev, "truncated fw: need 0x%llx avail 0x%zx\n",
864 offset + filesz, fw->size);
865 ret = -EINVAL;
866 break;
867 }
868
869 if (!rproc_u64_fit_in_size_t(memsz)) {
870 dev_err(dev, "size (%llx) does not fit in size_t type\n",
871 memsz);
872 ret = -EOVERFLOW;
873 break;
874 }
875
876 /* grab the kernel address for this device address */
877 ptr = rproc_da_to_va(rproc, da, memsz, NULL);
878 if (!ptr) {
879 dev_err(dev, "bad phdr da 0x%llx mem 0x%llx\n", da,
880 memsz);
881 ret = -EINVAL;
882 break;
883 }
884
885 /* put the segment where the remote processor expects it */
886 if (filesz) {
887 ret = imx_dsp_rproc_memcpy(ptr, elf_data + offset, filesz);
888 if (ret) {
889 dev_err(dev, "memory copy failed for da 0x%llx memsz 0x%llx\n",
890 da, memsz);
891 break;
892 }
893 }
894
895 /* zero out remaining memory for this segment */
896 if (memsz > filesz) {
897 ret = imx_dsp_rproc_memset(ptr + filesz, 0, memsz - filesz);
898 if (ret) {
899 dev_err(dev, "memset failed for da 0x%llx memsz 0x%llx\n",
900 da, memsz);
901 break;
902 }
903 }
904 }
905
906 return ret;
907 }
908
imx_dsp_rproc_parse_fw(struct rproc * rproc,const struct firmware * fw)909 static int imx_dsp_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
910 {
911 if (rproc_elf_load_rsc_table(rproc, fw))
912 dev_warn(&rproc->dev, "no resource table found for this firmware\n");
913
914 return 0;
915 }
916
917 static const struct rproc_ops imx_dsp_rproc_ops = {
918 .prepare = imx_dsp_rproc_prepare,
919 .unprepare = imx_dsp_rproc_unprepare,
920 .start = imx_dsp_rproc_start,
921 .stop = imx_dsp_rproc_stop,
922 .kick = imx_dsp_rproc_kick,
923 .load = imx_dsp_rproc_elf_load_segments,
924 .parse_fw = imx_dsp_rproc_parse_fw,
925 .sanity_check = rproc_elf_sanity_check,
926 .get_boot_addr = rproc_elf_get_boot_addr,
927 };
928
929 /**
930 * imx_dsp_attach_pm_domains() - attach the power domains
931 * @priv: private data pointer
932 *
933 * On i.MX8QM and i.MX8QXP there is multiple power domains
934 * required, so need to link them.
935 */
imx_dsp_attach_pm_domains(struct imx_dsp_rproc * priv)936 static int imx_dsp_attach_pm_domains(struct imx_dsp_rproc *priv)
937 {
938 struct device *dev = priv->rproc->dev.parent;
939 int ret, i;
940
941 priv->num_domains = of_count_phandle_with_args(dev->of_node,
942 "power-domains",
943 "#power-domain-cells");
944
945 /* If only one domain, then no need to link the device */
946 if (priv->num_domains <= 1)
947 return 0;
948
949 priv->pd_dev = devm_kmalloc_array(dev, priv->num_domains,
950 sizeof(*priv->pd_dev),
951 GFP_KERNEL);
952 if (!priv->pd_dev)
953 return -ENOMEM;
954
955 priv->pd_dev_link = devm_kmalloc_array(dev, priv->num_domains,
956 sizeof(*priv->pd_dev_link),
957 GFP_KERNEL);
958 if (!priv->pd_dev_link)
959 return -ENOMEM;
960
961 for (i = 0; i < priv->num_domains; i++) {
962 priv->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);
963 if (IS_ERR(priv->pd_dev[i])) {
964 ret = PTR_ERR(priv->pd_dev[i]);
965 goto detach_pm;
966 }
967
968 /*
969 * device_link_add will check priv->pd_dev[i], if it is
970 * NULL, then will break.
971 */
972 priv->pd_dev_link[i] = device_link_add(dev,
973 priv->pd_dev[i],
974 DL_FLAG_STATELESS |
975 DL_FLAG_PM_RUNTIME);
976 if (!priv->pd_dev_link[i]) {
977 dev_pm_domain_detach(priv->pd_dev[i], false);
978 ret = -EINVAL;
979 goto detach_pm;
980 }
981 }
982
983 return 0;
984
985 detach_pm:
986 while (--i >= 0) {
987 device_link_del(priv->pd_dev_link[i]);
988 dev_pm_domain_detach(priv->pd_dev[i], false);
989 }
990
991 return ret;
992 }
993
imx_dsp_detach_pm_domains(struct imx_dsp_rproc * priv)994 static int imx_dsp_detach_pm_domains(struct imx_dsp_rproc *priv)
995 {
996 int i;
997
998 if (priv->num_domains <= 1)
999 return 0;
1000
1001 for (i = 0; i < priv->num_domains; i++) {
1002 device_link_del(priv->pd_dev_link[i]);
1003 dev_pm_domain_detach(priv->pd_dev[i], false);
1004 }
1005
1006 return 0;
1007 }
1008
1009 /**
1010 * imx_dsp_rproc_detect_mode() - detect DSP control mode
1011 * @priv: private data pointer
1012 *
1013 * Different platform has different control method for DSP, which depends
1014 * on how the DSP is integrated in platform.
1015 *
1016 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
1017 * Control Unit.
1018 * For i.MX8MP and i.MX8ULP, DSP should be started and stopped by system
1019 * integration module.
1020 */
imx_dsp_rproc_detect_mode(struct imx_dsp_rproc * priv)1021 static int imx_dsp_rproc_detect_mode(struct imx_dsp_rproc *priv)
1022 {
1023 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
1024 struct device *dev = priv->rproc->dev.parent;
1025 struct regmap *regmap;
1026 int ret = 0;
1027
1028 switch (dsp_dcfg->dcfg->method) {
1029 case IMX_RPROC_SCU_API:
1030 ret = imx_scu_get_handle(&priv->ipc_handle);
1031 if (ret)
1032 return ret;
1033 break;
1034 case IMX_RPROC_MMIO:
1035 regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,dsp-ctrl");
1036 if (IS_ERR(regmap)) {
1037 dev_err(dev, "failed to find syscon\n");
1038 return PTR_ERR(regmap);
1039 }
1040
1041 priv->regmap = regmap;
1042 break;
1043 default:
1044 ret = -EOPNOTSUPP;
1045 break;
1046 }
1047
1048 return ret;
1049 }
1050
1051 static const char *imx_dsp_clks_names[DSP_RPROC_CLK_MAX] = {
1052 /* DSP clocks */
1053 "core", "ocram", "debug", "ipg", "mu",
1054 };
1055
imx_dsp_rproc_clk_get(struct imx_dsp_rproc * priv)1056 static int imx_dsp_rproc_clk_get(struct imx_dsp_rproc *priv)
1057 {
1058 struct device *dev = priv->rproc->dev.parent;
1059 struct clk_bulk_data *clks = priv->clks;
1060 int i;
1061
1062 for (i = 0; i < DSP_RPROC_CLK_MAX; i++)
1063 clks[i].id = imx_dsp_clks_names[i];
1064
1065 return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks);
1066 }
1067
imx_dsp_rproc_probe(struct platform_device * pdev)1068 static int imx_dsp_rproc_probe(struct platform_device *pdev)
1069 {
1070 const struct imx_dsp_rproc_dcfg *dsp_dcfg;
1071 struct device *dev = &pdev->dev;
1072 struct imx_dsp_rproc *priv;
1073 struct rproc *rproc;
1074 const char *fw_name;
1075 int ret;
1076
1077 dsp_dcfg = of_device_get_match_data(dev);
1078 if (!dsp_dcfg)
1079 return -ENODEV;
1080
1081 ret = rproc_of_parse_firmware(dev, 0, &fw_name);
1082 if (ret) {
1083 dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
1084 ret);
1085 return ret;
1086 }
1087
1088 rproc = rproc_alloc(dev, "imx-dsp-rproc", &imx_dsp_rproc_ops, fw_name,
1089 sizeof(*priv));
1090 if (!rproc)
1091 return -ENOMEM;
1092
1093 priv = rproc->priv;
1094 priv->rproc = rproc;
1095 priv->dsp_dcfg = dsp_dcfg;
1096
1097 dev_set_drvdata(dev, rproc);
1098
1099 INIT_WORK(&priv->rproc_work, imx_dsp_rproc_vq_work);
1100
1101 ret = imx_dsp_rproc_detect_mode(priv);
1102 if (ret) {
1103 dev_err(dev, "failed on imx_dsp_rproc_detect_mode\n");
1104 goto err_put_rproc;
1105 }
1106
1107 /* There are multiple power domains required by DSP on some platform */
1108 ret = imx_dsp_attach_pm_domains(priv);
1109 if (ret) {
1110 dev_err(dev, "failed on imx_dsp_attach_pm_domains\n");
1111 goto err_put_rproc;
1112 }
1113 /* Get clocks */
1114 ret = imx_dsp_rproc_clk_get(priv);
1115 if (ret) {
1116 dev_err(dev, "failed on imx_dsp_rproc_clk_get\n");
1117 goto err_detach_domains;
1118 }
1119
1120 init_completion(&priv->pm_comp);
1121 rproc->auto_boot = false;
1122 ret = rproc_add(rproc);
1123 if (ret) {
1124 dev_err(dev, "rproc_add failed\n");
1125 goto err_detach_domains;
1126 }
1127
1128 pm_runtime_enable(dev);
1129
1130 return 0;
1131
1132 err_detach_domains:
1133 imx_dsp_detach_pm_domains(priv);
1134 err_put_rproc:
1135 rproc_free(rproc);
1136
1137 return ret;
1138 }
1139
imx_dsp_rproc_remove(struct platform_device * pdev)1140 static int imx_dsp_rproc_remove(struct platform_device *pdev)
1141 {
1142 struct rproc *rproc = platform_get_drvdata(pdev);
1143 struct imx_dsp_rproc *priv = rproc->priv;
1144
1145 pm_runtime_disable(&pdev->dev);
1146 rproc_del(rproc);
1147 imx_dsp_detach_pm_domains(priv);
1148 rproc_free(rproc);
1149
1150 return 0;
1151 }
1152
1153 /* pm runtime functions */
imx_dsp_runtime_resume(struct device * dev)1154 static int imx_dsp_runtime_resume(struct device *dev)
1155 {
1156 struct rproc *rproc = dev_get_drvdata(dev);
1157 struct imx_dsp_rproc *priv = rproc->priv;
1158 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
1159 int ret;
1160
1161 /*
1162 * There is power domain attached with mailbox, if setup mailbox
1163 * in probe(), then the power of mailbox is always enabled,
1164 * the power can't be saved.
1165 * So move setup of mailbox to runtime resume.
1166 */
1167 ret = imx_dsp_rproc_mbox_init(priv);
1168 if (ret) {
1169 dev_err(dev, "failed on imx_dsp_rproc_mbox_init\n");
1170 return ret;
1171 }
1172
1173 ret = clk_bulk_prepare_enable(DSP_RPROC_CLK_MAX, priv->clks);
1174 if (ret) {
1175 dev_err(dev, "failed on clk_bulk_prepare_enable\n");
1176 return ret;
1177 }
1178
1179 /* Reset DSP if needed */
1180 if (dsp_dcfg->reset)
1181 dsp_dcfg->reset(priv);
1182
1183 return 0;
1184 }
1185
imx_dsp_runtime_suspend(struct device * dev)1186 static int imx_dsp_runtime_suspend(struct device *dev)
1187 {
1188 struct rproc *rproc = dev_get_drvdata(dev);
1189 struct imx_dsp_rproc *priv = rproc->priv;
1190
1191 clk_bulk_disable_unprepare(DSP_RPROC_CLK_MAX, priv->clks);
1192
1193 imx_dsp_rproc_free_mbox(priv);
1194
1195 return 0;
1196 }
1197
imx_dsp_load_firmware(const struct firmware * fw,void * context)1198 static void imx_dsp_load_firmware(const struct firmware *fw, void *context)
1199 {
1200 struct rproc *rproc = context;
1201 int ret;
1202
1203 /*
1204 * Same flow as start procedure.
1205 * Load the ELF segments to memory firstly.
1206 */
1207 ret = rproc_load_segments(rproc, fw);
1208 if (ret)
1209 goto out;
1210
1211 /* Start the remote processor */
1212 ret = rproc->ops->start(rproc);
1213 if (ret)
1214 goto out;
1215
1216 rproc->ops->kick(rproc, 0);
1217
1218 out:
1219 release_firmware(fw);
1220 }
1221
imx_dsp_suspend(struct device * dev)1222 static __maybe_unused int imx_dsp_suspend(struct device *dev)
1223 {
1224 struct rproc *rproc = dev_get_drvdata(dev);
1225 struct imx_dsp_rproc *priv = rproc->priv;
1226 __u32 mmsg = RP_MBOX_SUSPEND_SYSTEM;
1227 int ret;
1228
1229 if (rproc->state != RPROC_RUNNING)
1230 goto out;
1231
1232 reinit_completion(&priv->pm_comp);
1233
1234 /* Tell DSP that suspend is happening */
1235 ret = mbox_send_message(priv->tx_ch, (void *)&mmsg);
1236 if (ret < 0) {
1237 dev_err(dev, "PM mbox_send_message failed: %d\n", ret);
1238 return ret;
1239 }
1240
1241 /*
1242 * DSP need to save the context at suspend.
1243 * Here waiting the response for DSP, then power can be disabled.
1244 */
1245 if (!wait_for_completion_timeout(&priv->pm_comp, msecs_to_jiffies(100)))
1246 return -EBUSY;
1247
1248 out:
1249 /*
1250 * The power of DSP is disabled in suspend, so force pm runtime
1251 * to be suspend, then we can reenable the power and clocks at
1252 * resume stage.
1253 */
1254 return pm_runtime_force_suspend(dev);
1255 }
1256
imx_dsp_resume(struct device * dev)1257 static __maybe_unused int imx_dsp_resume(struct device *dev)
1258 {
1259 struct rproc *rproc = dev_get_drvdata(dev);
1260 int ret = 0;
1261
1262 ret = pm_runtime_force_resume(dev);
1263 if (ret)
1264 return ret;
1265
1266 if (rproc->state != RPROC_RUNNING)
1267 return 0;
1268
1269 /*
1270 * The power of DSP is disabled at suspend, the memory of dsp
1271 * is reset, the image segments are lost. So need to reload
1272 * firmware and restart the DSP if it is in running state.
1273 */
1274 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
1275 rproc->firmware, dev, GFP_KERNEL,
1276 rproc, imx_dsp_load_firmware);
1277 if (ret < 0) {
1278 dev_err(dev, "load firmware failed: %d\n", ret);
1279 goto err;
1280 }
1281
1282 return 0;
1283
1284 err:
1285 pm_runtime_force_suspend(dev);
1286
1287 return ret;
1288 }
1289
1290 static const struct dev_pm_ops imx_dsp_rproc_pm_ops = {
1291 SET_SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume)
1292 SET_RUNTIME_PM_OPS(imx_dsp_runtime_suspend,
1293 imx_dsp_runtime_resume, NULL)
1294 };
1295
1296 static const struct of_device_id imx_dsp_rproc_of_match[] = {
1297 { .compatible = "fsl,imx8qxp-hifi4", .data = &imx_dsp_rproc_cfg_imx8qxp },
1298 { .compatible = "fsl,imx8qm-hifi4", .data = &imx_dsp_rproc_cfg_imx8qm },
1299 { .compatible = "fsl,imx8mp-hifi4", .data = &imx_dsp_rproc_cfg_imx8mp },
1300 { .compatible = "fsl,imx8ulp-hifi4", .data = &imx_dsp_rproc_cfg_imx8ulp },
1301 {},
1302 };
1303 MODULE_DEVICE_TABLE(of, imx_dsp_rproc_of_match);
1304
1305 static struct platform_driver imx_dsp_rproc_driver = {
1306 .probe = imx_dsp_rproc_probe,
1307 .remove = imx_dsp_rproc_remove,
1308 .driver = {
1309 .name = "imx-dsp-rproc",
1310 .of_match_table = imx_dsp_rproc_of_match,
1311 .pm = &imx_dsp_rproc_pm_ops,
1312 },
1313 };
1314 module_platform_driver(imx_dsp_rproc_driver);
1315
1316 MODULE_LICENSE("GPL v2");
1317 MODULE_DESCRIPTION("i.MX HiFi Core Remote Processor Control Driver");
1318 MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
1319