1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017 Impinj, Inc
4 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
5 *
6 * Based on the code of analogus driver:
7 *
8 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19 #include <linux/sizes.h>
20 #include <dt-bindings/power/imx7-power.h>
21 #include <dt-bindings/power/imx8mq-power.h>
22 #include <dt-bindings/power/imx8mm-power.h>
23 #include <dt-bindings/power/imx8mn-power.h>
24 #include <dt-bindings/power/imx8mp-power.h>
25
26 #define GPC_LPCR_A_CORE_BSC 0x000
27
28 #define GPC_PGC_CPU_MAPPING 0x0ec
29 #define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
30
31 #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
32 #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
33 #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4)
34 #define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3)
35 #define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2)
36
37 #define IMX8M_PCIE2_A53_DOMAIN BIT(15)
38 #define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14)
39 #define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13)
40 #define IMX8M_DISP_A53_DOMAIN BIT(12)
41 #define IMX8M_HDMI_A53_DOMAIN BIT(11)
42 #define IMX8M_VPU_A53_DOMAIN BIT(10)
43 #define IMX8M_GPU_A53_DOMAIN BIT(9)
44 #define IMX8M_DDR2_A53_DOMAIN BIT(8)
45 #define IMX8M_DDR1_A53_DOMAIN BIT(7)
46 #define IMX8M_OTG2_A53_DOMAIN BIT(5)
47 #define IMX8M_OTG1_A53_DOMAIN BIT(4)
48 #define IMX8M_PCIE1_A53_DOMAIN BIT(3)
49 #define IMX8M_MIPI_A53_DOMAIN BIT(2)
50
51 #define IMX8MM_VPUH1_A53_DOMAIN BIT(15)
52 #define IMX8MM_VPUG2_A53_DOMAIN BIT(14)
53 #define IMX8MM_VPUG1_A53_DOMAIN BIT(13)
54 #define IMX8MM_DISPMIX_A53_DOMAIN BIT(12)
55 #define IMX8MM_VPUMIX_A53_DOMAIN BIT(10)
56 #define IMX8MM_GPUMIX_A53_DOMAIN BIT(9)
57 #define IMX8MM_GPU_A53_DOMAIN (BIT(8) | BIT(11))
58 #define IMX8MM_DDR1_A53_DOMAIN BIT(7)
59 #define IMX8MM_OTG2_A53_DOMAIN BIT(5)
60 #define IMX8MM_OTG1_A53_DOMAIN BIT(4)
61 #define IMX8MM_PCIE_A53_DOMAIN BIT(3)
62 #define IMX8MM_MIPI_A53_DOMAIN BIT(2)
63
64 #define IMX8MN_DISPMIX_A53_DOMAIN BIT(12)
65 #define IMX8MN_GPUMIX_A53_DOMAIN BIT(9)
66 #define IMX8MN_DDR1_A53_DOMAIN BIT(7)
67 #define IMX8MN_OTG1_A53_DOMAIN BIT(4)
68 #define IMX8MN_MIPI_A53_DOMAIN BIT(2)
69
70 #define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20)
71 #define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
72 #define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18)
73 #define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17)
74 #define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16)
75 #define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15)
76 #define IMX8MP_VPU_G2_A53_DOMAIN BIT(14)
77 #define IMX8MP_VPU_G1_A53_DOMAIN BIT(13)
78 #define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
79 #define IMX8MP_GPU3D_A53_DOMAIN BIT(11)
80 #define IMX8MP_VPUMIX_A53_DOMAIN BIT(10)
81 #define IMX8MP_GPUMIX_A53_DOMAIN BIT(9)
82 #define IMX8MP_GPU2D_A53_DOMAIN BIT(8)
83 #define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7)
84 #define IMX8MP_MLMIX_A53_DOMAIN BIT(6)
85 #define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
86 #define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
87 #define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
88 #define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2)
89
90 #define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
91 #define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
92
93 #define GPC_PU_PGC_SW_PUP_REQ 0x0f8
94 #define GPC_PU_PGC_SW_PDN_REQ 0x104
95
96 #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
97 #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
98 #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
99 #define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
100 #define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
101
102 #define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
103 #define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12)
104 #define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11)
105 #define IMX8M_DISP_SW_Pxx_REQ BIT(10)
106 #define IMX8M_HDMI_SW_Pxx_REQ BIT(9)
107 #define IMX8M_VPU_SW_Pxx_REQ BIT(8)
108 #define IMX8M_GPU_SW_Pxx_REQ BIT(7)
109 #define IMX8M_DDR2_SW_Pxx_REQ BIT(6)
110 #define IMX8M_DDR1_SW_Pxx_REQ BIT(5)
111 #define IMX8M_OTG2_SW_Pxx_REQ BIT(3)
112 #define IMX8M_OTG1_SW_Pxx_REQ BIT(2)
113 #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
114 #define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
115
116 #define IMX8MM_VPUH1_SW_Pxx_REQ BIT(13)
117 #define IMX8MM_VPUG2_SW_Pxx_REQ BIT(12)
118 #define IMX8MM_VPUG1_SW_Pxx_REQ BIT(11)
119 #define IMX8MM_DISPMIX_SW_Pxx_REQ BIT(10)
120 #define IMX8MM_VPUMIX_SW_Pxx_REQ BIT(8)
121 #define IMX8MM_GPUMIX_SW_Pxx_REQ BIT(7)
122 #define IMX8MM_GPU_SW_Pxx_REQ (BIT(6) | BIT(9))
123 #define IMX8MM_DDR1_SW_Pxx_REQ BIT(5)
124 #define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
125 #define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
126 #define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
127 #define IMX8MM_MIPI_SW_Pxx_REQ BIT(0)
128
129 #define IMX8MN_DISPMIX_SW_Pxx_REQ BIT(10)
130 #define IMX8MN_GPUMIX_SW_Pxx_REQ BIT(7)
131 #define IMX8MN_DDR1_SW_Pxx_REQ BIT(5)
132 #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
133 #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
134
135 #define IMX8MP_DDRMIX_Pxx_REQ BIT(19)
136 #define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18)
137 #define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
138 #define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16)
139 #define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15)
140 #define IMX8MP_HDMIMIX_Pxx_REQ BIT(14)
141 #define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13)
142 #define IMX8MP_VPU_G2_Pxx_REQ BIT(12)
143 #define IMX8MP_VPU_G1_Pxx_REQ BIT(11)
144 #define IMX8MP_MEDIMIX_Pxx_REQ BIT(10)
145 #define IMX8MP_GPU_3D_Pxx_REQ BIT(9)
146 #define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8)
147 #define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7)
148 #define IMX8MP_GPU_2D_Pxx_REQ BIT(6)
149 #define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5)
150 #define IMX8MP_MLMIX_Pxx_REQ BIT(4)
151 #define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
152 #define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
153 #define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
154 #define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0)
155
156 #define GPC_M4_PU_PDN_FLG 0x1bc
157
158 #define IMX8MP_GPC_PU_PWRHSK 0x190
159 #define GPC_PU_PWRHSK 0x1fc
160
161 #define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
162 #define IMX8M_VPU_HSK_PWRDNACKN BIT(25)
163 #define IMX8M_DISP_HSK_PWRDNACKN BIT(24)
164 #define IMX8M_GPU_HSK_PWRDNREQN BIT(6)
165 #define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
166 #define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
167
168 #define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
169 #define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
170 #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
171 #define IMX8MM_DISPMIX_HSK_PWRDNACKN BIT(25)
172 #define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
173 #define IMX8MM_GPUMIX_HSK_PWRDNREQN BIT(11)
174 #define IMX8MM_GPU_HSK_PWRDNREQN (BIT(9) | BIT(10))
175 #define IMX8MM_VPUMIX_HSK_PWRDNREQN BIT(8)
176 #define IMX8MM_DISPMIX_HSK_PWRDNREQN BIT(7)
177 #define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
178
179 #define IMX8MN_GPUMIX_HSK_PWRDNACKN (BIT(29) | BIT(27))
180 #define IMX8MN_DISPMIX_HSK_PWRDNACKN BIT(25)
181 #define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23)
182 #define IMX8MN_GPUMIX_HSK_PWRDNREQN (BIT(11) | BIT(9))
183 #define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
184 #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
185
186 #define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
187 #define IMX8MP_HDMIMIX_PWRDNACKN BIT(29)
188 #define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
189 #define IMX8MP_VPUMIX_PWRDNACKN BIT(26)
190 #define IMX8MP_GPUMIX_PWRDNACKN BIT(25)
191 #define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24))
192 #define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31))
193 #define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
194 #define IMX8MP_HDMIMIX_PWRDNREQN BIT(13)
195 #define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
196 #define IMX8MP_VPUMIX_PWRDNREQN BIT(10)
197 #define IMX8MP_GPUMIX_PWRDNREQN BIT(9)
198 #define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8))
199 #define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15))
200
201 /*
202 * The PGC offset values in Reference Manual
203 * (Rev. 1, 01/2018 and the older ones) GPC chapter's
204 * GPC_PGC memory map are incorrect, below offset
205 * values are from design RTL.
206 */
207 #define IMX7_PGC_MIPI 16
208 #define IMX7_PGC_PCIE 17
209 #define IMX7_PGC_USB_HSIC 20
210
211 #define IMX8M_PGC_MIPI 16
212 #define IMX8M_PGC_PCIE1 17
213 #define IMX8M_PGC_OTG1 18
214 #define IMX8M_PGC_OTG2 19
215 #define IMX8M_PGC_DDR1 21
216 #define IMX8M_PGC_GPU 23
217 #define IMX8M_PGC_VPU 24
218 #define IMX8M_PGC_DISP 26
219 #define IMX8M_PGC_MIPI_CSI1 27
220 #define IMX8M_PGC_MIPI_CSI2 28
221 #define IMX8M_PGC_PCIE2 29
222
223 #define IMX8MM_PGC_MIPI 16
224 #define IMX8MM_PGC_PCIE 17
225 #define IMX8MM_PGC_OTG1 18
226 #define IMX8MM_PGC_OTG2 19
227 #define IMX8MM_PGC_DDR1 21
228 #define IMX8MM_PGC_GPU2D 22
229 #define IMX8MM_PGC_GPUMIX 23
230 #define IMX8MM_PGC_VPUMIX 24
231 #define IMX8MM_PGC_GPU3D 25
232 #define IMX8MM_PGC_DISPMIX 26
233 #define IMX8MM_PGC_VPUG1 27
234 #define IMX8MM_PGC_VPUG2 28
235 #define IMX8MM_PGC_VPUH1 29
236
237 #define IMX8MN_PGC_MIPI 16
238 #define IMX8MN_PGC_OTG1 18
239 #define IMX8MN_PGC_DDR1 21
240 #define IMX8MN_PGC_GPUMIX 23
241 #define IMX8MN_PGC_DISPMIX 26
242
243 #define IMX8MP_PGC_NOC 9
244 #define IMX8MP_PGC_MIPI1 12
245 #define IMX8MP_PGC_PCIE 13
246 #define IMX8MP_PGC_USB1 14
247 #define IMX8MP_PGC_USB2 15
248 #define IMX8MP_PGC_MLMIX 16
249 #define IMX8MP_PGC_AUDIOMIX 17
250 #define IMX8MP_PGC_GPU2D 18
251 #define IMX8MP_PGC_GPUMIX 19
252 #define IMX8MP_PGC_VPUMIX 20
253 #define IMX8MP_PGC_GPU3D 21
254 #define IMX8MP_PGC_MEDIAMIX 22
255 #define IMX8MP_PGC_VPU_G1 23
256 #define IMX8MP_PGC_VPU_G2 24
257 #define IMX8MP_PGC_VPU_VC8000E 25
258 #define IMX8MP_PGC_HDMIMIX 26
259 #define IMX8MP_PGC_HDMI 27
260 #define IMX8MP_PGC_MIPI2 28
261 #define IMX8MP_PGC_HSIOMIX 29
262 #define IMX8MP_PGC_MEDIA_ISP_DWP 30
263 #define IMX8MP_PGC_DDRMIX 31
264
265 #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
266 #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
267
268 #define GPC_PGC_CTRL_PCR BIT(0)
269
270 struct imx_pgc_regs {
271 u16 map;
272 u16 pup;
273 u16 pdn;
274 u16 hsk;
275 };
276
277 struct imx_pgc_domain {
278 struct generic_pm_domain genpd;
279 struct regmap *regmap;
280 const struct imx_pgc_regs *regs;
281 struct regulator *regulator;
282 struct reset_control *reset;
283 struct clk_bulk_data *clks;
284 int num_clks;
285
286 unsigned long pgc;
287
288 const struct {
289 u32 pxx;
290 u32 map;
291 u32 hskreq;
292 u32 hskack;
293 } bits;
294
295 const int voltage;
296 const bool keep_clocks;
297 struct device *dev;
298
299 unsigned int pgc_sw_pup_reg;
300 unsigned int pgc_sw_pdn_reg;
301 };
302
303 struct imx_pgc_domain_data {
304 const struct imx_pgc_domain *domains;
305 size_t domains_num;
306 const struct regmap_access_table *reg_access_table;
307 const struct imx_pgc_regs *pgc_regs;
308 };
309
310 static inline struct imx_pgc_domain *
to_imx_pgc_domain(struct generic_pm_domain * genpd)311 to_imx_pgc_domain(struct generic_pm_domain *genpd)
312 {
313 return container_of(genpd, struct imx_pgc_domain, genpd);
314 }
315
imx_pgc_power_up(struct generic_pm_domain * genpd)316 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
317 {
318 struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
319 u32 reg_val, pgc;
320 int ret;
321
322 ret = pm_runtime_get_sync(domain->dev);
323 if (ret < 0) {
324 pm_runtime_put_noidle(domain->dev);
325 return ret;
326 }
327
328 if (!IS_ERR(domain->regulator)) {
329 ret = regulator_enable(domain->regulator);
330 if (ret) {
331 dev_err(domain->dev,
332 "failed to enable regulator: %pe\n",
333 ERR_PTR(ret));
334 goto out_put_pm;
335 }
336 }
337
338 reset_control_assert(domain->reset);
339
340 /* Enable reset clocks for all devices in the domain */
341 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
342 if (ret) {
343 dev_err(domain->dev, "failed to enable reset clocks\n");
344 goto out_regulator_disable;
345 }
346
347 /* delays for reset to propagate */
348 udelay(5);
349
350 if (domain->bits.pxx) {
351 /* request the domain to power up */
352 regmap_update_bits(domain->regmap, domain->regs->pup,
353 domain->bits.pxx, domain->bits.pxx);
354 /*
355 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
356 * for PUP_REQ/PDN_REQ bit to be cleared
357 */
358 ret = regmap_read_poll_timeout(domain->regmap,
359 domain->regs->pup, reg_val,
360 !(reg_val & domain->bits.pxx),
361 0, USEC_PER_MSEC);
362 if (ret) {
363 dev_err(domain->dev, "failed to command PGC\n");
364 goto out_clk_disable;
365 }
366
367 /* disable power control */
368 for_each_set_bit(pgc, &domain->pgc, 32) {
369 regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
370 GPC_PGC_CTRL_PCR);
371 }
372 }
373
374 /* delay for reset to propagate */
375 udelay(5);
376
377 reset_control_deassert(domain->reset);
378
379 /* request the ADB400 to power up */
380 if (domain->bits.hskreq) {
381 regmap_update_bits(domain->regmap, domain->regs->hsk,
382 domain->bits.hskreq, domain->bits.hskreq);
383
384 /*
385 * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
386 * (reg_val & domain->bits.hskack), 0,
387 * USEC_PER_MSEC);
388 * Technically we need the commented code to wait handshake. But that needs
389 * the BLK-CTL module BUS clk-en bit being set.
390 *
391 * There is a separate BLK-CTL module and we will have such a driver for it,
392 * that driver will set the BUS clk-en bit and handshake will be triggered
393 * automatically there. Just add a delay and suppose the handshake finish
394 * after that.
395 */
396 }
397
398 /* Disable reset clocks for all devices in the domain */
399 if (!domain->keep_clocks)
400 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
401
402 return 0;
403
404 out_clk_disable:
405 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
406 out_regulator_disable:
407 if (!IS_ERR(domain->regulator))
408 regulator_disable(domain->regulator);
409 out_put_pm:
410 pm_runtime_put(domain->dev);
411
412 return ret;
413 }
414
imx_pgc_power_down(struct generic_pm_domain * genpd)415 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
416 {
417 struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
418 u32 reg_val, pgc;
419 int ret;
420
421 /* Enable reset clocks for all devices in the domain */
422 if (!domain->keep_clocks) {
423 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
424 if (ret) {
425 dev_err(domain->dev, "failed to enable reset clocks\n");
426 return ret;
427 }
428 }
429
430 /* request the ADB400 to power down */
431 if (domain->bits.hskreq) {
432 regmap_clear_bits(domain->regmap, domain->regs->hsk,
433 domain->bits.hskreq);
434
435 ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
436 reg_val,
437 !(reg_val & domain->bits.hskack),
438 0, USEC_PER_MSEC);
439 if (ret) {
440 dev_err(domain->dev, "failed to power down ADB400\n");
441 goto out_clk_disable;
442 }
443 }
444
445 if (domain->bits.pxx) {
446 /* enable power control */
447 for_each_set_bit(pgc, &domain->pgc, 32) {
448 regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
449 GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
450 }
451
452 /* request the domain to power down */
453 regmap_update_bits(domain->regmap, domain->regs->pdn,
454 domain->bits.pxx, domain->bits.pxx);
455 /*
456 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
457 * for PUP_REQ/PDN_REQ bit to be cleared
458 */
459 ret = regmap_read_poll_timeout(domain->regmap,
460 domain->regs->pdn, reg_val,
461 !(reg_val & domain->bits.pxx),
462 0, USEC_PER_MSEC);
463 if (ret) {
464 dev_err(domain->dev, "failed to command PGC\n");
465 goto out_clk_disable;
466 }
467 }
468
469 /* Disable reset clocks for all devices in the domain */
470 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
471
472 if (!IS_ERR(domain->regulator)) {
473 ret = regulator_disable(domain->regulator);
474 if (ret) {
475 dev_err(domain->dev,
476 "failed to disable regulator: %pe\n",
477 ERR_PTR(ret));
478 return ret;
479 }
480 }
481
482 pm_runtime_put_sync_suspend(domain->dev);
483
484 return 0;
485
486 out_clk_disable:
487 if (!domain->keep_clocks)
488 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
489
490 return ret;
491 }
492
493 static const struct imx_pgc_domain imx7_pgc_domains[] = {
494 [IMX7_POWER_DOMAIN_MIPI_PHY] = {
495 .genpd = {
496 .name = "mipi-phy",
497 },
498 .bits = {
499 .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
500 .map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
501 },
502 .voltage = 1000000,
503 .pgc = BIT(IMX7_PGC_MIPI),
504 },
505
506 [IMX7_POWER_DOMAIN_PCIE_PHY] = {
507 .genpd = {
508 .name = "pcie-phy",
509 },
510 .bits = {
511 .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
512 .map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
513 },
514 .voltage = 1000000,
515 .pgc = BIT(IMX7_PGC_PCIE),
516 },
517
518 [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
519 .genpd = {
520 .name = "usb-hsic-phy",
521 },
522 .bits = {
523 .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
524 .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
525 },
526 .voltage = 1200000,
527 .pgc = BIT(IMX7_PGC_USB_HSIC),
528 },
529 };
530
531 static const struct regmap_range imx7_yes_ranges[] = {
532 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
533 GPC_M4_PU_PDN_FLG),
534 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
535 GPC_PGC_SR(IMX7_PGC_MIPI)),
536 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
537 GPC_PGC_SR(IMX7_PGC_PCIE)),
538 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
539 GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
540 };
541
542 static const struct regmap_access_table imx7_access_table = {
543 .yes_ranges = imx7_yes_ranges,
544 .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
545 };
546
547 static const struct imx_pgc_regs imx7_pgc_regs = {
548 .map = GPC_PGC_CPU_MAPPING,
549 .pup = GPC_PU_PGC_SW_PUP_REQ,
550 .pdn = GPC_PU_PGC_SW_PDN_REQ,
551 .hsk = GPC_PU_PWRHSK,
552 };
553
554 static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
555 .domains = imx7_pgc_domains,
556 .domains_num = ARRAY_SIZE(imx7_pgc_domains),
557 .reg_access_table = &imx7_access_table,
558 .pgc_regs = &imx7_pgc_regs,
559 };
560
561 static const struct imx_pgc_domain imx8m_pgc_domains[] = {
562 [IMX8M_POWER_DOMAIN_MIPI] = {
563 .genpd = {
564 .name = "mipi",
565 },
566 .bits = {
567 .pxx = IMX8M_MIPI_SW_Pxx_REQ,
568 .map = IMX8M_MIPI_A53_DOMAIN,
569 },
570 .pgc = BIT(IMX8M_PGC_MIPI),
571 },
572
573 [IMX8M_POWER_DOMAIN_PCIE1] = {
574 .genpd = {
575 .name = "pcie1",
576 },
577 .bits = {
578 .pxx = IMX8M_PCIE1_SW_Pxx_REQ,
579 .map = IMX8M_PCIE1_A53_DOMAIN,
580 },
581 .pgc = BIT(IMX8M_PGC_PCIE1),
582 },
583
584 [IMX8M_POWER_DOMAIN_USB_OTG1] = {
585 .genpd = {
586 .name = "usb-otg1",
587 },
588 .bits = {
589 .pxx = IMX8M_OTG1_SW_Pxx_REQ,
590 .map = IMX8M_OTG1_A53_DOMAIN,
591 },
592 .pgc = BIT(IMX8M_PGC_OTG1),
593 },
594
595 [IMX8M_POWER_DOMAIN_USB_OTG2] = {
596 .genpd = {
597 .name = "usb-otg2",
598 },
599 .bits = {
600 .pxx = IMX8M_OTG2_SW_Pxx_REQ,
601 .map = IMX8M_OTG2_A53_DOMAIN,
602 },
603 .pgc = BIT(IMX8M_PGC_OTG2),
604 },
605
606 [IMX8M_POWER_DOMAIN_DDR1] = {
607 .genpd = {
608 .name = "ddr1",
609 },
610 .bits = {
611 .pxx = IMX8M_DDR1_SW_Pxx_REQ,
612 .map = IMX8M_DDR2_A53_DOMAIN,
613 },
614 .pgc = BIT(IMX8M_PGC_DDR1),
615 },
616
617 [IMX8M_POWER_DOMAIN_GPU] = {
618 .genpd = {
619 .name = "gpu",
620 },
621 .bits = {
622 .pxx = IMX8M_GPU_SW_Pxx_REQ,
623 .map = IMX8M_GPU_A53_DOMAIN,
624 .hskreq = IMX8M_GPU_HSK_PWRDNREQN,
625 .hskack = IMX8M_GPU_HSK_PWRDNACKN,
626 },
627 .pgc = BIT(IMX8M_PGC_GPU),
628 },
629
630 [IMX8M_POWER_DOMAIN_VPU] = {
631 .genpd = {
632 .name = "vpu",
633 },
634 .bits = {
635 .pxx = IMX8M_VPU_SW_Pxx_REQ,
636 .map = IMX8M_VPU_A53_DOMAIN,
637 .hskreq = IMX8M_VPU_HSK_PWRDNREQN,
638 .hskack = IMX8M_VPU_HSK_PWRDNACKN,
639 },
640 .pgc = BIT(IMX8M_PGC_VPU),
641 .keep_clocks = true,
642 },
643
644 [IMX8M_POWER_DOMAIN_DISP] = {
645 .genpd = {
646 .name = "disp",
647 },
648 .bits = {
649 .pxx = IMX8M_DISP_SW_Pxx_REQ,
650 .map = IMX8M_DISP_A53_DOMAIN,
651 .hskreq = IMX8M_DISP_HSK_PWRDNREQN,
652 .hskack = IMX8M_DISP_HSK_PWRDNACKN,
653 },
654 .pgc = BIT(IMX8M_PGC_DISP),
655 },
656
657 [IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
658 .genpd = {
659 .name = "mipi-csi1",
660 },
661 .bits = {
662 .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
663 .map = IMX8M_MIPI_CSI1_A53_DOMAIN,
664 },
665 .pgc = BIT(IMX8M_PGC_MIPI_CSI1),
666 },
667
668 [IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
669 .genpd = {
670 .name = "mipi-csi2",
671 },
672 .bits = {
673 .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
674 .map = IMX8M_MIPI_CSI2_A53_DOMAIN,
675 },
676 .pgc = BIT(IMX8M_PGC_MIPI_CSI2),
677 },
678
679 [IMX8M_POWER_DOMAIN_PCIE2] = {
680 .genpd = {
681 .name = "pcie2",
682 },
683 .bits = {
684 .pxx = IMX8M_PCIE2_SW_Pxx_REQ,
685 .map = IMX8M_PCIE2_A53_DOMAIN,
686 },
687 .pgc = BIT(IMX8M_PGC_PCIE2),
688 },
689 };
690
691 static const struct regmap_range imx8m_yes_ranges[] = {
692 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
693 GPC_PU_PWRHSK),
694 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
695 GPC_PGC_SR(IMX8M_PGC_MIPI)),
696 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
697 GPC_PGC_SR(IMX8M_PGC_PCIE1)),
698 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
699 GPC_PGC_SR(IMX8M_PGC_OTG1)),
700 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
701 GPC_PGC_SR(IMX8M_PGC_OTG2)),
702 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
703 GPC_PGC_SR(IMX8M_PGC_DDR1)),
704 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
705 GPC_PGC_SR(IMX8M_PGC_GPU)),
706 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
707 GPC_PGC_SR(IMX8M_PGC_VPU)),
708 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
709 GPC_PGC_SR(IMX8M_PGC_DISP)),
710 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
711 GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
712 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
713 GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
714 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
715 GPC_PGC_SR(IMX8M_PGC_PCIE2)),
716 };
717
718 static const struct regmap_access_table imx8m_access_table = {
719 .yes_ranges = imx8m_yes_ranges,
720 .n_yes_ranges = ARRAY_SIZE(imx8m_yes_ranges),
721 };
722
723 static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
724 .domains = imx8m_pgc_domains,
725 .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
726 .reg_access_table = &imx8m_access_table,
727 .pgc_regs = &imx7_pgc_regs,
728 };
729
730 static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
731 [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
732 .genpd = {
733 .name = "hsiomix",
734 },
735 .bits = {
736 .pxx = 0, /* no power sequence control */
737 .map = 0, /* no power sequence control */
738 .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
739 .hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
740 },
741 .keep_clocks = true,
742 },
743
744 [IMX8MM_POWER_DOMAIN_PCIE] = {
745 .genpd = {
746 .name = "pcie",
747 },
748 .bits = {
749 .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
750 .map = IMX8MM_PCIE_A53_DOMAIN,
751 },
752 .pgc = BIT(IMX8MM_PGC_PCIE),
753 },
754
755 [IMX8MM_POWER_DOMAIN_OTG1] = {
756 .genpd = {
757 .name = "usb-otg1",
758 },
759 .bits = {
760 .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
761 .map = IMX8MM_OTG1_A53_DOMAIN,
762 },
763 .pgc = BIT(IMX8MM_PGC_OTG1),
764 },
765
766 [IMX8MM_POWER_DOMAIN_OTG2] = {
767 .genpd = {
768 .name = "usb-otg2",
769 },
770 .bits = {
771 .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
772 .map = IMX8MM_OTG2_A53_DOMAIN,
773 },
774 .pgc = BIT(IMX8MM_PGC_OTG2),
775 },
776
777 [IMX8MM_POWER_DOMAIN_GPUMIX] = {
778 .genpd = {
779 .name = "gpumix",
780 },
781 .bits = {
782 .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
783 .map = IMX8MM_GPUMIX_A53_DOMAIN,
784 .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
785 .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
786 },
787 .pgc = BIT(IMX8MM_PGC_GPUMIX),
788 .keep_clocks = true,
789 },
790
791 [IMX8MM_POWER_DOMAIN_GPU] = {
792 .genpd = {
793 .name = "gpu",
794 },
795 .bits = {
796 .pxx = IMX8MM_GPU_SW_Pxx_REQ,
797 .map = IMX8MM_GPU_A53_DOMAIN,
798 .hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
799 .hskack = IMX8MM_GPU_HSK_PWRDNACKN,
800 },
801 .pgc = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
802 },
803
804 [IMX8MM_POWER_DOMAIN_VPUMIX] = {
805 .genpd = {
806 .name = "vpumix",
807 },
808 .bits = {
809 .pxx = IMX8MM_VPUMIX_SW_Pxx_REQ,
810 .map = IMX8MM_VPUMIX_A53_DOMAIN,
811 .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
812 .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
813 },
814 .pgc = BIT(IMX8MM_PGC_VPUMIX),
815 .keep_clocks = true,
816 },
817
818 [IMX8MM_POWER_DOMAIN_VPUG1] = {
819 .genpd = {
820 .name = "vpu-g1",
821 },
822 .bits = {
823 .pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
824 .map = IMX8MM_VPUG1_A53_DOMAIN,
825 },
826 .pgc = BIT(IMX8MM_PGC_VPUG1),
827 },
828
829 [IMX8MM_POWER_DOMAIN_VPUG2] = {
830 .genpd = {
831 .name = "vpu-g2",
832 },
833 .bits = {
834 .pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
835 .map = IMX8MM_VPUG2_A53_DOMAIN,
836 },
837 .pgc = BIT(IMX8MM_PGC_VPUG2),
838 },
839
840 [IMX8MM_POWER_DOMAIN_VPUH1] = {
841 .genpd = {
842 .name = "vpu-h1",
843 },
844 .bits = {
845 .pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
846 .map = IMX8MM_VPUH1_A53_DOMAIN,
847 },
848 .pgc = BIT(IMX8MM_PGC_VPUH1),
849 .keep_clocks = true,
850 },
851
852 [IMX8MM_POWER_DOMAIN_DISPMIX] = {
853 .genpd = {
854 .name = "dispmix",
855 },
856 .bits = {
857 .pxx = IMX8MM_DISPMIX_SW_Pxx_REQ,
858 .map = IMX8MM_DISPMIX_A53_DOMAIN,
859 .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
860 .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
861 },
862 .pgc = BIT(IMX8MM_PGC_DISPMIX),
863 .keep_clocks = true,
864 },
865
866 [IMX8MM_POWER_DOMAIN_MIPI] = {
867 .genpd = {
868 .name = "mipi",
869 },
870 .bits = {
871 .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
872 .map = IMX8MM_MIPI_A53_DOMAIN,
873 },
874 .pgc = BIT(IMX8MM_PGC_MIPI),
875 },
876 };
877
878 static const struct regmap_range imx8mm_yes_ranges[] = {
879 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
880 GPC_PU_PWRHSK),
881 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
882 GPC_PGC_SR(IMX8MM_PGC_MIPI)),
883 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
884 GPC_PGC_SR(IMX8MM_PGC_PCIE)),
885 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
886 GPC_PGC_SR(IMX8MM_PGC_OTG1)),
887 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
888 GPC_PGC_SR(IMX8MM_PGC_OTG2)),
889 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
890 GPC_PGC_SR(IMX8MM_PGC_DDR1)),
891 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
892 GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
893 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX),
894 GPC_PGC_SR(IMX8MM_PGC_GPUMIX)),
895 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX),
896 GPC_PGC_SR(IMX8MM_PGC_VPUMIX)),
897 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D),
898 GPC_PGC_SR(IMX8MM_PGC_GPU3D)),
899 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX),
900 GPC_PGC_SR(IMX8MM_PGC_DISPMIX)),
901 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1),
902 GPC_PGC_SR(IMX8MM_PGC_VPUG1)),
903 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2),
904 GPC_PGC_SR(IMX8MM_PGC_VPUG2)),
905 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1),
906 GPC_PGC_SR(IMX8MM_PGC_VPUH1)),
907 };
908
909 static const struct regmap_access_table imx8mm_access_table = {
910 .yes_ranges = imx8mm_yes_ranges,
911 .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
912 };
913
914 static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
915 .domains = imx8mm_pgc_domains,
916 .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
917 .reg_access_table = &imx8mm_access_table,
918 .pgc_regs = &imx7_pgc_regs,
919 };
920
921 static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
922 [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
923 .genpd = {
924 .name = "mipi-phy1",
925 },
926 .bits = {
927 .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
928 .map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
929 },
930 .pgc = BIT(IMX8MP_PGC_MIPI1),
931 },
932
933 [IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
934 .genpd = {
935 .name = "pcie-phy1",
936 },
937 .bits = {
938 .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
939 .map = IMX8MP_PCIE_PHY_A53_DOMAIN,
940 },
941 .pgc = BIT(IMX8MP_PGC_PCIE),
942 },
943
944 [IMX8MP_POWER_DOMAIN_USB1_PHY] = {
945 .genpd = {
946 .name = "usb-otg1",
947 },
948 .bits = {
949 .pxx = IMX8MP_USB1_PHY_Pxx_REQ,
950 .map = IMX8MP_USB1_PHY_A53_DOMAIN,
951 },
952 .pgc = BIT(IMX8MP_PGC_USB1),
953 },
954
955 [IMX8MP_POWER_DOMAIN_USB2_PHY] = {
956 .genpd = {
957 .name = "usb-otg2",
958 },
959 .bits = {
960 .pxx = IMX8MP_USB2_PHY_Pxx_REQ,
961 .map = IMX8MP_USB2_PHY_A53_DOMAIN,
962 },
963 .pgc = BIT(IMX8MP_PGC_USB2),
964 },
965
966 [IMX8MP_POWER_DOMAIN_MLMIX] = {
967 .genpd = {
968 .name = "mlmix",
969 },
970 .bits = {
971 .pxx = IMX8MP_MLMIX_Pxx_REQ,
972 .map = IMX8MP_MLMIX_A53_DOMAIN,
973 .hskreq = IMX8MP_MLMIX_PWRDNREQN,
974 .hskack = IMX8MP_MLMIX_PWRDNACKN,
975 },
976 .pgc = BIT(IMX8MP_PGC_MLMIX),
977 .keep_clocks = true,
978 },
979
980 [IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
981 .genpd = {
982 .name = "audiomix",
983 },
984 .bits = {
985 .pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
986 .map = IMX8MP_AUDIOMIX_A53_DOMAIN,
987 .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
988 .hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
989 },
990 .pgc = BIT(IMX8MP_PGC_AUDIOMIX),
991 .keep_clocks = true,
992 },
993
994 [IMX8MP_POWER_DOMAIN_GPU2D] = {
995 .genpd = {
996 .name = "gpu2d",
997 },
998 .bits = {
999 .pxx = IMX8MP_GPU_2D_Pxx_REQ,
1000 .map = IMX8MP_GPU2D_A53_DOMAIN,
1001 },
1002 .pgc = BIT(IMX8MP_PGC_GPU2D),
1003 },
1004
1005 [IMX8MP_POWER_DOMAIN_GPUMIX] = {
1006 .genpd = {
1007 .name = "gpumix",
1008 },
1009 .bits = {
1010 .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
1011 .map = IMX8MP_GPUMIX_A53_DOMAIN,
1012 .hskreq = IMX8MP_GPUMIX_PWRDNREQN,
1013 .hskack = IMX8MP_GPUMIX_PWRDNACKN,
1014 },
1015 .pgc = BIT(IMX8MP_PGC_GPUMIX),
1016 .keep_clocks = true,
1017 },
1018
1019 [IMX8MP_POWER_DOMAIN_VPUMIX] = {
1020 .genpd = {
1021 .name = "vpumix",
1022 },
1023 .bits = {
1024 .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
1025 .map = IMX8MP_VPUMIX_A53_DOMAIN,
1026 .hskreq = IMX8MP_VPUMIX_PWRDNREQN,
1027 .hskack = IMX8MP_VPUMIX_PWRDNACKN,
1028 },
1029 .pgc = BIT(IMX8MP_PGC_VPUMIX),
1030 .keep_clocks = true,
1031 },
1032
1033 [IMX8MP_POWER_DOMAIN_GPU3D] = {
1034 .genpd = {
1035 .name = "gpu3d",
1036 },
1037 .bits = {
1038 .pxx = IMX8MP_GPU_3D_Pxx_REQ,
1039 .map = IMX8MP_GPU3D_A53_DOMAIN,
1040 },
1041 .pgc = BIT(IMX8MP_PGC_GPU3D),
1042 },
1043
1044 [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
1045 .genpd = {
1046 .name = "mediamix",
1047 },
1048 .bits = {
1049 .pxx = IMX8MP_MEDIMIX_Pxx_REQ,
1050 .map = IMX8MP_MEDIAMIX_A53_DOMAIN,
1051 .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
1052 .hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
1053 },
1054 .pgc = BIT(IMX8MP_PGC_MEDIAMIX),
1055 .keep_clocks = true,
1056 },
1057
1058 [IMX8MP_POWER_DOMAIN_VPU_G1] = {
1059 .genpd = {
1060 .name = "vpu-g1",
1061 },
1062 .bits = {
1063 .pxx = IMX8MP_VPU_G1_Pxx_REQ,
1064 .map = IMX8MP_VPU_G1_A53_DOMAIN,
1065 },
1066 .pgc = BIT(IMX8MP_PGC_VPU_G1),
1067 },
1068
1069 [IMX8MP_POWER_DOMAIN_VPU_G2] = {
1070 .genpd = {
1071 .name = "vpu-g2",
1072 },
1073 .bits = {
1074 .pxx = IMX8MP_VPU_G2_Pxx_REQ,
1075 .map = IMX8MP_VPU_G2_A53_DOMAIN
1076 },
1077 .pgc = BIT(IMX8MP_PGC_VPU_G2),
1078 },
1079
1080 [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
1081 .genpd = {
1082 .name = "vpu-h1",
1083 },
1084 .bits = {
1085 .pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
1086 .map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
1087 },
1088 .pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
1089 },
1090
1091 [IMX8MP_POWER_DOMAIN_HDMIMIX] = {
1092 .genpd = {
1093 .name = "hdmimix",
1094 },
1095 .bits = {
1096 .pxx = IMX8MP_HDMIMIX_Pxx_REQ,
1097 .map = IMX8MP_HDMIMIX_A53_DOMAIN,
1098 .hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
1099 .hskack = IMX8MP_HDMIMIX_PWRDNACKN,
1100 },
1101 .pgc = BIT(IMX8MP_PGC_HDMIMIX),
1102 .keep_clocks = true,
1103 },
1104
1105 [IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
1106 .genpd = {
1107 .name = "hdmi-phy",
1108 },
1109 .bits = {
1110 .pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
1111 .map = IMX8MP_HDMI_PHY_A53_DOMAIN,
1112 },
1113 .pgc = BIT(IMX8MP_PGC_HDMI),
1114 },
1115
1116 [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
1117 .genpd = {
1118 .name = "mipi-phy2",
1119 },
1120 .bits = {
1121 .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
1122 .map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
1123 },
1124 .pgc = BIT(IMX8MP_PGC_MIPI2),
1125 },
1126
1127 [IMX8MP_POWER_DOMAIN_HSIOMIX] = {
1128 .genpd = {
1129 .name = "hsiomix",
1130 },
1131 .bits = {
1132 .pxx = IMX8MP_HSIOMIX_Pxx_REQ,
1133 .map = IMX8MP_HSIOMIX_A53_DOMAIN,
1134 .hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
1135 .hskack = IMX8MP_HSIOMIX_PWRDNACKN,
1136 },
1137 .pgc = BIT(IMX8MP_PGC_HSIOMIX),
1138 .keep_clocks = true,
1139 },
1140
1141 [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
1142 .genpd = {
1143 .name = "mediamix-isp-dwp",
1144 },
1145 .bits = {
1146 .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
1147 .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
1148 },
1149 .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
1150 },
1151 };
1152
1153 static const struct regmap_range imx8mp_yes_ranges[] = {
1154 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
1155 IMX8MP_GPC_PGC_CPU_MAPPING),
1156 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
1157 GPC_PGC_SR(IMX8MP_PGC_NOC)),
1158 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
1159 GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
1160 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
1161 GPC_PGC_SR(IMX8MP_PGC_PCIE)),
1162 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
1163 GPC_PGC_SR(IMX8MP_PGC_USB1)),
1164 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
1165 GPC_PGC_SR(IMX8MP_PGC_USB2)),
1166 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
1167 GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
1168 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
1169 GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
1170 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
1171 GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
1172 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
1173 GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
1174 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
1175 GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
1176 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
1177 GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
1178 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
1179 GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
1180 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
1181 GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
1182 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
1183 GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
1184 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
1185 GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
1186 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
1187 GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
1188 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
1189 GPC_PGC_SR(IMX8MP_PGC_HDMI)),
1190 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
1191 GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
1192 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
1193 GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
1194 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
1195 GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
1196 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
1197 GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
1198 };
1199
1200 static const struct regmap_access_table imx8mp_access_table = {
1201 .yes_ranges = imx8mp_yes_ranges,
1202 .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges),
1203 };
1204
1205 static const struct imx_pgc_regs imx8mp_pgc_regs = {
1206 .map = IMX8MP_GPC_PGC_CPU_MAPPING,
1207 .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
1208 .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
1209 .hsk = IMX8MP_GPC_PU_PWRHSK,
1210 };
1211 static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
1212 .domains = imx8mp_pgc_domains,
1213 .domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
1214 .reg_access_table = &imx8mp_access_table,
1215 .pgc_regs = &imx8mp_pgc_regs,
1216 };
1217
1218 static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
1219 [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
1220 .genpd = {
1221 .name = "hsiomix",
1222 },
1223 .bits = {
1224 .pxx = 0, /* no power sequence control */
1225 .map = 0, /* no power sequence control */
1226 .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
1227 .hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
1228 },
1229 .keep_clocks = true,
1230 },
1231
1232 [IMX8MN_POWER_DOMAIN_OTG1] = {
1233 .genpd = {
1234 .name = "usb-otg1",
1235 },
1236 .bits = {
1237 .pxx = IMX8MN_OTG1_SW_Pxx_REQ,
1238 .map = IMX8MN_OTG1_A53_DOMAIN,
1239 },
1240 .pgc = BIT(IMX8MN_PGC_OTG1),
1241 },
1242
1243 [IMX8MN_POWER_DOMAIN_GPUMIX] = {
1244 .genpd = {
1245 .name = "gpumix",
1246 },
1247 .bits = {
1248 .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
1249 .map = IMX8MN_GPUMIX_A53_DOMAIN,
1250 .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
1251 .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
1252 },
1253 .pgc = BIT(IMX8MN_PGC_GPUMIX),
1254 .keep_clocks = true,
1255 },
1256
1257 [IMX8MN_POWER_DOMAIN_DISPMIX] = {
1258 .genpd = {
1259 .name = "dispmix",
1260 },
1261 .bits = {
1262 .pxx = IMX8MN_DISPMIX_SW_Pxx_REQ,
1263 .map = IMX8MN_DISPMIX_A53_DOMAIN,
1264 .hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN,
1265 .hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN,
1266 },
1267 .pgc = BIT(IMX8MN_PGC_DISPMIX),
1268 .keep_clocks = true,
1269 },
1270
1271 [IMX8MN_POWER_DOMAIN_MIPI] = {
1272 .genpd = {
1273 .name = "mipi",
1274 },
1275 .bits = {
1276 .pxx = IMX8MN_MIPI_SW_Pxx_REQ,
1277 .map = IMX8MN_MIPI_A53_DOMAIN,
1278 },
1279 .pgc = BIT(IMX8MN_PGC_MIPI),
1280 },
1281 };
1282
1283 static const struct regmap_range imx8mn_yes_ranges[] = {
1284 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
1285 GPC_PU_PWRHSK),
1286 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
1287 GPC_PGC_SR(IMX8MN_PGC_MIPI)),
1288 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
1289 GPC_PGC_SR(IMX8MN_PGC_OTG1)),
1290 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
1291 GPC_PGC_SR(IMX8MN_PGC_DDR1)),
1292 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
1293 GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
1294 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
1295 GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
1296 };
1297
1298 static const struct regmap_access_table imx8mn_access_table = {
1299 .yes_ranges = imx8mn_yes_ranges,
1300 .n_yes_ranges = ARRAY_SIZE(imx8mn_yes_ranges),
1301 };
1302
1303 static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
1304 .domains = imx8mn_pgc_domains,
1305 .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
1306 .reg_access_table = &imx8mn_access_table,
1307 .pgc_regs = &imx7_pgc_regs,
1308 };
1309
imx_pgc_domain_probe(struct platform_device * pdev)1310 static int imx_pgc_domain_probe(struct platform_device *pdev)
1311 {
1312 struct imx_pgc_domain *domain = pdev->dev.platform_data;
1313 int ret;
1314
1315 domain->dev = &pdev->dev;
1316
1317 domain->regulator = devm_regulator_get_optional(domain->dev, "power");
1318 if (IS_ERR(domain->regulator)) {
1319 if (PTR_ERR(domain->regulator) != -ENODEV)
1320 return dev_err_probe(domain->dev, PTR_ERR(domain->regulator),
1321 "Failed to get domain's regulator\n");
1322 } else if (domain->voltage) {
1323 regulator_set_voltage(domain->regulator,
1324 domain->voltage, domain->voltage);
1325 }
1326
1327 domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks);
1328 if (domain->num_clks < 0)
1329 return dev_err_probe(domain->dev, domain->num_clks,
1330 "Failed to get domain's clocks\n");
1331
1332 domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev);
1333 if (IS_ERR(domain->reset))
1334 return dev_err_probe(domain->dev, PTR_ERR(domain->reset),
1335 "Failed to get domain's resets\n");
1336
1337 pm_runtime_enable(domain->dev);
1338
1339 if (domain->bits.map)
1340 regmap_update_bits(domain->regmap, domain->regs->map,
1341 domain->bits.map, domain->bits.map);
1342
1343 ret = pm_genpd_init(&domain->genpd, NULL, true);
1344 if (ret) {
1345 dev_err(domain->dev, "Failed to init power domain\n");
1346 goto out_domain_unmap;
1347 }
1348
1349 if (IS_ENABLED(CONFIG_LOCKDEP) &&
1350 of_property_read_bool(domain->dev->of_node, "power-domains"))
1351 lockdep_set_subclass(&domain->genpd.mlock, 1);
1352
1353 ret = of_genpd_add_provider_simple(domain->dev->of_node,
1354 &domain->genpd);
1355 if (ret) {
1356 dev_err(domain->dev, "Failed to add genpd provider\n");
1357 goto out_genpd_remove;
1358 }
1359
1360 return 0;
1361
1362 out_genpd_remove:
1363 pm_genpd_remove(&domain->genpd);
1364 out_domain_unmap:
1365 if (domain->bits.map)
1366 regmap_update_bits(domain->regmap, domain->regs->map,
1367 domain->bits.map, 0);
1368 pm_runtime_disable(domain->dev);
1369
1370 return ret;
1371 }
1372
imx_pgc_domain_remove(struct platform_device * pdev)1373 static int imx_pgc_domain_remove(struct platform_device *pdev)
1374 {
1375 struct imx_pgc_domain *domain = pdev->dev.platform_data;
1376
1377 of_genpd_del_provider(domain->dev->of_node);
1378 pm_genpd_remove(&domain->genpd);
1379
1380 if (domain->bits.map)
1381 regmap_update_bits(domain->regmap, domain->regs->map,
1382 domain->bits.map, 0);
1383
1384 pm_runtime_disable(domain->dev);
1385
1386 return 0;
1387 }
1388
1389 #ifdef CONFIG_PM_SLEEP
imx_pgc_domain_suspend(struct device * dev)1390 static int imx_pgc_domain_suspend(struct device *dev)
1391 {
1392 int ret;
1393
1394 /*
1395 * This may look strange, but is done so the generic PM_SLEEP code
1396 * can power down our domain and more importantly power it up again
1397 * after resume, without tripping over our usage of runtime PM to
1398 * power up/down the nested domains.
1399 */
1400 ret = pm_runtime_get_sync(dev);
1401 if (ret < 0) {
1402 pm_runtime_put_noidle(dev);
1403 return ret;
1404 }
1405
1406 return 0;
1407 }
1408
imx_pgc_domain_resume(struct device * dev)1409 static int imx_pgc_domain_resume(struct device *dev)
1410 {
1411 return pm_runtime_put(dev);
1412 }
1413 #endif
1414
1415 static const struct dev_pm_ops imx_pgc_domain_pm_ops = {
1416 SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume)
1417 };
1418
1419 static const struct platform_device_id imx_pgc_domain_id[] = {
1420 { "imx-pgc-domain", },
1421 { },
1422 };
1423
1424 static struct platform_driver imx_pgc_domain_driver = {
1425 .driver = {
1426 .name = "imx-pgc",
1427 .pm = &imx_pgc_domain_pm_ops,
1428 },
1429 .probe = imx_pgc_domain_probe,
1430 .remove = imx_pgc_domain_remove,
1431 .id_table = imx_pgc_domain_id,
1432 };
builtin_platform_driver(imx_pgc_domain_driver)1433 builtin_platform_driver(imx_pgc_domain_driver)
1434
1435 static int imx_gpcv2_probe(struct platform_device *pdev)
1436 {
1437 const struct imx_pgc_domain_data *domain_data =
1438 of_device_get_match_data(&pdev->dev);
1439
1440 struct regmap_config regmap_config = {
1441 .reg_bits = 32,
1442 .val_bits = 32,
1443 .reg_stride = 4,
1444 .rd_table = domain_data->reg_access_table,
1445 .wr_table = domain_data->reg_access_table,
1446 .max_register = SZ_4K,
1447 };
1448 struct device *dev = &pdev->dev;
1449 struct device_node *pgc_np, *np;
1450 struct regmap *regmap;
1451 void __iomem *base;
1452 int ret;
1453
1454 pgc_np = of_get_child_by_name(dev->of_node, "pgc");
1455 if (!pgc_np) {
1456 dev_err(dev, "No power domains specified in DT\n");
1457 return -EINVAL;
1458 }
1459
1460 base = devm_platform_ioremap_resource(pdev, 0);
1461 if (IS_ERR(base))
1462 return PTR_ERR(base);
1463
1464 regmap = devm_regmap_init_mmio(dev, base, ®map_config);
1465 if (IS_ERR(regmap)) {
1466 ret = PTR_ERR(regmap);
1467 dev_err(dev, "failed to init regmap (%d)\n", ret);
1468 return ret;
1469 }
1470
1471 for_each_child_of_node(pgc_np, np) {
1472 struct platform_device *pd_pdev;
1473 struct imx_pgc_domain *domain;
1474 u32 domain_index;
1475
1476 if (!of_device_is_available(np))
1477 continue;
1478
1479 ret = of_property_read_u32(np, "reg", &domain_index);
1480 if (ret) {
1481 dev_err(dev, "Failed to read 'reg' property\n");
1482 of_node_put(np);
1483 return ret;
1484 }
1485
1486 if (domain_index >= domain_data->domains_num) {
1487 dev_warn(dev,
1488 "Domain index %d is out of bounds\n",
1489 domain_index);
1490 continue;
1491 }
1492
1493 pd_pdev = platform_device_alloc("imx-pgc-domain",
1494 domain_index);
1495 if (!pd_pdev) {
1496 dev_err(dev, "Failed to allocate platform device\n");
1497 of_node_put(np);
1498 return -ENOMEM;
1499 }
1500
1501 ret = platform_device_add_data(pd_pdev,
1502 &domain_data->domains[domain_index],
1503 sizeof(domain_data->domains[domain_index]));
1504 if (ret) {
1505 platform_device_put(pd_pdev);
1506 of_node_put(np);
1507 return ret;
1508 }
1509
1510 domain = pd_pdev->dev.platform_data;
1511 domain->regmap = regmap;
1512 domain->regs = domain_data->pgc_regs;
1513
1514 domain->genpd.power_on = imx_pgc_power_up;
1515 domain->genpd.power_off = imx_pgc_power_down;
1516
1517 pd_pdev->dev.parent = dev;
1518 pd_pdev->dev.of_node = np;
1519
1520 ret = platform_device_add(pd_pdev);
1521 if (ret) {
1522 platform_device_put(pd_pdev);
1523 of_node_put(np);
1524 return ret;
1525 }
1526 }
1527
1528 return 0;
1529 }
1530
1531 static const struct of_device_id imx_gpcv2_dt_ids[] = {
1532 { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
1533 { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
1534 { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
1535 { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
1536 { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
1537 { }
1538 };
1539
1540 static struct platform_driver imx_gpc_driver = {
1541 .driver = {
1542 .name = "imx-gpcv2",
1543 .of_match_table = imx_gpcv2_dt_ids,
1544 },
1545 .probe = imx_gpcv2_probe,
1546 };
1547 builtin_platform_driver(imx_gpc_driver)
1548