1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Thunderbolt driver - quirks
4 *
5 * Copyright (c) 2020 Mario Limonciello <mario.limonciello@dell.com>
6 */
7
8 #include "tb.h"
9
quirk_force_power_link(struct tb_switch * sw)10 static void quirk_force_power_link(struct tb_switch *sw)
11 {
12 sw->quirks |= QUIRK_FORCE_POWER_LINK_CONTROLLER;
13 }
14
quirk_dp_credit_allocation(struct tb_switch * sw)15 static void quirk_dp_credit_allocation(struct tb_switch *sw)
16 {
17 if (sw->credit_allocation && sw->min_dp_main_credits == 56) {
18 sw->min_dp_main_credits = 18;
19 tb_sw_dbg(sw, "quirked DP main: %u\n", sw->min_dp_main_credits);
20 }
21 }
22
quirk_clx_disable(struct tb_switch * sw)23 static void quirk_clx_disable(struct tb_switch *sw)
24 {
25 sw->quirks |= QUIRK_NO_CLX;
26 tb_sw_dbg(sw, "disabling CL states\n");
27 }
28
quirk_usb3_maximum_bandwidth(struct tb_switch * sw)29 static void quirk_usb3_maximum_bandwidth(struct tb_switch *sw)
30 {
31 struct tb_port *port;
32
33 if (tb_switch_is_icm(sw))
34 return;
35
36 tb_switch_for_each_port(sw, port) {
37 if (!tb_port_is_usb3_down(port))
38 continue;
39 port->max_bw = 16376;
40 tb_port_dbg(port, "USB3 maximum bandwidth limited to %u Mb/s\n",
41 port->max_bw);
42 }
43 }
44
45 struct tb_quirk {
46 u16 hw_vendor_id;
47 u16 hw_device_id;
48 u16 vendor;
49 u16 device;
50 void (*hook)(struct tb_switch *sw);
51 };
52
53 static const struct tb_quirk tb_quirks[] = {
54 /* Dell WD19TB supports self-authentication on unplug */
55 { 0x0000, 0x0000, 0x00d4, 0xb070, quirk_force_power_link },
56 { 0x0000, 0x0000, 0x00d4, 0xb071, quirk_force_power_link },
57 /*
58 * Intel Goshen Ridge NVM 27 and before report wrong number of
59 * DP buffers.
60 */
61 { 0x8087, 0x0b26, 0x0000, 0x0000, quirk_dp_credit_allocation },
62 /*
63 * Limit the maximum USB3 bandwidth for the following Intel USB4
64 * host routers due to a hardware issue.
65 */
66 { 0x8087, PCI_DEVICE_ID_INTEL_ADL_NHI0, 0x0000, 0x0000,
67 quirk_usb3_maximum_bandwidth },
68 { 0x8087, PCI_DEVICE_ID_INTEL_ADL_NHI1, 0x0000, 0x0000,
69 quirk_usb3_maximum_bandwidth },
70 { 0x8087, PCI_DEVICE_ID_INTEL_RPL_NHI0, 0x0000, 0x0000,
71 quirk_usb3_maximum_bandwidth },
72 { 0x8087, PCI_DEVICE_ID_INTEL_RPL_NHI1, 0x0000, 0x0000,
73 quirk_usb3_maximum_bandwidth },
74 { 0x8087, PCI_DEVICE_ID_INTEL_MTL_M_NHI0, 0x0000, 0x0000,
75 quirk_usb3_maximum_bandwidth },
76 { 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI0, 0x0000, 0x0000,
77 quirk_usb3_maximum_bandwidth },
78 { 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI1, 0x0000, 0x0000,
79 quirk_usb3_maximum_bandwidth },
80 { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI, 0x0000, 0x0000,
81 quirk_usb3_maximum_bandwidth },
82 { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI, 0x0000, 0x0000,
83 quirk_usb3_maximum_bandwidth },
84 { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE, 0x0000, 0x0000,
85 quirk_usb3_maximum_bandwidth },
86 { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE, 0x0000, 0x0000,
87 quirk_usb3_maximum_bandwidth },
88 /*
89 * CLx is not supported on AMD USB4 Yellow Carp and Pink Sardine platforms.
90 */
91 { 0x0438, 0x0208, 0x0000, 0x0000, quirk_clx_disable },
92 { 0x0438, 0x0209, 0x0000, 0x0000, quirk_clx_disable },
93 { 0x0438, 0x020a, 0x0000, 0x0000, quirk_clx_disable },
94 { 0x0438, 0x020b, 0x0000, 0x0000, quirk_clx_disable },
95 };
96
97 /**
98 * tb_check_quirks() - Check for quirks to apply
99 * @sw: Thunderbolt switch
100 *
101 * Apply any quirks for the Thunderbolt controller.
102 */
tb_check_quirks(struct tb_switch * sw)103 void tb_check_quirks(struct tb_switch *sw)
104 {
105 int i;
106
107 for (i = 0; i < ARRAY_SIZE(tb_quirks); i++) {
108 const struct tb_quirk *q = &tb_quirks[i];
109
110 if (q->hw_vendor_id && q->hw_vendor_id != sw->config.vendor_id)
111 continue;
112 if (q->hw_device_id && q->hw_device_id != sw->config.device_id)
113 continue;
114 if (q->vendor && q->vendor != sw->vendor)
115 continue;
116 if (q->device && q->device != sw->device)
117 continue;
118
119 q->hook(sw);
120 }
121 }
122