1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for CPM (SCC/SMC) serial ports; core driver
4 *
5 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
6 * Based on ppc8xx.c by Thomas Gleixner
7 * Based on drivers/serial/amba.c by Russell King
8 *
9 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
10 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
11 *
12 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
13 * (C) 2004 Intracom, S.A.
14 * (C) 2005-2006 MontaVista Software, Inc.
15 * Vitaly Bordug <vbordug@ru.mvista.com>
16 */
17
18 #include <linux/module.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/ioport.h>
22 #include <linux/init.h>
23 #include <linux/serial.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/device.h>
27 #include <linux/memblock.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/fs_uart_pd.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_platform.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/clk.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/delay.h>
39 #include <asm/fs_pd.h>
40 #include <asm/udbg.h>
41
42 #include <linux/serial_core.h>
43 #include <linux/kernel.h>
44
45 #include "cpm_uart.h"
46
47
48 /**************************************************************/
49
50 static int cpm_uart_tx_pump(struct uart_port *port);
51 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
52 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
53 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
54
55 /**************************************************************/
56
57 #define HW_BUF_SPD_THRESHOLD 2400
58
59 /*
60 * Check, if transmit buffers are processed
61 */
cpm_uart_tx_empty(struct uart_port * port)62 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
63 {
64 struct uart_cpm_port *pinfo =
65 container_of(port, struct uart_cpm_port, port);
66 cbd_t __iomem *bdp = pinfo->tx_bd_base;
67 int ret = 0;
68
69 while (1) {
70 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
71 break;
72
73 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
74 ret = TIOCSER_TEMT;
75 break;
76 }
77 bdp++;
78 }
79
80 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
81
82 return ret;
83 }
84
cpm_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)85 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
86 {
87 struct uart_cpm_port *pinfo =
88 container_of(port, struct uart_cpm_port, port);
89
90 if (pinfo->gpios[GPIO_RTS])
91 gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
92
93 if (pinfo->gpios[GPIO_DTR])
94 gpiod_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
95 }
96
cpm_uart_get_mctrl(struct uart_port * port)97 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
98 {
99 struct uart_cpm_port *pinfo =
100 container_of(port, struct uart_cpm_port, port);
101 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
102
103 if (pinfo->gpios[GPIO_CTS]) {
104 if (gpiod_get_value(pinfo->gpios[GPIO_CTS]))
105 mctrl &= ~TIOCM_CTS;
106 }
107
108 if (pinfo->gpios[GPIO_DSR]) {
109 if (gpiod_get_value(pinfo->gpios[GPIO_DSR]))
110 mctrl &= ~TIOCM_DSR;
111 }
112
113 if (pinfo->gpios[GPIO_DCD]) {
114 if (gpiod_get_value(pinfo->gpios[GPIO_DCD]))
115 mctrl &= ~TIOCM_CAR;
116 }
117
118 if (pinfo->gpios[GPIO_RI]) {
119 if (!gpiod_get_value(pinfo->gpios[GPIO_RI]))
120 mctrl |= TIOCM_RNG;
121 }
122
123 return mctrl;
124 }
125
126 /*
127 * Stop transmitter
128 */
cpm_uart_stop_tx(struct uart_port * port)129 static void cpm_uart_stop_tx(struct uart_port *port)
130 {
131 struct uart_cpm_port *pinfo =
132 container_of(port, struct uart_cpm_port, port);
133 smc_t __iomem *smcp = pinfo->smcp;
134 scc_t __iomem *sccp = pinfo->sccp;
135
136 pr_debug("CPM uart[%d]:stop tx\n", port->line);
137
138 if (IS_SMC(pinfo))
139 clrbits8(&smcp->smc_smcm, SMCM_TX);
140 else
141 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
142 }
143
144 /*
145 * Start transmitter
146 */
cpm_uart_start_tx(struct uart_port * port)147 static void cpm_uart_start_tx(struct uart_port *port)
148 {
149 struct uart_cpm_port *pinfo =
150 container_of(port, struct uart_cpm_port, port);
151 smc_t __iomem *smcp = pinfo->smcp;
152 scc_t __iomem *sccp = pinfo->sccp;
153
154 pr_debug("CPM uart[%d]:start tx\n", port->line);
155
156 if (IS_SMC(pinfo)) {
157 if (in_8(&smcp->smc_smcm) & SMCM_TX)
158 return;
159 } else {
160 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
161 return;
162 }
163
164 if (cpm_uart_tx_pump(port) != 0) {
165 if (IS_SMC(pinfo)) {
166 setbits8(&smcp->smc_smcm, SMCM_TX);
167 } else {
168 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
169 }
170 }
171 }
172
173 /*
174 * Stop receiver
175 */
cpm_uart_stop_rx(struct uart_port * port)176 static void cpm_uart_stop_rx(struct uart_port *port)
177 {
178 struct uart_cpm_port *pinfo =
179 container_of(port, struct uart_cpm_port, port);
180 smc_t __iomem *smcp = pinfo->smcp;
181 scc_t __iomem *sccp = pinfo->sccp;
182
183 pr_debug("CPM uart[%d]:stop rx\n", port->line);
184
185 if (IS_SMC(pinfo))
186 clrbits8(&smcp->smc_smcm, SMCM_RX);
187 else
188 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
189 }
190
191 /*
192 * Generate a break.
193 */
cpm_uart_break_ctl(struct uart_port * port,int break_state)194 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
195 {
196 struct uart_cpm_port *pinfo =
197 container_of(port, struct uart_cpm_port, port);
198
199 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
200 break_state);
201
202 if (break_state)
203 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
204 else
205 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
206 }
207
208 /*
209 * Transmit characters, refill buffer descriptor, if possible
210 */
cpm_uart_int_tx(struct uart_port * port)211 static void cpm_uart_int_tx(struct uart_port *port)
212 {
213 pr_debug("CPM uart[%d]:TX INT\n", port->line);
214
215 cpm_uart_tx_pump(port);
216 }
217
218 #ifdef CONFIG_CONSOLE_POLL
219 static int serial_polled;
220 #endif
221
222 /*
223 * Receive characters
224 */
cpm_uart_int_rx(struct uart_port * port)225 static void cpm_uart_int_rx(struct uart_port *port)
226 {
227 int i;
228 unsigned char ch;
229 u8 *cp;
230 struct tty_port *tport = &port->state->port;
231 struct uart_cpm_port *pinfo =
232 container_of(port, struct uart_cpm_port, port);
233 cbd_t __iomem *bdp;
234 u16 status;
235 unsigned int flg;
236
237 pr_debug("CPM uart[%d]:RX INT\n", port->line);
238
239 /* Just loop through the closed BDs and copy the characters into
240 * the buffer.
241 */
242 bdp = pinfo->rx_cur;
243 for (;;) {
244 #ifdef CONFIG_CONSOLE_POLL
245 if (unlikely(serial_polled)) {
246 serial_polled = 0;
247 return;
248 }
249 #endif
250 /* get status */
251 status = in_be16(&bdp->cbd_sc);
252 /* If this one is empty, return happy */
253 if (status & BD_SC_EMPTY)
254 break;
255
256 /* get number of characters, and check spce in flip-buffer */
257 i = in_be16(&bdp->cbd_datlen);
258
259 /* If we have not enough room in tty flip buffer, then we try
260 * later, which will be the next rx-interrupt or a timeout
261 */
262 if (tty_buffer_request_room(tport, i) < i) {
263 printk(KERN_WARNING "No room in flip buffer\n");
264 return;
265 }
266
267 /* get pointer */
268 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
269
270 /* loop through the buffer */
271 while (i-- > 0) {
272 ch = *cp++;
273 port->icount.rx++;
274 flg = TTY_NORMAL;
275
276 if (status &
277 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
278 goto handle_error;
279 if (uart_handle_sysrq_char(port, ch))
280 continue;
281 #ifdef CONFIG_CONSOLE_POLL
282 if (unlikely(serial_polled)) {
283 serial_polled = 0;
284 return;
285 }
286 #endif
287 error_return:
288 tty_insert_flip_char(tport, ch, flg);
289
290 } /* End while (i--) */
291
292 /* This BD is ready to be used again. Clear status. get next */
293 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
294 BD_SC_OV | BD_SC_ID);
295 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
296
297 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
298 bdp = pinfo->rx_bd_base;
299 else
300 bdp++;
301
302 } /* End for (;;) */
303
304 /* Write back buffer pointer */
305 pinfo->rx_cur = bdp;
306
307 /* activate BH processing */
308 tty_flip_buffer_push(tport);
309
310 return;
311
312 /* Error processing */
313
314 handle_error:
315 /* Statistics */
316 if (status & BD_SC_BR)
317 port->icount.brk++;
318 if (status & BD_SC_PR)
319 port->icount.parity++;
320 if (status & BD_SC_FR)
321 port->icount.frame++;
322 if (status & BD_SC_OV)
323 port->icount.overrun++;
324
325 /* Mask out ignored conditions */
326 status &= port->read_status_mask;
327
328 /* Handle the remaining ones */
329 if (status & BD_SC_BR)
330 flg = TTY_BREAK;
331 else if (status & BD_SC_PR)
332 flg = TTY_PARITY;
333 else if (status & BD_SC_FR)
334 flg = TTY_FRAME;
335
336 /* overrun does not affect the current character ! */
337 if (status & BD_SC_OV) {
338 ch = 0;
339 flg = TTY_OVERRUN;
340 /* We skip this buffer */
341 /* CHECK: Is really nothing senseful there */
342 /* ASSUMPTION: it contains nothing valid */
343 i = 0;
344 }
345 port->sysrq = 0;
346 goto error_return;
347 }
348
349 /*
350 * Asynchron mode interrupt handler
351 */
cpm_uart_int(int irq,void * data)352 static irqreturn_t cpm_uart_int(int irq, void *data)
353 {
354 u8 events;
355 struct uart_port *port = data;
356 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
357 smc_t __iomem *smcp = pinfo->smcp;
358 scc_t __iomem *sccp = pinfo->sccp;
359
360 pr_debug("CPM uart[%d]:IRQ\n", port->line);
361
362 if (IS_SMC(pinfo)) {
363 events = in_8(&smcp->smc_smce);
364 out_8(&smcp->smc_smce, events);
365 if (events & SMCM_BRKE)
366 uart_handle_break(port);
367 if (events & SMCM_RX)
368 cpm_uart_int_rx(port);
369 if (events & SMCM_TX)
370 cpm_uart_int_tx(port);
371 } else {
372 events = in_be16(&sccp->scc_scce);
373 out_be16(&sccp->scc_scce, events);
374 if (events & UART_SCCM_BRKE)
375 uart_handle_break(port);
376 if (events & UART_SCCM_RX)
377 cpm_uart_int_rx(port);
378 if (events & UART_SCCM_TX)
379 cpm_uart_int_tx(port);
380 }
381 return (events) ? IRQ_HANDLED : IRQ_NONE;
382 }
383
cpm_uart_startup(struct uart_port * port)384 static int cpm_uart_startup(struct uart_port *port)
385 {
386 int retval;
387 struct uart_cpm_port *pinfo =
388 container_of(port, struct uart_cpm_port, port);
389
390 pr_debug("CPM uart[%d]:startup\n", port->line);
391
392 /* If the port is not the console, make sure rx is disabled. */
393 if (!(pinfo->flags & FLAG_CONSOLE)) {
394 /* Disable UART rx */
395 if (IS_SMC(pinfo)) {
396 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
397 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
398 } else {
399 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
400 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
401 }
402 cpm_uart_initbd(pinfo);
403 if (IS_SMC(pinfo)) {
404 out_be32(&pinfo->smcup->smc_rstate, 0);
405 out_be32(&pinfo->smcup->smc_tstate, 0);
406 out_be16(&pinfo->smcup->smc_rbptr,
407 in_be16(&pinfo->smcup->smc_rbase));
408 out_be16(&pinfo->smcup->smc_tbptr,
409 in_be16(&pinfo->smcup->smc_tbase));
410 } else {
411 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
412 }
413 }
414 /* Install interrupt handler. */
415 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
416 if (retval)
417 return retval;
418
419 /* Startup rx-int */
420 if (IS_SMC(pinfo)) {
421 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
422 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
423 } else {
424 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
425 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
426 }
427
428 return 0;
429 }
430
cpm_uart_wait_until_send(struct uart_cpm_port * pinfo)431 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
432 {
433 set_current_state(TASK_UNINTERRUPTIBLE);
434 schedule_timeout(pinfo->wait_closing);
435 }
436
437 /*
438 * Shutdown the uart
439 */
cpm_uart_shutdown(struct uart_port * port)440 static void cpm_uart_shutdown(struct uart_port *port)
441 {
442 struct uart_cpm_port *pinfo =
443 container_of(port, struct uart_cpm_port, port);
444
445 pr_debug("CPM uart[%d]:shutdown\n", port->line);
446
447 /* free interrupt handler */
448 free_irq(port->irq, port);
449
450 /* If the port is not the console, disable Rx and Tx. */
451 if (!(pinfo->flags & FLAG_CONSOLE)) {
452 /* Wait for all the BDs marked sent */
453 while(!cpm_uart_tx_empty(port)) {
454 set_current_state(TASK_UNINTERRUPTIBLE);
455 schedule_timeout(2);
456 }
457
458 if (pinfo->wait_closing)
459 cpm_uart_wait_until_send(pinfo);
460
461 /* Stop uarts */
462 if (IS_SMC(pinfo)) {
463 smc_t __iomem *smcp = pinfo->smcp;
464 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
465 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
466 } else {
467 scc_t __iomem *sccp = pinfo->sccp;
468 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
469 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
470 }
471
472 /* Shut them really down and reinit buffer descriptors */
473 if (IS_SMC(pinfo)) {
474 out_be16(&pinfo->smcup->smc_brkcr, 0);
475 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
476 } else {
477 out_be16(&pinfo->sccup->scc_brkcr, 0);
478 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
479 }
480
481 cpm_uart_initbd(pinfo);
482 }
483 }
484
cpm_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)485 static void cpm_uart_set_termios(struct uart_port *port,
486 struct ktermios *termios,
487 const struct ktermios *old)
488 {
489 int baud;
490 unsigned long flags;
491 u16 cval, scval, prev_mode;
492 struct uart_cpm_port *pinfo =
493 container_of(port, struct uart_cpm_port, port);
494 smc_t __iomem *smcp = pinfo->smcp;
495 scc_t __iomem *sccp = pinfo->sccp;
496 int maxidl;
497
498 pr_debug("CPM uart[%d]:set_termios\n", port->line);
499
500 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
501 if (baud < HW_BUF_SPD_THRESHOLD || port->flags & UPF_LOW_LATENCY)
502 pinfo->rx_fifosize = 1;
503 else
504 pinfo->rx_fifosize = RX_BUF_SIZE;
505
506 /* MAXIDL is the timeout after which a receive buffer is closed
507 * when not full if no more characters are received.
508 * We calculate it from the baudrate so that the duration is
509 * always the same at standard rates: about 4ms.
510 */
511 maxidl = baud / 2400;
512 if (maxidl < 1)
513 maxidl = 1;
514 if (maxidl > 0x10)
515 maxidl = 0x10;
516
517 cval = 0;
518 scval = 0;
519
520 if (termios->c_cflag & CSTOPB) {
521 cval |= SMCMR_SL; /* Two stops */
522 scval |= SCU_PSMR_SL;
523 }
524
525 if (termios->c_cflag & PARENB) {
526 cval |= SMCMR_PEN;
527 scval |= SCU_PSMR_PEN;
528 if (!(termios->c_cflag & PARODD)) {
529 cval |= SMCMR_PM_EVEN;
530 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
531 }
532 }
533
534 /*
535 * Update the timeout
536 */
537 uart_update_timeout(port, termios->c_cflag, baud);
538
539 /*
540 * Set up parity check flag
541 */
542 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
543 if (termios->c_iflag & INPCK)
544 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
545 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
546 port->read_status_mask |= BD_SC_BR;
547
548 /*
549 * Characters to ignore
550 */
551 port->ignore_status_mask = 0;
552 if (termios->c_iflag & IGNPAR)
553 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
554 if (termios->c_iflag & IGNBRK) {
555 port->ignore_status_mask |= BD_SC_BR;
556 /*
557 * If we're ignore parity and break indicators, ignore
558 * overruns too. (For real raw support).
559 */
560 if (termios->c_iflag & IGNPAR)
561 port->ignore_status_mask |= BD_SC_OV;
562 }
563 /*
564 * !!! ignore all characters if CREAD is not set
565 */
566 if ((termios->c_cflag & CREAD) == 0)
567 port->read_status_mask &= ~BD_SC_EMPTY;
568
569 spin_lock_irqsave(&port->lock, flags);
570
571 if (IS_SMC(pinfo)) {
572 unsigned int bits = tty_get_frame_size(termios->c_cflag);
573
574 /*
575 * MRBLR can be changed while an SMC/SCC is operating only
576 * if it is done in a single bus cycle with one 16-bit move
577 * (not two 8-bit bus cycles back-to-back). This occurs when
578 * the cp shifts control to the next RxBD, so the change does
579 * not take effect immediately. To guarantee the exact RxBD
580 * on which the change occurs, change MRBLR only while the
581 * SMC/SCC receiver is disabled.
582 */
583 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
584 out_be16(&pinfo->smcup->smc_maxidl, maxidl);
585
586 /* Set the mode register. We want to keep a copy of the
587 * enables, because we want to put them back if they were
588 * present.
589 */
590 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
591 /* Output in *one* operation, so we don't interrupt RX/TX if they
592 * were already enabled.
593 * Character length programmed into the register is frame bits minus 1.
594 */
595 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits - 1) | cval |
596 SMCMR_SM_UART | prev_mode);
597 } else {
598 unsigned int bits = tty_get_char_size(termios->c_cflag);
599
600 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
601 out_be16(&pinfo->sccup->scc_maxidl, maxidl);
602 out_be16(&sccp->scc_psmr, (UART_LCR_WLEN(bits) << 12) | scval);
603 }
604
605 if (pinfo->clk)
606 clk_set_rate(pinfo->clk, baud);
607 else
608 cpm_set_brg(pinfo->brg - 1, baud);
609 spin_unlock_irqrestore(&port->lock, flags);
610 }
611
cpm_uart_type(struct uart_port * port)612 static const char *cpm_uart_type(struct uart_port *port)
613 {
614 pr_debug("CPM uart[%d]:uart_type\n", port->line);
615
616 return port->type == PORT_CPM ? "CPM UART" : NULL;
617 }
618
619 /*
620 * verify the new serial_struct (for TIOCSSERIAL).
621 */
cpm_uart_verify_port(struct uart_port * port,struct serial_struct * ser)622 static int cpm_uart_verify_port(struct uart_port *port,
623 struct serial_struct *ser)
624 {
625 int ret = 0;
626
627 pr_debug("CPM uart[%d]:verify_port\n", port->line);
628
629 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
630 ret = -EINVAL;
631 if (ser->irq < 0 || ser->irq >= nr_irqs)
632 ret = -EINVAL;
633 if (ser->baud_base < 9600)
634 ret = -EINVAL;
635 return ret;
636 }
637
638 /*
639 * Transmit characters, refill buffer descriptor, if possible
640 */
cpm_uart_tx_pump(struct uart_port * port)641 static int cpm_uart_tx_pump(struct uart_port *port)
642 {
643 cbd_t __iomem *bdp;
644 u8 *p;
645 int count;
646 struct uart_cpm_port *pinfo =
647 container_of(port, struct uart_cpm_port, port);
648 struct circ_buf *xmit = &port->state->xmit;
649
650 /* Handle xon/xoff */
651 if (port->x_char) {
652 /* Pick next descriptor and fill from buffer */
653 bdp = pinfo->tx_cur;
654
655 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
656
657 *p++ = port->x_char;
658
659 out_be16(&bdp->cbd_datlen, 1);
660 setbits16(&bdp->cbd_sc, BD_SC_READY);
661 /* Get next BD. */
662 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
663 bdp = pinfo->tx_bd_base;
664 else
665 bdp++;
666 pinfo->tx_cur = bdp;
667
668 port->icount.tx++;
669 port->x_char = 0;
670 return 1;
671 }
672
673 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
674 cpm_uart_stop_tx(port);
675 return 0;
676 }
677
678 /* Pick next descriptor and fill from buffer */
679 bdp = pinfo->tx_cur;
680
681 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
682 xmit->tail != xmit->head) {
683 count = 0;
684 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
685 while (count < pinfo->tx_fifosize) {
686 *p++ = xmit->buf[xmit->tail];
687 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
688 port->icount.tx++;
689 count++;
690 if (xmit->head == xmit->tail)
691 break;
692 }
693 out_be16(&bdp->cbd_datlen, count);
694 setbits16(&bdp->cbd_sc, BD_SC_READY);
695 /* Get next BD. */
696 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
697 bdp = pinfo->tx_bd_base;
698 else
699 bdp++;
700 }
701 pinfo->tx_cur = bdp;
702
703 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
704 uart_write_wakeup(port);
705
706 if (uart_circ_empty(xmit)) {
707 cpm_uart_stop_tx(port);
708 return 0;
709 }
710
711 return 1;
712 }
713
714 /*
715 * init buffer descriptors
716 */
cpm_uart_initbd(struct uart_cpm_port * pinfo)717 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
718 {
719 int i;
720 u8 *mem_addr;
721 cbd_t __iomem *bdp;
722
723 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
724
725 /* Set the physical address of the host memory
726 * buffers in the buffer descriptors, and the
727 * virtual address for us to work with.
728 */
729 mem_addr = pinfo->mem_addr;
730 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
731 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
732 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
733 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
734 mem_addr += pinfo->rx_fifosize;
735 }
736
737 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
738 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
739
740 /* Set the physical address of the host memory
741 * buffers in the buffer descriptors, and the
742 * virtual address for us to work with.
743 */
744 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
745 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
746 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
747 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
748 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
749 mem_addr += pinfo->tx_fifosize;
750 }
751
752 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
753 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
754 }
755
cpm_uart_init_scc(struct uart_cpm_port * pinfo)756 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
757 {
758 scc_t __iomem *scp;
759 scc_uart_t __iomem *sup;
760
761 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
762
763 scp = pinfo->sccp;
764 sup = pinfo->sccup;
765
766 /* Store address */
767 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
768 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
769 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
770 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
771
772 /* Set up the uart parameters in the
773 * parameter ram.
774 */
775
776 cpm_set_scc_fcr(sup);
777
778 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
779 out_be16(&sup->scc_maxidl, 0x10);
780 out_be16(&sup->scc_brkcr, 1);
781 out_be16(&sup->scc_parec, 0);
782 out_be16(&sup->scc_frmec, 0);
783 out_be16(&sup->scc_nosec, 0);
784 out_be16(&sup->scc_brkec, 0);
785 out_be16(&sup->scc_uaddr1, 0);
786 out_be16(&sup->scc_uaddr2, 0);
787 out_be16(&sup->scc_toseq, 0);
788 out_be16(&sup->scc_char1, 0x8000);
789 out_be16(&sup->scc_char2, 0x8000);
790 out_be16(&sup->scc_char3, 0x8000);
791 out_be16(&sup->scc_char4, 0x8000);
792 out_be16(&sup->scc_char5, 0x8000);
793 out_be16(&sup->scc_char6, 0x8000);
794 out_be16(&sup->scc_char7, 0x8000);
795 out_be16(&sup->scc_char8, 0x8000);
796 out_be16(&sup->scc_rccm, 0xc0ff);
797
798 /* Send the CPM an initialize command.
799 */
800 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
801
802 /* Set UART mode, 8 bit, no parity, one stop.
803 * Enable receive and transmit.
804 */
805 out_be32(&scp->scc_gsmrh, 0);
806 out_be32(&scp->scc_gsmrl,
807 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
808
809 /* Enable rx interrupts and clear all pending events. */
810 out_be16(&scp->scc_sccm, 0);
811 out_be16(&scp->scc_scce, 0xffff);
812 out_be16(&scp->scc_dsr, 0x7e7e);
813 out_be16(&scp->scc_psmr, 0x3000);
814
815 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
816 }
817
cpm_uart_init_smc(struct uart_cpm_port * pinfo)818 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
819 {
820 smc_t __iomem *sp;
821 smc_uart_t __iomem *up;
822
823 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
824
825 sp = pinfo->smcp;
826 up = pinfo->smcup;
827
828 /* Store address */
829 out_be16(&pinfo->smcup->smc_rbase,
830 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
831 out_be16(&pinfo->smcup->smc_tbase,
832 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
833
834 /*
835 * In case SMC is being relocated...
836 */
837 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
838 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
839 out_be32(&up->smc_rstate, 0);
840 out_be32(&up->smc_tstate, 0);
841 out_be16(&up->smc_brkcr, 1); /* number of break chars */
842 out_be16(&up->smc_brkec, 0);
843
844 /* Set up the uart parameters in the
845 * parameter ram.
846 */
847 cpm_set_smc_fcr(up);
848
849 /* Using idle character time requires some additional tuning. */
850 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
851 out_be16(&up->smc_maxidl, 0x10);
852 out_be16(&up->smc_brklen, 0);
853 out_be16(&up->smc_brkec, 0);
854 out_be16(&up->smc_brkcr, 1);
855
856 /* Set UART mode, 8 bit, no parity, one stop.
857 * Enable receive and transmit.
858 */
859 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
860
861 /* Enable only rx interrupts clear all pending events. */
862 out_8(&sp->smc_smcm, 0);
863 out_8(&sp->smc_smce, 0xff);
864
865 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
866 }
867
868 /*
869 * Initialize port. This is called from early_console stuff
870 * so we have to be careful here !
871 */
cpm_uart_request_port(struct uart_port * port)872 static int cpm_uart_request_port(struct uart_port *port)
873 {
874 struct uart_cpm_port *pinfo =
875 container_of(port, struct uart_cpm_port, port);
876 int ret;
877
878 pr_debug("CPM uart[%d]:request port\n", port->line);
879
880 if (pinfo->flags & FLAG_CONSOLE)
881 return 0;
882
883 if (IS_SMC(pinfo)) {
884 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
885 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
886 } else {
887 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
888 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
889 }
890
891 ret = cpm_uart_allocbuf(pinfo, 0);
892
893 if (ret)
894 return ret;
895
896 cpm_uart_initbd(pinfo);
897 if (IS_SMC(pinfo))
898 cpm_uart_init_smc(pinfo);
899 else
900 cpm_uart_init_scc(pinfo);
901
902 return 0;
903 }
904
cpm_uart_release_port(struct uart_port * port)905 static void cpm_uart_release_port(struct uart_port *port)
906 {
907 struct uart_cpm_port *pinfo =
908 container_of(port, struct uart_cpm_port, port);
909
910 if (!(pinfo->flags & FLAG_CONSOLE))
911 cpm_uart_freebuf(pinfo);
912 }
913
914 /*
915 * Configure/autoconfigure the port.
916 */
cpm_uart_config_port(struct uart_port * port,int flags)917 static void cpm_uart_config_port(struct uart_port *port, int flags)
918 {
919 pr_debug("CPM uart[%d]:config_port\n", port->line);
920
921 if (flags & UART_CONFIG_TYPE) {
922 port->type = PORT_CPM;
923 cpm_uart_request_port(port);
924 }
925 }
926
927 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
928 /*
929 * Write a string to the serial port
930 * Note that this is called with interrupts already disabled
931 */
cpm_uart_early_write(struct uart_cpm_port * pinfo,const char * string,u_int count,bool handle_linefeed)932 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
933 const char *string, u_int count, bool handle_linefeed)
934 {
935 unsigned int i;
936 cbd_t __iomem *bdp, *bdbase;
937 unsigned char *cpm_outp_addr;
938
939 /* Get the address of the host memory buffer.
940 */
941 bdp = pinfo->tx_cur;
942 bdbase = pinfo->tx_bd_base;
943
944 /*
945 * Now, do each character. This is not as bad as it looks
946 * since this is a holding FIFO and not a transmitting FIFO.
947 * We could add the complexity of filling the entire transmit
948 * buffer, but we would just wait longer between accesses......
949 */
950 for (i = 0; i < count; i++, string++) {
951 /* Wait for transmitter fifo to empty.
952 * Ready indicates output is ready, and xmt is doing
953 * that, not that it is ready for us to send.
954 */
955 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
956 ;
957
958 /* Send the character out.
959 * If the buffer address is in the CPM DPRAM, don't
960 * convert it.
961 */
962 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
963 pinfo);
964 *cpm_outp_addr = *string;
965
966 out_be16(&bdp->cbd_datlen, 1);
967 setbits16(&bdp->cbd_sc, BD_SC_READY);
968
969 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
970 bdp = bdbase;
971 else
972 bdp++;
973
974 /* if a LF, also do CR... */
975 if (handle_linefeed && *string == 10) {
976 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
977 ;
978
979 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
980 pinfo);
981 *cpm_outp_addr = 13;
982
983 out_be16(&bdp->cbd_datlen, 1);
984 setbits16(&bdp->cbd_sc, BD_SC_READY);
985
986 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
987 bdp = bdbase;
988 else
989 bdp++;
990 }
991 }
992
993 /*
994 * Finally, Wait for transmitter & holding register to empty
995 * and restore the IER
996 */
997 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
998 ;
999
1000 pinfo->tx_cur = bdp;
1001 }
1002 #endif
1003
1004 #ifdef CONFIG_CONSOLE_POLL
1005 /* Serial polling routines for writing and reading from the uart while
1006 * in an interrupt or debug context.
1007 */
1008
1009 #define GDB_BUF_SIZE 512 /* power of 2, please */
1010
1011 static char poll_buf[GDB_BUF_SIZE];
1012 static char *pollp;
1013 static int poll_chars;
1014
poll_wait_key(char * obuf,struct uart_cpm_port * pinfo)1015 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1016 {
1017 u_char c, *cp;
1018 volatile cbd_t *bdp;
1019 int i;
1020
1021 /* Get the address of the host memory buffer.
1022 */
1023 bdp = pinfo->rx_cur;
1024 if (bdp->cbd_sc & BD_SC_EMPTY)
1025 return NO_POLL_CHAR;
1026
1027 /* If the buffer address is in the CPM DPRAM, don't
1028 * convert it.
1029 */
1030 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1031
1032 if (obuf) {
1033 i = c = bdp->cbd_datlen;
1034 while (i-- > 0)
1035 *obuf++ = *cp++;
1036 } else
1037 c = *cp;
1038 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1039 bdp->cbd_sc |= BD_SC_EMPTY;
1040
1041 if (bdp->cbd_sc & BD_SC_WRAP)
1042 bdp = pinfo->rx_bd_base;
1043 else
1044 bdp++;
1045 pinfo->rx_cur = (cbd_t *)bdp;
1046
1047 return (int)c;
1048 }
1049
cpm_get_poll_char(struct uart_port * port)1050 static int cpm_get_poll_char(struct uart_port *port)
1051 {
1052 struct uart_cpm_port *pinfo =
1053 container_of(port, struct uart_cpm_port, port);
1054
1055 if (!serial_polled) {
1056 serial_polled = 1;
1057 poll_chars = 0;
1058 }
1059 if (poll_chars <= 0) {
1060 int ret = poll_wait_key(poll_buf, pinfo);
1061
1062 if (ret == NO_POLL_CHAR)
1063 return ret;
1064 poll_chars = ret;
1065 pollp = poll_buf;
1066 }
1067 poll_chars--;
1068 return *pollp++;
1069 }
1070
cpm_put_poll_char(struct uart_port * port,unsigned char c)1071 static void cpm_put_poll_char(struct uart_port *port,
1072 unsigned char c)
1073 {
1074 struct uart_cpm_port *pinfo =
1075 container_of(port, struct uart_cpm_port, port);
1076 static char ch[2];
1077
1078 ch[0] = (char)c;
1079 cpm_uart_early_write(pinfo, ch, 1, false);
1080 }
1081
1082 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1083 static struct uart_port *udbg_port;
1084
udbg_cpm_putc(char c)1085 static void udbg_cpm_putc(char c)
1086 {
1087 if (c == '\n')
1088 cpm_put_poll_char(udbg_port, '\r');
1089 cpm_put_poll_char(udbg_port, c);
1090 }
1091
udbg_cpm_getc_poll(void)1092 static int udbg_cpm_getc_poll(void)
1093 {
1094 int c = cpm_get_poll_char(udbg_port);
1095
1096 return c == NO_POLL_CHAR ? -1 : c;
1097 }
1098
udbg_cpm_getc(void)1099 static int udbg_cpm_getc(void)
1100 {
1101 int c;
1102
1103 while ((c = udbg_cpm_getc_poll()) == -1)
1104 cpu_relax();
1105 return c;
1106 }
1107 #endif /* CONFIG_SERIAL_CPM_CONSOLE */
1108
1109 #endif /* CONFIG_CONSOLE_POLL */
1110
1111 static const struct uart_ops cpm_uart_pops = {
1112 .tx_empty = cpm_uart_tx_empty,
1113 .set_mctrl = cpm_uart_set_mctrl,
1114 .get_mctrl = cpm_uart_get_mctrl,
1115 .stop_tx = cpm_uart_stop_tx,
1116 .start_tx = cpm_uart_start_tx,
1117 .stop_rx = cpm_uart_stop_rx,
1118 .break_ctl = cpm_uart_break_ctl,
1119 .startup = cpm_uart_startup,
1120 .shutdown = cpm_uart_shutdown,
1121 .set_termios = cpm_uart_set_termios,
1122 .type = cpm_uart_type,
1123 .release_port = cpm_uart_release_port,
1124 .request_port = cpm_uart_request_port,
1125 .config_port = cpm_uart_config_port,
1126 .verify_port = cpm_uart_verify_port,
1127 #ifdef CONFIG_CONSOLE_POLL
1128 .poll_get_char = cpm_get_poll_char,
1129 .poll_put_char = cpm_put_poll_char,
1130 #endif
1131 };
1132
1133 struct uart_cpm_port cpm_uart_ports[UART_NR];
1134
cpm_uart_init_port(struct device_node * np,struct uart_cpm_port * pinfo)1135 static int cpm_uart_init_port(struct device_node *np,
1136 struct uart_cpm_port *pinfo)
1137 {
1138 const u32 *data;
1139 void __iomem *mem, *pram;
1140 struct device *dev = pinfo->port.dev;
1141 int len;
1142 int ret;
1143 int i;
1144
1145 data = of_get_property(np, "clock", NULL);
1146 if (data) {
1147 struct clk *clk = clk_get(NULL, (const char*)data);
1148 if (!IS_ERR(clk))
1149 pinfo->clk = clk;
1150 }
1151 if (!pinfo->clk) {
1152 data = of_get_property(np, "fsl,cpm-brg", &len);
1153 if (!data || len != 4) {
1154 printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1155 "fsl,cpm-brg property.\n", np);
1156 return -EINVAL;
1157 }
1158 pinfo->brg = *data;
1159 }
1160
1161 data = of_get_property(np, "fsl,cpm-command", &len);
1162 if (!data || len != 4) {
1163 printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1164 "fsl,cpm-command property.\n", np);
1165 return -EINVAL;
1166 }
1167 pinfo->command = *data;
1168
1169 mem = of_iomap(np, 0);
1170 if (!mem)
1171 return -ENOMEM;
1172
1173 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1174 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1175 pinfo->sccp = mem;
1176 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1177 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1178 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1179 pinfo->flags |= FLAG_SMC;
1180 pinfo->smcp = mem;
1181 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1182 } else {
1183 ret = -ENODEV;
1184 goto out_mem;
1185 }
1186
1187 if (!pram) {
1188 ret = -ENOMEM;
1189 goto out_mem;
1190 }
1191
1192 pinfo->tx_nrfifos = TX_NUM_FIFO;
1193 pinfo->tx_fifosize = TX_BUF_SIZE;
1194 pinfo->rx_nrfifos = RX_NUM_FIFO;
1195 pinfo->rx_fifosize = RX_BUF_SIZE;
1196
1197 pinfo->port.uartclk = ppc_proc_freq;
1198 pinfo->port.mapbase = (unsigned long)mem;
1199 pinfo->port.type = PORT_CPM;
1200 pinfo->port.ops = &cpm_uart_pops;
1201 pinfo->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CPM_CONSOLE);
1202 pinfo->port.iotype = UPIO_MEM;
1203 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1204 spin_lock_init(&pinfo->port.lock);
1205
1206 for (i = 0; i < NUM_GPIOS; i++) {
1207 struct gpio_desc *gpiod;
1208
1209 pinfo->gpios[i] = NULL;
1210
1211 gpiod = devm_gpiod_get_index_optional(dev, NULL, i, GPIOD_ASIS);
1212
1213 if (IS_ERR(gpiod)) {
1214 ret = PTR_ERR(gpiod);
1215 goto out_pram;
1216 }
1217
1218 if (gpiod) {
1219 if (i == GPIO_RTS || i == GPIO_DTR)
1220 ret = gpiod_direction_output(gpiod, 0);
1221 else
1222 ret = gpiod_direction_input(gpiod);
1223 if (ret) {
1224 pr_err("can't set direction for gpio #%d: %d\n",
1225 i, ret);
1226 continue;
1227 }
1228 pinfo->gpios[i] = gpiod;
1229 }
1230 }
1231
1232 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1233 #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_CPM_CONSOLE)
1234 if (!udbg_port)
1235 #endif
1236 udbg_putc = NULL;
1237 #endif
1238
1239 return cpm_uart_request_port(&pinfo->port);
1240
1241 out_pram:
1242 cpm_uart_unmap_pram(pinfo, pram);
1243 out_mem:
1244 iounmap(mem);
1245 return ret;
1246 }
1247
1248 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1249 /*
1250 * Print a string to the serial port trying not to disturb
1251 * any possible real use of the port...
1252 *
1253 * Note that this is called with interrupts already disabled
1254 */
cpm_uart_console_write(struct console * co,const char * s,u_int count)1255 static void cpm_uart_console_write(struct console *co, const char *s,
1256 u_int count)
1257 {
1258 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1259 unsigned long flags;
1260
1261 if (unlikely(oops_in_progress)) {
1262 local_irq_save(flags);
1263 cpm_uart_early_write(pinfo, s, count, true);
1264 local_irq_restore(flags);
1265 } else {
1266 spin_lock_irqsave(&pinfo->port.lock, flags);
1267 cpm_uart_early_write(pinfo, s, count, true);
1268 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1269 }
1270 }
1271
1272
cpm_uart_console_setup(struct console * co,char * options)1273 static int __init cpm_uart_console_setup(struct console *co, char *options)
1274 {
1275 int baud = 38400;
1276 int bits = 8;
1277 int parity = 'n';
1278 int flow = 'n';
1279 int ret;
1280 struct uart_cpm_port *pinfo;
1281 struct uart_port *port;
1282
1283 struct device_node *np;
1284 int i = 0;
1285
1286 if (co->index >= UART_NR) {
1287 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1288 co->index);
1289 return -ENODEV;
1290 }
1291
1292 for_each_node_by_type(np, "serial") {
1293 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1294 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1295 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1296 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1297 continue;
1298
1299 if (i++ == co->index)
1300 break;
1301 }
1302
1303 if (!np)
1304 return -ENODEV;
1305
1306 pinfo = &cpm_uart_ports[co->index];
1307
1308 pinfo->flags |= FLAG_CONSOLE;
1309 port = &pinfo->port;
1310
1311 ret = cpm_uart_init_port(np, pinfo);
1312 of_node_put(np);
1313 if (ret)
1314 return ret;
1315
1316 if (options) {
1317 uart_parse_options(options, &baud, &parity, &bits, &flow);
1318 } else {
1319 if ((baud = uart_baudrate()) == -1)
1320 baud = 9600;
1321 }
1322
1323 if (IS_SMC(pinfo)) {
1324 out_be16(&pinfo->smcup->smc_brkcr, 0);
1325 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1326 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1327 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1328 } else {
1329 out_be16(&pinfo->sccup->scc_brkcr, 0);
1330 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1331 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1332 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1333 }
1334
1335 ret = cpm_uart_allocbuf(pinfo, 1);
1336
1337 if (ret)
1338 return ret;
1339
1340 cpm_uart_initbd(pinfo);
1341
1342 if (IS_SMC(pinfo))
1343 cpm_uart_init_smc(pinfo);
1344 else
1345 cpm_uart_init_scc(pinfo);
1346
1347 uart_set_options(port, co, baud, parity, bits, flow);
1348 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1349
1350 #ifdef CONFIG_CONSOLE_POLL
1351 if (!udbg_port) {
1352 udbg_port = &pinfo->port;
1353 udbg_putc = udbg_cpm_putc;
1354 udbg_getc = udbg_cpm_getc;
1355 udbg_getc_poll = udbg_cpm_getc_poll;
1356 }
1357 #endif
1358
1359 return 0;
1360 }
1361
1362 static struct uart_driver cpm_reg;
1363 static struct console cpm_scc_uart_console = {
1364 .name = "ttyCPM",
1365 .write = cpm_uart_console_write,
1366 .device = uart_console_device,
1367 .setup = cpm_uart_console_setup,
1368 .flags = CON_PRINTBUFFER,
1369 .index = -1,
1370 .data = &cpm_reg,
1371 };
1372
cpm_uart_console_init(void)1373 static int __init cpm_uart_console_init(void)
1374 {
1375 cpm_muram_init();
1376 register_console(&cpm_scc_uart_console);
1377 return 0;
1378 }
1379
1380 console_initcall(cpm_uart_console_init);
1381
1382 #define CPM_UART_CONSOLE &cpm_scc_uart_console
1383 #else
1384 #define CPM_UART_CONSOLE NULL
1385 #endif
1386
1387 static struct uart_driver cpm_reg = {
1388 .owner = THIS_MODULE,
1389 .driver_name = "ttyCPM",
1390 .dev_name = "ttyCPM",
1391 .major = SERIAL_CPM_MAJOR,
1392 .minor = SERIAL_CPM_MINOR,
1393 .cons = CPM_UART_CONSOLE,
1394 .nr = UART_NR,
1395 };
1396
1397 static int probe_index;
1398
cpm_uart_probe(struct platform_device * ofdev)1399 static int cpm_uart_probe(struct platform_device *ofdev)
1400 {
1401 int index = probe_index++;
1402 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1403 int ret;
1404
1405 pinfo->port.line = index;
1406
1407 if (index >= UART_NR)
1408 return -ENODEV;
1409
1410 platform_set_drvdata(ofdev, pinfo);
1411
1412 /* initialize the device pointer for the port */
1413 pinfo->port.dev = &ofdev->dev;
1414
1415 pinfo->port.irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1416 if (!pinfo->port.irq)
1417 return -EINVAL;
1418
1419 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1420 if (!ret)
1421 return uart_add_one_port(&cpm_reg, &pinfo->port);
1422
1423 irq_dispose_mapping(pinfo->port.irq);
1424
1425 return ret;
1426 }
1427
cpm_uart_remove(struct platform_device * ofdev)1428 static int cpm_uart_remove(struct platform_device *ofdev)
1429 {
1430 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
1431 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1432 }
1433
1434 static const struct of_device_id cpm_uart_match[] = {
1435 {
1436 .compatible = "fsl,cpm1-smc-uart",
1437 },
1438 {
1439 .compatible = "fsl,cpm1-scc-uart",
1440 },
1441 {
1442 .compatible = "fsl,cpm2-smc-uart",
1443 },
1444 {
1445 .compatible = "fsl,cpm2-scc-uart",
1446 },
1447 {}
1448 };
1449 MODULE_DEVICE_TABLE(of, cpm_uart_match);
1450
1451 static struct platform_driver cpm_uart_driver = {
1452 .driver = {
1453 .name = "cpm_uart",
1454 .of_match_table = cpm_uart_match,
1455 },
1456 .probe = cpm_uart_probe,
1457 .remove = cpm_uart_remove,
1458 };
1459
cpm_uart_init(void)1460 static int __init cpm_uart_init(void)
1461 {
1462 int ret = uart_register_driver(&cpm_reg);
1463 if (ret)
1464 return ret;
1465
1466 ret = platform_driver_register(&cpm_uart_driver);
1467 if (ret)
1468 uart_unregister_driver(&cpm_reg);
1469
1470 return ret;
1471 }
1472
cpm_uart_exit(void)1473 static void __exit cpm_uart_exit(void)
1474 {
1475 platform_driver_unregister(&cpm_uart_driver);
1476 uart_unregister_driver(&cpm_reg);
1477 }
1478
1479 module_init(cpm_uart_init);
1480 module_exit(cpm_uart_exit);
1481
1482 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1483 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1484 MODULE_LICENSE("GPL");
1485 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
1486