1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
4 *
5 * Copyright (C) 2004 Infineon IFAP DC COM CPE
6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
7 * Copyright (C) 2007 John Crispin <john@phrozen.org>
8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/device.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/lantiq.h>
19 #include <linux/module.h>
20 #include <linux/of_platform.h>
21 #include <linux/serial.h>
22 #include <linux/serial_core.h>
23 #include <linux/slab.h>
24 #include <linux/sysrq.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27
28 #define PORT_LTQ_ASC 111
29 #define MAXPORTS 2
30 #define UART_DUMMY_UER_RX 1
31 #define DRVNAME "lantiq,asc"
32 #ifdef __BIG_ENDIAN
33 #define LTQ_ASC_TBUF (0x0020 + 3)
34 #define LTQ_ASC_RBUF (0x0024 + 3)
35 #else
36 #define LTQ_ASC_TBUF 0x0020
37 #define LTQ_ASC_RBUF 0x0024
38 #endif
39 #define LTQ_ASC_FSTAT 0x0048
40 #define LTQ_ASC_WHBSTATE 0x0018
41 #define LTQ_ASC_STATE 0x0014
42 #define LTQ_ASC_IRNCR 0x00F8
43 #define LTQ_ASC_CLC 0x0000
44 #define LTQ_ASC_ID 0x0008
45 #define LTQ_ASC_PISEL 0x0004
46 #define LTQ_ASC_TXFCON 0x0044
47 #define LTQ_ASC_RXFCON 0x0040
48 #define LTQ_ASC_CON 0x0010
49 #define LTQ_ASC_BG 0x0050
50 #define LTQ_ASC_IRNREN 0x00F4
51
52 #define ASC_IRNREN_TX 0x1
53 #define ASC_IRNREN_RX 0x2
54 #define ASC_IRNREN_ERR 0x4
55 #define ASC_IRNREN_TX_BUF 0x8
56 #define ASC_IRNCR_TIR 0x1
57 #define ASC_IRNCR_RIR 0x2
58 #define ASC_IRNCR_EIR 0x4
59 #define ASC_IRNCR_MASK GENMASK(2, 0)
60
61 #define ASCOPT_CSIZE 0x3
62 #define TXFIFO_FL 1
63 #define RXFIFO_FL 1
64 #define ASCCLC_DISS 0x2
65 #define ASCCLC_RMCMASK 0x0000FF00
66 #define ASCCLC_RMCOFFSET 8
67 #define ASCCON_M_8ASYNC 0x0
68 #define ASCCON_M_7ASYNC 0x2
69 #define ASCCON_ODD 0x00000020
70 #define ASCCON_STP 0x00000080
71 #define ASCCON_BRS 0x00000100
72 #define ASCCON_FDE 0x00000200
73 #define ASCCON_R 0x00008000
74 #define ASCCON_FEN 0x00020000
75 #define ASCCON_ROEN 0x00080000
76 #define ASCCON_TOEN 0x00100000
77 #define ASCSTATE_PE 0x00010000
78 #define ASCSTATE_FE 0x00020000
79 #define ASCSTATE_ROE 0x00080000
80 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
81 #define ASCWHBSTATE_CLRREN 0x00000001
82 #define ASCWHBSTATE_SETREN 0x00000002
83 #define ASCWHBSTATE_CLRPE 0x00000004
84 #define ASCWHBSTATE_CLRFE 0x00000008
85 #define ASCWHBSTATE_CLRROE 0x00000020
86 #define ASCTXFCON_TXFEN 0x0001
87 #define ASCTXFCON_TXFFLU 0x0002
88 #define ASCTXFCON_TXFITLMASK 0x3F00
89 #define ASCTXFCON_TXFITLOFF 8
90 #define ASCRXFCON_RXFEN 0x0001
91 #define ASCRXFCON_RXFFLU 0x0002
92 #define ASCRXFCON_RXFITLMASK 0x3F00
93 #define ASCRXFCON_RXFITLOFF 8
94 #define ASCFSTAT_RXFFLMASK 0x003F
95 #define ASCFSTAT_TXFFLMASK 0x3F00
96 #define ASCFSTAT_TXFREEMASK 0x3F000000
97
98 static void lqasc_tx_chars(struct uart_port *port);
99 static struct ltq_uart_port *lqasc_port[MAXPORTS];
100 static struct uart_driver lqasc_reg;
101
102 struct ltq_soc_data {
103 int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port);
104 int (*request_irq)(struct uart_port *port);
105 void (*free_irq)(struct uart_port *port);
106 };
107
108 struct ltq_uart_port {
109 struct uart_port port;
110 /* clock used to derive divider */
111 struct clk *freqclk;
112 /* clock gating of the ASC core */
113 struct clk *clk;
114 unsigned int tx_irq;
115 unsigned int rx_irq;
116 unsigned int err_irq;
117 unsigned int common_irq;
118 spinlock_t lock; /* exclusive access for multi core */
119
120 const struct ltq_soc_data *soc;
121 };
122
asc_update_bits(u32 clear,u32 set,void __iomem * reg)123 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
124 {
125 u32 tmp = __raw_readl(reg);
126
127 __raw_writel((tmp & ~clear) | set, reg);
128 }
129
130 static inline struct
to_ltq_uart_port(struct uart_port * port)131 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
132 {
133 return container_of(port, struct ltq_uart_port, port);
134 }
135
136 static void
lqasc_stop_tx(struct uart_port * port)137 lqasc_stop_tx(struct uart_port *port)
138 {
139 return;
140 }
141
lqasc_tx_ready(struct uart_port * port)142 static bool lqasc_tx_ready(struct uart_port *port)
143 {
144 u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT);
145
146 return FIELD_GET(ASCFSTAT_TXFREEMASK, fstat);
147 }
148
149 static void
lqasc_start_tx(struct uart_port * port)150 lqasc_start_tx(struct uart_port *port)
151 {
152 unsigned long flags;
153 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
154
155 spin_lock_irqsave(<q_port->lock, flags);
156 lqasc_tx_chars(port);
157 spin_unlock_irqrestore(<q_port->lock, flags);
158 return;
159 }
160
161 static void
lqasc_stop_rx(struct uart_port * port)162 lqasc_stop_rx(struct uart_port *port)
163 {
164 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
165 }
166
167 static int
lqasc_rx_chars(struct uart_port * port)168 lqasc_rx_chars(struct uart_port *port)
169 {
170 struct tty_port *tport = &port->state->port;
171 unsigned int ch = 0, rsr = 0, fifocnt;
172
173 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
174 ASCFSTAT_RXFFLMASK;
175 while (fifocnt--) {
176 u8 flag = TTY_NORMAL;
177 ch = readb(port->membase + LTQ_ASC_RBUF);
178 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
179 & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
180 tty_flip_buffer_push(tport);
181 port->icount.rx++;
182
183 /*
184 * Note that the error handling code is
185 * out of the main execution path
186 */
187 if (rsr & ASCSTATE_ANY) {
188 if (rsr & ASCSTATE_PE) {
189 port->icount.parity++;
190 asc_update_bits(0, ASCWHBSTATE_CLRPE,
191 port->membase + LTQ_ASC_WHBSTATE);
192 } else if (rsr & ASCSTATE_FE) {
193 port->icount.frame++;
194 asc_update_bits(0, ASCWHBSTATE_CLRFE,
195 port->membase + LTQ_ASC_WHBSTATE);
196 }
197 if (rsr & ASCSTATE_ROE) {
198 port->icount.overrun++;
199 asc_update_bits(0, ASCWHBSTATE_CLRROE,
200 port->membase + LTQ_ASC_WHBSTATE);
201 }
202
203 rsr &= port->read_status_mask;
204
205 if (rsr & ASCSTATE_PE)
206 flag = TTY_PARITY;
207 else if (rsr & ASCSTATE_FE)
208 flag = TTY_FRAME;
209 }
210
211 if ((rsr & port->ignore_status_mask) == 0)
212 tty_insert_flip_char(tport, ch, flag);
213
214 if (rsr & ASCSTATE_ROE)
215 /*
216 * Overrun is special, since it's reported
217 * immediately, and doesn't affect the current
218 * character
219 */
220 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
221 }
222
223 if (ch != 0)
224 tty_flip_buffer_push(tport);
225
226 return 0;
227 }
228
229 static void
lqasc_tx_chars(struct uart_port * port)230 lqasc_tx_chars(struct uart_port *port)
231 {
232 struct circ_buf *xmit = &port->state->xmit;
233 if (uart_tx_stopped(port)) {
234 lqasc_stop_tx(port);
235 return;
236 }
237
238 while (lqasc_tx_ready(port)) {
239 if (port->x_char) {
240 writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
241 port->icount.tx++;
242 port->x_char = 0;
243 continue;
244 }
245
246 if (uart_circ_empty(xmit))
247 break;
248
249 writeb(port->state->xmit.buf[port->state->xmit.tail],
250 port->membase + LTQ_ASC_TBUF);
251 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
252 port->icount.tx++;
253 }
254
255 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
256 uart_write_wakeup(port);
257 }
258
259 static irqreturn_t
lqasc_tx_int(int irq,void * _port)260 lqasc_tx_int(int irq, void *_port)
261 {
262 unsigned long flags;
263 struct uart_port *port = (struct uart_port *)_port;
264 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
265
266 spin_lock_irqsave(<q_port->lock, flags);
267 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
268 spin_unlock_irqrestore(<q_port->lock, flags);
269 lqasc_start_tx(port);
270 return IRQ_HANDLED;
271 }
272
273 static irqreturn_t
lqasc_err_int(int irq,void * _port)274 lqasc_err_int(int irq, void *_port)
275 {
276 unsigned long flags;
277 struct uart_port *port = (struct uart_port *)_port;
278 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
279
280 spin_lock_irqsave(<q_port->lock, flags);
281 __raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR);
282 /* clear any pending interrupts */
283 asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
284 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
285 spin_unlock_irqrestore(<q_port->lock, flags);
286 return IRQ_HANDLED;
287 }
288
289 static irqreturn_t
lqasc_rx_int(int irq,void * _port)290 lqasc_rx_int(int irq, void *_port)
291 {
292 unsigned long flags;
293 struct uart_port *port = (struct uart_port *)_port;
294 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
295
296 spin_lock_irqsave(<q_port->lock, flags);
297 __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
298 lqasc_rx_chars(port);
299 spin_unlock_irqrestore(<q_port->lock, flags);
300 return IRQ_HANDLED;
301 }
302
lqasc_irq(int irq,void * p)303 static irqreturn_t lqasc_irq(int irq, void *p)
304 {
305 unsigned long flags;
306 u32 stat;
307 struct uart_port *port = p;
308 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
309
310 spin_lock_irqsave(<q_port->lock, flags);
311 stat = readl(port->membase + LTQ_ASC_IRNCR);
312 spin_unlock_irqrestore(<q_port->lock, flags);
313 if (!(stat & ASC_IRNCR_MASK))
314 return IRQ_NONE;
315
316 if (stat & ASC_IRNCR_TIR)
317 lqasc_tx_int(irq, p);
318
319 if (stat & ASC_IRNCR_RIR)
320 lqasc_rx_int(irq, p);
321
322 if (stat & ASC_IRNCR_EIR)
323 lqasc_err_int(irq, p);
324
325 return IRQ_HANDLED;
326 }
327
328 static unsigned int
lqasc_tx_empty(struct uart_port * port)329 lqasc_tx_empty(struct uart_port *port)
330 {
331 int status;
332 status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
333 ASCFSTAT_TXFFLMASK;
334 return status ? 0 : TIOCSER_TEMT;
335 }
336
337 static unsigned int
lqasc_get_mctrl(struct uart_port * port)338 lqasc_get_mctrl(struct uart_port *port)
339 {
340 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
341 }
342
343 static void
lqasc_set_mctrl(struct uart_port * port,u_int mctrl)344 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
345 {
346 }
347
348 static void
lqasc_break_ctl(struct uart_port * port,int break_state)349 lqasc_break_ctl(struct uart_port *port, int break_state)
350 {
351 }
352
353 static int
lqasc_startup(struct uart_port * port)354 lqasc_startup(struct uart_port *port)
355 {
356 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
357 int retval;
358 unsigned long flags;
359
360 if (!IS_ERR(ltq_port->clk))
361 clk_prepare_enable(ltq_port->clk);
362 port->uartclk = clk_get_rate(ltq_port->freqclk);
363
364 spin_lock_irqsave(<q_port->lock, flags);
365 asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
366 port->membase + LTQ_ASC_CLC);
367
368 __raw_writel(0, port->membase + LTQ_ASC_PISEL);
369 __raw_writel(
370 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
371 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
372 port->membase + LTQ_ASC_TXFCON);
373 __raw_writel(
374 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
375 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
376 port->membase + LTQ_ASC_RXFCON);
377 /* make sure other settings are written to hardware before
378 * setting enable bits
379 */
380 wmb();
381 asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
382 ASCCON_ROEN, port->membase + LTQ_ASC_CON);
383
384 spin_unlock_irqrestore(<q_port->lock, flags);
385
386 retval = ltq_port->soc->request_irq(port);
387 if (retval)
388 return retval;
389
390 __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
391 port->membase + LTQ_ASC_IRNREN);
392 return retval;
393 }
394
395 static void
lqasc_shutdown(struct uart_port * port)396 lqasc_shutdown(struct uart_port *port)
397 {
398 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
399 unsigned long flags;
400
401 ltq_port->soc->free_irq(port);
402
403 spin_lock_irqsave(<q_port->lock, flags);
404 __raw_writel(0, port->membase + LTQ_ASC_CON);
405 asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
406 port->membase + LTQ_ASC_RXFCON);
407 asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
408 port->membase + LTQ_ASC_TXFCON);
409 spin_unlock_irqrestore(<q_port->lock, flags);
410 if (!IS_ERR(ltq_port->clk))
411 clk_disable_unprepare(ltq_port->clk);
412 }
413
414 static void
lqasc_set_termios(struct uart_port * port,struct ktermios * new,const struct ktermios * old)415 lqasc_set_termios(struct uart_port *port, struct ktermios *new,
416 const struct ktermios *old)
417 {
418 unsigned int cflag;
419 unsigned int iflag;
420 unsigned int divisor;
421 unsigned int baud;
422 unsigned int con = 0;
423 unsigned long flags;
424 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
425
426 cflag = new->c_cflag;
427 iflag = new->c_iflag;
428
429 switch (cflag & CSIZE) {
430 case CS7:
431 con = ASCCON_M_7ASYNC;
432 break;
433
434 case CS5:
435 case CS6:
436 default:
437 new->c_cflag &= ~ CSIZE;
438 new->c_cflag |= CS8;
439 con = ASCCON_M_8ASYNC;
440 break;
441 }
442
443 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
444
445 if (cflag & CSTOPB)
446 con |= ASCCON_STP;
447
448 if (cflag & PARENB) {
449 if (!(cflag & PARODD))
450 con &= ~ASCCON_ODD;
451 else
452 con |= ASCCON_ODD;
453 }
454
455 port->read_status_mask = ASCSTATE_ROE;
456 if (iflag & INPCK)
457 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
458
459 port->ignore_status_mask = 0;
460 if (iflag & IGNPAR)
461 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
462
463 if (iflag & IGNBRK) {
464 /*
465 * If we're ignoring parity and break indicators,
466 * ignore overruns too (for real raw support).
467 */
468 if (iflag & IGNPAR)
469 port->ignore_status_mask |= ASCSTATE_ROE;
470 }
471
472 if ((cflag & CREAD) == 0)
473 port->ignore_status_mask |= UART_DUMMY_UER_RX;
474
475 /* set error signals - framing, parity and overrun, enable receiver */
476 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
477
478 spin_lock_irqsave(<q_port->lock, flags);
479
480 /* set up CON */
481 asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
482
483 /* Set baud rate - take a divider of 2 into account */
484 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
485 divisor = uart_get_divisor(port, baud);
486 divisor = divisor / 2 - 1;
487
488 /* disable the baudrate generator */
489 asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
490
491 /* make sure the fractional divider is off */
492 asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
493
494 /* set up to use divisor of 2 */
495 asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
496
497 /* now we can write the new baudrate into the register */
498 __raw_writel(divisor, port->membase + LTQ_ASC_BG);
499
500 /* turn the baudrate generator back on */
501 asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
502
503 /* enable rx */
504 __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
505
506 spin_unlock_irqrestore(<q_port->lock, flags);
507
508 /* Don't rewrite B0 */
509 if (tty_termios_baud_rate(new))
510 tty_termios_encode_baud_rate(new, baud, baud);
511
512 uart_update_timeout(port, cflag, baud);
513 }
514
515 static const char*
lqasc_type(struct uart_port * port)516 lqasc_type(struct uart_port *port)
517 {
518 if (port->type == PORT_LTQ_ASC)
519 return DRVNAME;
520 else
521 return NULL;
522 }
523
524 static void
lqasc_release_port(struct uart_port * port)525 lqasc_release_port(struct uart_port *port)
526 {
527 struct platform_device *pdev = to_platform_device(port->dev);
528
529 if (port->flags & UPF_IOREMAP) {
530 devm_iounmap(&pdev->dev, port->membase);
531 port->membase = NULL;
532 }
533 }
534
535 static int
lqasc_request_port(struct uart_port * port)536 lqasc_request_port(struct uart_port *port)
537 {
538 struct platform_device *pdev = to_platform_device(port->dev);
539 struct resource *res;
540 int size;
541
542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 if (!res) {
544 dev_err(&pdev->dev, "cannot obtain I/O memory region");
545 return -ENODEV;
546 }
547 size = resource_size(res);
548
549 res = devm_request_mem_region(&pdev->dev, res->start,
550 size, dev_name(&pdev->dev));
551 if (!res) {
552 dev_err(&pdev->dev, "cannot request I/O memory region");
553 return -EBUSY;
554 }
555
556 if (port->flags & UPF_IOREMAP) {
557 port->membase = devm_ioremap(&pdev->dev,
558 port->mapbase, size);
559 if (port->membase == NULL)
560 return -ENOMEM;
561 }
562 return 0;
563 }
564
565 static void
lqasc_config_port(struct uart_port * port,int flags)566 lqasc_config_port(struct uart_port *port, int flags)
567 {
568 if (flags & UART_CONFIG_TYPE) {
569 port->type = PORT_LTQ_ASC;
570 lqasc_request_port(port);
571 }
572 }
573
574 static int
lqasc_verify_port(struct uart_port * port,struct serial_struct * ser)575 lqasc_verify_port(struct uart_port *port,
576 struct serial_struct *ser)
577 {
578 int ret = 0;
579 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
580 ret = -EINVAL;
581 if (ser->irq < 0 || ser->irq >= NR_IRQS)
582 ret = -EINVAL;
583 if (ser->baud_base < 9600)
584 ret = -EINVAL;
585 return ret;
586 }
587
588 static const struct uart_ops lqasc_pops = {
589 .tx_empty = lqasc_tx_empty,
590 .set_mctrl = lqasc_set_mctrl,
591 .get_mctrl = lqasc_get_mctrl,
592 .stop_tx = lqasc_stop_tx,
593 .start_tx = lqasc_start_tx,
594 .stop_rx = lqasc_stop_rx,
595 .break_ctl = lqasc_break_ctl,
596 .startup = lqasc_startup,
597 .shutdown = lqasc_shutdown,
598 .set_termios = lqasc_set_termios,
599 .type = lqasc_type,
600 .release_port = lqasc_release_port,
601 .request_port = lqasc_request_port,
602 .config_port = lqasc_config_port,
603 .verify_port = lqasc_verify_port,
604 };
605
606 #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
607 static void
lqasc_console_putchar(struct uart_port * port,unsigned char ch)608 lqasc_console_putchar(struct uart_port *port, unsigned char ch)
609 {
610 if (!port->membase)
611 return;
612
613 while (!lqasc_tx_ready(port))
614 ;
615
616 writeb(ch, port->membase + LTQ_ASC_TBUF);
617 }
618
lqasc_serial_port_write(struct uart_port * port,const char * s,u_int count)619 static void lqasc_serial_port_write(struct uart_port *port, const char *s,
620 u_int count)
621 {
622 uart_console_write(port, s, count, lqasc_console_putchar);
623 }
624
625 static void
lqasc_console_write(struct console * co,const char * s,u_int count)626 lqasc_console_write(struct console *co, const char *s, u_int count)
627 {
628 struct ltq_uart_port *ltq_port;
629 unsigned long flags;
630
631 if (co->index >= MAXPORTS)
632 return;
633
634 ltq_port = lqasc_port[co->index];
635 if (!ltq_port)
636 return;
637
638 spin_lock_irqsave(<q_port->lock, flags);
639 lqasc_serial_port_write(<q_port->port, s, count);
640 spin_unlock_irqrestore(<q_port->lock, flags);
641 }
642
643 static int __init
lqasc_console_setup(struct console * co,char * options)644 lqasc_console_setup(struct console *co, char *options)
645 {
646 struct ltq_uart_port *ltq_port;
647 struct uart_port *port;
648 int baud = 115200;
649 int bits = 8;
650 int parity = 'n';
651 int flow = 'n';
652
653 if (co->index >= MAXPORTS)
654 return -ENODEV;
655
656 ltq_port = lqasc_port[co->index];
657 if (!ltq_port)
658 return -ENODEV;
659
660 port = <q_port->port;
661
662 if (!IS_ERR(ltq_port->clk))
663 clk_prepare_enable(ltq_port->clk);
664
665 port->uartclk = clk_get_rate(ltq_port->freqclk);
666
667 if (options)
668 uart_parse_options(options, &baud, &parity, &bits, &flow);
669 return uart_set_options(port, co, baud, parity, bits, flow);
670 }
671
672 static struct console lqasc_console = {
673 .name = "ttyLTQ",
674 .write = lqasc_console_write,
675 .device = uart_console_device,
676 .setup = lqasc_console_setup,
677 .flags = CON_PRINTBUFFER,
678 .index = -1,
679 .data = &lqasc_reg,
680 };
681
682 static int __init
lqasc_console_init(void)683 lqasc_console_init(void)
684 {
685 register_console(&lqasc_console);
686 return 0;
687 }
688 console_initcall(lqasc_console_init);
689
lqasc_serial_early_console_write(struct console * co,const char * s,u_int count)690 static void lqasc_serial_early_console_write(struct console *co,
691 const char *s,
692 u_int count)
693 {
694 struct earlycon_device *dev = co->data;
695
696 lqasc_serial_port_write(&dev->port, s, count);
697 }
698
699 static int __init
lqasc_serial_early_console_setup(struct earlycon_device * device,const char * opt)700 lqasc_serial_early_console_setup(struct earlycon_device *device,
701 const char *opt)
702 {
703 if (!device->port.membase)
704 return -ENODEV;
705
706 device->con->write = lqasc_serial_early_console_write;
707 return 0;
708 }
709 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
710 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
711
712 #define LANTIQ_SERIAL_CONSOLE (&lqasc_console)
713
714 #else
715
716 #define LANTIQ_SERIAL_CONSOLE NULL
717
718 #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */
719
720 static struct uart_driver lqasc_reg = {
721 .owner = THIS_MODULE,
722 .driver_name = DRVNAME,
723 .dev_name = "ttyLTQ",
724 .major = 0,
725 .minor = 0,
726 .nr = MAXPORTS,
727 .cons = LANTIQ_SERIAL_CONSOLE,
728 };
729
fetch_irq_lantiq(struct device * dev,struct ltq_uart_port * ltq_port)730 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
731 {
732 struct uart_port *port = <q_port->port;
733 struct platform_device *pdev = to_platform_device(dev);
734 int irq;
735
736 irq = platform_get_irq(pdev, 0);
737 if (irq < 0)
738 return irq;
739 ltq_port->tx_irq = irq;
740 irq = platform_get_irq(pdev, 1);
741 if (irq < 0)
742 return irq;
743 ltq_port->rx_irq = irq;
744 irq = platform_get_irq(pdev, 2);
745 if (irq < 0)
746 return irq;
747 ltq_port->err_irq = irq;
748
749 port->irq = ltq_port->tx_irq;
750
751 return 0;
752 }
753
request_irq_lantiq(struct uart_port * port)754 static int request_irq_lantiq(struct uart_port *port)
755 {
756 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
757 int retval;
758
759 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
760 0, "asc_tx", port);
761 if (retval) {
762 dev_err(port->dev, "failed to request asc_tx\n");
763 return retval;
764 }
765
766 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
767 0, "asc_rx", port);
768 if (retval) {
769 dev_err(port->dev, "failed to request asc_rx\n");
770 goto err1;
771 }
772
773 retval = request_irq(ltq_port->err_irq, lqasc_err_int,
774 0, "asc_err", port);
775 if (retval) {
776 dev_err(port->dev, "failed to request asc_err\n");
777 goto err2;
778 }
779 return 0;
780
781 err2:
782 free_irq(ltq_port->rx_irq, port);
783 err1:
784 free_irq(ltq_port->tx_irq, port);
785 return retval;
786 }
787
free_irq_lantiq(struct uart_port * port)788 static void free_irq_lantiq(struct uart_port *port)
789 {
790 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
791
792 free_irq(ltq_port->tx_irq, port);
793 free_irq(ltq_port->rx_irq, port);
794 free_irq(ltq_port->err_irq, port);
795 }
796
fetch_irq_intel(struct device * dev,struct ltq_uart_port * ltq_port)797 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port)
798 {
799 struct uart_port *port = <q_port->port;
800 int ret;
801
802 ret = platform_get_irq(to_platform_device(dev), 0);
803 if (ret < 0) {
804 dev_err(dev, "failed to fetch IRQ for serial port\n");
805 return ret;
806 }
807 ltq_port->common_irq = ret;
808 port->irq = ret;
809
810 return 0;
811 }
812
request_irq_intel(struct uart_port * port)813 static int request_irq_intel(struct uart_port *port)
814 {
815 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
816 int retval;
817
818 retval = request_irq(ltq_port->common_irq, lqasc_irq, 0,
819 "asc_irq", port);
820 if (retval)
821 dev_err(port->dev, "failed to request asc_irq\n");
822
823 return retval;
824 }
825
free_irq_intel(struct uart_port * port)826 static void free_irq_intel(struct uart_port *port)
827 {
828 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
829
830 free_irq(ltq_port->common_irq, port);
831 }
832
lqasc_probe(struct platform_device * pdev)833 static int lqasc_probe(struct platform_device *pdev)
834 {
835 struct device_node *node = pdev->dev.of_node;
836 struct ltq_uart_port *ltq_port;
837 struct uart_port *port;
838 struct resource *mmres;
839 int line;
840 int ret;
841
842 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
843 if (!mmres) {
844 dev_err(&pdev->dev,
845 "failed to get memory for serial port\n");
846 return -ENODEV;
847 }
848
849 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
850 GFP_KERNEL);
851 if (!ltq_port)
852 return -ENOMEM;
853
854 port = <q_port->port;
855
856 ltq_port->soc = of_device_get_match_data(&pdev->dev);
857 ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port);
858 if (ret)
859 return ret;
860
861 /* get serial id */
862 line = of_alias_get_id(node, "serial");
863 if (line < 0) {
864 if (IS_ENABLED(CONFIG_LANTIQ)) {
865 if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
866 line = 0;
867 else
868 line = 1;
869 } else {
870 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
871 line);
872 return line;
873 }
874 }
875
876 if (lqasc_port[line]) {
877 dev_err(&pdev->dev, "port %d already allocated\n", line);
878 return -EBUSY;
879 }
880
881 port->iotype = SERIAL_IO_MEM;
882 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
883 port->ops = &lqasc_pops;
884 port->fifosize = 16;
885 port->type = PORT_LTQ_ASC;
886 port->line = line;
887 port->dev = &pdev->dev;
888 /* unused, just to be backward-compatible */
889 port->mapbase = mmres->start;
890
891 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
892 ltq_port->freqclk = clk_get_fpi();
893 else
894 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
895
896
897 if (IS_ERR(ltq_port->freqclk)) {
898 pr_err("failed to get fpi clk\n");
899 return -ENOENT;
900 }
901
902 /* not all asc ports have clock gates, lets ignore the return code */
903 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
904 ltq_port->clk = clk_get(&pdev->dev, NULL);
905 else
906 ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
907
908 spin_lock_init(<q_port->lock);
909 lqasc_port[line] = ltq_port;
910 platform_set_drvdata(pdev, ltq_port);
911
912 ret = uart_add_one_port(&lqasc_reg, port);
913
914 return ret;
915 }
916
lqasc_remove(struct platform_device * pdev)917 static int lqasc_remove(struct platform_device *pdev)
918 {
919 struct uart_port *port = platform_get_drvdata(pdev);
920
921 return uart_remove_one_port(&lqasc_reg, port);
922 }
923
924 static const struct ltq_soc_data soc_data_lantiq = {
925 .fetch_irq = fetch_irq_lantiq,
926 .request_irq = request_irq_lantiq,
927 .free_irq = free_irq_lantiq,
928 };
929
930 static const struct ltq_soc_data soc_data_intel = {
931 .fetch_irq = fetch_irq_intel,
932 .request_irq = request_irq_intel,
933 .free_irq = free_irq_intel,
934 };
935
936 static const struct of_device_id ltq_asc_match[] = {
937 { .compatible = "lantiq,asc", .data = &soc_data_lantiq },
938 { .compatible = "intel,lgm-asc", .data = &soc_data_intel },
939 {},
940 };
941 MODULE_DEVICE_TABLE(of, ltq_asc_match);
942
943 static struct platform_driver lqasc_driver = {
944 .probe = lqasc_probe,
945 .remove = lqasc_remove,
946 .driver = {
947 .name = DRVNAME,
948 .of_match_table = ltq_asc_match,
949 },
950 };
951
952 static int __init
init_lqasc(void)953 init_lqasc(void)
954 {
955 int ret;
956
957 ret = uart_register_driver(&lqasc_reg);
958 if (ret != 0)
959 return ret;
960
961 ret = platform_driver_register(&lqasc_driver);
962 if (ret != 0)
963 uart_unregister_driver(&lqasc_reg);
964
965 return ret;
966 }
967
exit_lqasc(void)968 static void __exit exit_lqasc(void)
969 {
970 platform_driver_unregister(&lqasc_driver);
971 uart_unregister_driver(&lqasc_reg);
972 }
973
974 module_init(init_lqasc);
975 module_exit(exit_lqasc);
976
977 MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
978 MODULE_LICENSE("GPL v2");
979