1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PIC32 Integrated Serial Driver.
4 *
5 * Copyright (C) 2015 Microchip Technology, Inc.
6 *
7 * Authors:
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/platform_device.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_gpio.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/console.h>
21 #include <linux/clk.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/serial_core.h>
25 #include <linux/delay.h>
26
27 #include <asm/mach-pic32/pic32.h>
28
29 /* UART name and device definitions */
30 #define PIC32_DEV_NAME "pic32-uart"
31 #define PIC32_MAX_UARTS 6
32 #define PIC32_SDEV_NAME "ttyPIC"
33
34 #define PIC32_UART_DFLT_BRATE 9600
35 #define PIC32_UART_TX_FIFO_DEPTH 8
36 #define PIC32_UART_RX_FIFO_DEPTH 8
37
38 #define PIC32_UART_MODE 0x00
39 #define PIC32_UART_STA 0x10
40 #define PIC32_UART_TX 0x20
41 #define PIC32_UART_RX 0x30
42 #define PIC32_UART_BRG 0x40
43
44 /* struct pic32_sport - pic32 serial port descriptor
45 * @port: uart port descriptor
46 * @idx: port index
47 * @irq_fault: virtual fault interrupt number
48 * @irq_fault_name: irq fault name
49 * @irq_rx: virtual rx interrupt number
50 * @irq_rx_name: irq rx name
51 * @irq_tx: virtual tx interrupt number
52 * @irq_tx_name: irq tx name
53 * @cts_gpiod: clear to send GPIO
54 * @dev: device descriptor
55 **/
56 struct pic32_sport {
57 struct uart_port port;
58 int idx;
59
60 int irq_fault;
61 const char *irq_fault_name;
62 int irq_rx;
63 const char *irq_rx_name;
64 int irq_tx;
65 const char *irq_tx_name;
66 bool enable_tx_irq;
67
68 struct gpio_desc *cts_gpiod;
69
70 struct clk *clk;
71
72 struct device *dev;
73 };
74
to_pic32_sport(struct uart_port * port)75 static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
76 {
77 return container_of(port, struct pic32_sport, port);
78 }
79
pic32_uart_writel(struct pic32_sport * sport,u32 reg,u32 val)80 static inline void pic32_uart_writel(struct pic32_sport *sport,
81 u32 reg, u32 val)
82 {
83 __raw_writel(val, sport->port.membase + reg);
84 }
85
pic32_uart_readl(struct pic32_sport * sport,u32 reg)86 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
87 {
88 return __raw_readl(sport->port.membase + reg);
89 }
90
91 /* pic32 uart mode register bits */
92 #define PIC32_UART_MODE_ON BIT(15)
93 #define PIC32_UART_MODE_FRZ BIT(14)
94 #define PIC32_UART_MODE_SIDL BIT(13)
95 #define PIC32_UART_MODE_IREN BIT(12)
96 #define PIC32_UART_MODE_RTSMD BIT(11)
97 #define PIC32_UART_MODE_RESV1 BIT(10)
98 #define PIC32_UART_MODE_UEN1 BIT(9)
99 #define PIC32_UART_MODE_UEN0 BIT(8)
100 #define PIC32_UART_MODE_WAKE BIT(7)
101 #define PIC32_UART_MODE_LPBK BIT(6)
102 #define PIC32_UART_MODE_ABAUD BIT(5)
103 #define PIC32_UART_MODE_RXINV BIT(4)
104 #define PIC32_UART_MODE_BRGH BIT(3)
105 #define PIC32_UART_MODE_PDSEL1 BIT(2)
106 #define PIC32_UART_MODE_PDSEL0 BIT(1)
107 #define PIC32_UART_MODE_STSEL BIT(0)
108
109 /* pic32 uart status register bits */
110 #define PIC32_UART_STA_UTXISEL1 BIT(15)
111 #define PIC32_UART_STA_UTXISEL0 BIT(14)
112 #define PIC32_UART_STA_UTXINV BIT(13)
113 #define PIC32_UART_STA_URXEN BIT(12)
114 #define PIC32_UART_STA_UTXBRK BIT(11)
115 #define PIC32_UART_STA_UTXEN BIT(10)
116 #define PIC32_UART_STA_UTXBF BIT(9)
117 #define PIC32_UART_STA_TRMT BIT(8)
118 #define PIC32_UART_STA_URXISEL1 BIT(7)
119 #define PIC32_UART_STA_URXISEL0 BIT(6)
120 #define PIC32_UART_STA_ADDEN BIT(5)
121 #define PIC32_UART_STA_RIDLE BIT(4)
122 #define PIC32_UART_STA_PERR BIT(3)
123 #define PIC32_UART_STA_FERR BIT(2)
124 #define PIC32_UART_STA_OERR BIT(1)
125 #define PIC32_UART_STA_URXDA BIT(0)
126
127 /* pic32_sport pointer for console use */
128 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
129
pic32_wait_deplete_txbuf(struct pic32_sport * sport)130 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
131 {
132 /* wait for tx empty, otherwise chars will be lost or corrupted */
133 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
134 udelay(1);
135 }
136
137 /* serial core request to check if uart tx buffer is empty */
pic32_uart_tx_empty(struct uart_port * port)138 static unsigned int pic32_uart_tx_empty(struct uart_port *port)
139 {
140 struct pic32_sport *sport = to_pic32_sport(port);
141 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
142
143 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
144 }
145
146 /* serial core request to set UART outputs */
pic32_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)147 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
148 {
149 struct pic32_sport *sport = to_pic32_sport(port);
150
151 /* set loopback mode */
152 if (mctrl & TIOCM_LOOP)
153 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
154 PIC32_UART_MODE_LPBK);
155 else
156 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
157 PIC32_UART_MODE_LPBK);
158 }
159
160 /* serial core request to return the state of misc UART input pins */
pic32_uart_get_mctrl(struct uart_port * port)161 static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
162 {
163 struct pic32_sport *sport = to_pic32_sport(port);
164 unsigned int mctrl = 0;
165
166 /* get the state of CTS input pin for this port */
167 if (!sport->cts_gpiod)
168 mctrl |= TIOCM_CTS;
169 else if (gpiod_get_value(sport->cts_gpiod))
170 mctrl |= TIOCM_CTS;
171
172 /* DSR and CD are not supported in PIC32, so return 1
173 * RI is not supported in PIC32, so return 0
174 */
175 mctrl |= TIOCM_CD;
176 mctrl |= TIOCM_DSR;
177
178 return mctrl;
179 }
180
181 /* stop tx and start tx are not called in pairs, therefore a flag indicates
182 * the status of irq to control the irq-depth.
183 */
pic32_uart_irqtxen(struct pic32_sport * sport,u8 en)184 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
185 {
186 if (en && !sport->enable_tx_irq) {
187 enable_irq(sport->irq_tx);
188 sport->enable_tx_irq = true;
189 } else if (!en && sport->enable_tx_irq) {
190 /* use disable_irq_nosync() and not disable_irq() to avoid self
191 * imposed deadlock by not waiting for irq handler to end,
192 * since this callback is called from interrupt context.
193 */
194 disable_irq_nosync(sport->irq_tx);
195 sport->enable_tx_irq = false;
196 }
197 }
198
199 /* serial core request to disable tx ASAP (used for flow control) */
pic32_uart_stop_tx(struct uart_port * port)200 static void pic32_uart_stop_tx(struct uart_port *port)
201 {
202 struct pic32_sport *sport = to_pic32_sport(port);
203
204 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
205 return;
206
207 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
208 return;
209
210 /* wait for tx empty */
211 pic32_wait_deplete_txbuf(sport);
212
213 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
214 PIC32_UART_STA_UTXEN);
215 pic32_uart_irqtxen(sport, 0);
216 }
217
218 /* serial core request to (re)enable tx */
pic32_uart_start_tx(struct uart_port * port)219 static void pic32_uart_start_tx(struct uart_port *port)
220 {
221 struct pic32_sport *sport = to_pic32_sport(port);
222
223 pic32_uart_irqtxen(sport, 1);
224 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
225 PIC32_UART_STA_UTXEN);
226 }
227
228 /* serial core request to stop rx, called before port shutdown */
pic32_uart_stop_rx(struct uart_port * port)229 static void pic32_uart_stop_rx(struct uart_port *port)
230 {
231 struct pic32_sport *sport = to_pic32_sport(port);
232
233 /* disable rx interrupts */
234 disable_irq(sport->irq_rx);
235
236 /* receiver Enable bit OFF */
237 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
238 PIC32_UART_STA_URXEN);
239 }
240
241 /* serial core request to start/stop emitting break char */
pic32_uart_break_ctl(struct uart_port * port,int ctl)242 static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
243 {
244 struct pic32_sport *sport = to_pic32_sport(port);
245 unsigned long flags;
246
247 spin_lock_irqsave(&port->lock, flags);
248
249 if (ctl)
250 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
251 PIC32_UART_STA_UTXBRK);
252 else
253 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
254 PIC32_UART_STA_UTXBRK);
255
256 spin_unlock_irqrestore(&port->lock, flags);
257 }
258
259 /* get port type in string format */
pic32_uart_type(struct uart_port * port)260 static const char *pic32_uart_type(struct uart_port *port)
261 {
262 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
263 }
264
265 /* read all chars in rx fifo and send them to core */
pic32_uart_do_rx(struct uart_port * port)266 static void pic32_uart_do_rx(struct uart_port *port)
267 {
268 struct pic32_sport *sport = to_pic32_sport(port);
269 struct tty_port *tty;
270 unsigned int max_count;
271
272 /* limit number of char read in interrupt, should not be
273 * higher than fifo size anyway since we're much faster than
274 * serial port
275 */
276 max_count = PIC32_UART_RX_FIFO_DEPTH;
277
278 spin_lock(&port->lock);
279
280 tty = &port->state->port;
281
282 do {
283 u32 sta_reg, c;
284 char flag;
285
286 /* get overrun/fifo empty information from status register */
287 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
288 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
289
290 /* fifo reset is required to clear interrupt */
291 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
292 PIC32_UART_STA_OERR);
293
294 port->icount.overrun++;
295 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
296 }
297
298 /* Can at least one more character can be read? */
299 if (!(sta_reg & PIC32_UART_STA_URXDA))
300 break;
301
302 /* read the character and increment the rx counter */
303 c = pic32_uart_readl(sport, PIC32_UART_RX);
304
305 port->icount.rx++;
306 flag = TTY_NORMAL;
307 c &= 0xff;
308
309 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
310 (sta_reg & PIC32_UART_STA_FERR))) {
311
312 /* do stats first */
313 if (sta_reg & PIC32_UART_STA_PERR)
314 port->icount.parity++;
315 if (sta_reg & PIC32_UART_STA_FERR)
316 port->icount.frame++;
317
318 /* update flag wrt read_status_mask */
319 sta_reg &= port->read_status_mask;
320
321 if (sta_reg & PIC32_UART_STA_FERR)
322 flag = TTY_FRAME;
323 if (sta_reg & PIC32_UART_STA_PERR)
324 flag = TTY_PARITY;
325 }
326
327 if (uart_handle_sysrq_char(port, c))
328 continue;
329
330 if ((sta_reg & port->ignore_status_mask) == 0)
331 tty_insert_flip_char(tty, c, flag);
332
333 } while (--max_count);
334
335 spin_unlock(&port->lock);
336
337 tty_flip_buffer_push(tty);
338 }
339
340 /* fill tx fifo with chars to send, stop when fifo is about to be full
341 * or when all chars have been sent.
342 */
pic32_uart_do_tx(struct uart_port * port)343 static void pic32_uart_do_tx(struct uart_port *port)
344 {
345 struct pic32_sport *sport = to_pic32_sport(port);
346 struct circ_buf *xmit = &port->state->xmit;
347 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
348
349 if (port->x_char) {
350 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
351 port->icount.tx++;
352 port->x_char = 0;
353 return;
354 }
355
356 if (uart_tx_stopped(port)) {
357 pic32_uart_stop_tx(port);
358 return;
359 }
360
361 if (uart_circ_empty(xmit))
362 goto txq_empty;
363
364 /* keep stuffing chars into uart tx buffer
365 * 1) until uart fifo is full
366 * or
367 * 2) until the circ buffer is empty
368 * (all chars have been sent)
369 * or
370 * 3) until the max count is reached
371 * (prevents lingering here for too long in certain cases)
372 */
373 while (!(PIC32_UART_STA_UTXBF &
374 pic32_uart_readl(sport, PIC32_UART_STA))) {
375 unsigned int c = xmit->buf[xmit->tail];
376
377 pic32_uart_writel(sport, PIC32_UART_TX, c);
378
379 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
380 port->icount.tx++;
381 if (uart_circ_empty(xmit))
382 break;
383 if (--max_count == 0)
384 break;
385 }
386
387 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
388 uart_write_wakeup(port);
389
390 if (uart_circ_empty(xmit))
391 goto txq_empty;
392
393 return;
394
395 txq_empty:
396 pic32_uart_irqtxen(sport, 0);
397 }
398
399 /* RX interrupt handler */
pic32_uart_rx_interrupt(int irq,void * dev_id)400 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
401 {
402 struct uart_port *port = dev_id;
403
404 pic32_uart_do_rx(port);
405
406 return IRQ_HANDLED;
407 }
408
409 /* TX interrupt handler */
pic32_uart_tx_interrupt(int irq,void * dev_id)410 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
411 {
412 struct uart_port *port = dev_id;
413 unsigned long flags;
414
415 spin_lock_irqsave(&port->lock, flags);
416 pic32_uart_do_tx(port);
417 spin_unlock_irqrestore(&port->lock, flags);
418
419 return IRQ_HANDLED;
420 }
421
422 /* FAULT interrupt handler */
pic32_uart_fault_interrupt(int irq,void * dev_id)423 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
424 {
425 /* do nothing: pic32_uart_do_rx() handles faults. */
426 return IRQ_HANDLED;
427 }
428
429 /* enable rx & tx operation on uart */
pic32_uart_en_and_unmask(struct uart_port * port)430 static void pic32_uart_en_and_unmask(struct uart_port *port)
431 {
432 struct pic32_sport *sport = to_pic32_sport(port);
433
434 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
435 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
436 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
437 PIC32_UART_MODE_ON);
438 }
439
440 /* disable rx & tx operation on uart */
pic32_uart_dsbl_and_mask(struct uart_port * port)441 static void pic32_uart_dsbl_and_mask(struct uart_port *port)
442 {
443 struct pic32_sport *sport = to_pic32_sport(port);
444
445 /* wait for tx empty, otherwise chars will be lost or corrupted */
446 pic32_wait_deplete_txbuf(sport);
447
448 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
449 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
450 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
451 PIC32_UART_MODE_ON);
452 }
453
454 /* serial core request to initialize uart and start rx operation */
pic32_uart_startup(struct uart_port * port)455 static int pic32_uart_startup(struct uart_port *port)
456 {
457 struct pic32_sport *sport = to_pic32_sport(port);
458 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
459 unsigned long flags;
460 int ret;
461
462 local_irq_save(flags);
463
464 ret = clk_prepare_enable(sport->clk);
465 if (ret) {
466 local_irq_restore(flags);
467 goto out_done;
468 }
469
470 /* clear status and mode registers */
471 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
472 pic32_uart_writel(sport, PIC32_UART_STA, 0);
473
474 /* disable uart and mask all interrupts */
475 pic32_uart_dsbl_and_mask(port);
476
477 /* set default baud */
478 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
479
480 local_irq_restore(flags);
481
482 /* Each UART of a PIC32 has three interrupts therefore,
483 * we setup driver to register the 3 irqs for the device.
484 *
485 * For each irq request_irq() is called with interrupt disabled.
486 * And the irq is enabled as soon as we are ready to handle them.
487 */
488 sport->enable_tx_irq = false;
489
490 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
491 pic32_uart_type(port),
492 sport->idx);
493 if (!sport->irq_fault_name) {
494 dev_err(port->dev, "%s: kasprintf err!", __func__);
495 ret = -ENOMEM;
496 goto out_disable_clk;
497 }
498 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
499 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
500 IRQF_NO_THREAD, sport->irq_fault_name, port);
501 if (ret) {
502 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
503 __func__, sport->irq_fault, ret,
504 pic32_uart_type(port));
505 goto out_f;
506 }
507
508 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
509 pic32_uart_type(port),
510 sport->idx);
511 if (!sport->irq_rx_name) {
512 dev_err(port->dev, "%s: kasprintf err!", __func__);
513 ret = -ENOMEM;
514 goto out_f;
515 }
516 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
517 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
518 IRQF_NO_THREAD, sport->irq_rx_name, port);
519 if (ret) {
520 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
521 __func__, sport->irq_rx, ret,
522 pic32_uart_type(port));
523 goto out_r;
524 }
525
526 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
527 pic32_uart_type(port),
528 sport->idx);
529 if (!sport->irq_tx_name) {
530 dev_err(port->dev, "%s: kasprintf err!", __func__);
531 ret = -ENOMEM;
532 goto out_r;
533 }
534 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
535 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
536 IRQF_NO_THREAD, sport->irq_tx_name, port);
537 if (ret) {
538 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
539 __func__, sport->irq_tx, ret,
540 pic32_uart_type(port));
541 goto out_t;
542 }
543
544 local_irq_save(flags);
545
546 /* set rx interrupt on first receive */
547 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
548 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
549
550 /* set interrupt on empty */
551 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
552 PIC32_UART_STA_UTXISEL1);
553
554 /* enable all interrupts and eanable uart */
555 pic32_uart_en_and_unmask(port);
556
557 local_irq_restore(flags);
558
559 enable_irq(sport->irq_rx);
560
561 return 0;
562
563 out_t:
564 free_irq(sport->irq_tx, port);
565 kfree(sport->irq_tx_name);
566 out_r:
567 free_irq(sport->irq_rx, port);
568 kfree(sport->irq_rx_name);
569 out_f:
570 free_irq(sport->irq_fault, port);
571 kfree(sport->irq_fault_name);
572 out_disable_clk:
573 clk_disable_unprepare(sport->clk);
574 out_done:
575 return ret;
576 }
577
578 /* serial core request to flush & disable uart */
pic32_uart_shutdown(struct uart_port * port)579 static void pic32_uart_shutdown(struct uart_port *port)
580 {
581 struct pic32_sport *sport = to_pic32_sport(port);
582 unsigned long flags;
583
584 /* disable uart */
585 spin_lock_irqsave(&port->lock, flags);
586 pic32_uart_dsbl_and_mask(port);
587 spin_unlock_irqrestore(&port->lock, flags);
588 clk_disable_unprepare(sport->clk);
589
590 /* free all 3 interrupts for this UART */
591 free_irq(sport->irq_fault, port);
592 kfree(sport->irq_fault_name);
593 free_irq(sport->irq_tx, port);
594 kfree(sport->irq_tx_name);
595 free_irq(sport->irq_rx, port);
596 kfree(sport->irq_rx_name);
597 }
598
599 /* serial core request to change current uart setting */
pic32_uart_set_termios(struct uart_port * port,struct ktermios * new,const struct ktermios * old)600 static void pic32_uart_set_termios(struct uart_port *port,
601 struct ktermios *new,
602 const struct ktermios *old)
603 {
604 struct pic32_sport *sport = to_pic32_sport(port);
605 unsigned int baud;
606 unsigned int quot;
607 unsigned long flags;
608
609 spin_lock_irqsave(&port->lock, flags);
610
611 /* disable uart and mask all interrupts while changing speed */
612 pic32_uart_dsbl_and_mask(port);
613
614 /* stop bit options */
615 if (new->c_cflag & CSTOPB)
616 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
617 PIC32_UART_MODE_STSEL);
618 else
619 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
620 PIC32_UART_MODE_STSEL);
621
622 /* parity options */
623 if (new->c_cflag & PARENB) {
624 if (new->c_cflag & PARODD) {
625 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
626 PIC32_UART_MODE_PDSEL1);
627 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
628 PIC32_UART_MODE_PDSEL0);
629 } else {
630 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
631 PIC32_UART_MODE_PDSEL0);
632 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
633 PIC32_UART_MODE_PDSEL1);
634 }
635 } else {
636 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
637 PIC32_UART_MODE_PDSEL1 |
638 PIC32_UART_MODE_PDSEL0);
639 }
640 /* if hw flow ctrl, then the pins must be specified in device tree */
641 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) {
642 /* enable hardware flow control */
643 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
644 PIC32_UART_MODE_UEN1);
645 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
646 PIC32_UART_MODE_UEN0);
647 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
648 PIC32_UART_MODE_RTSMD);
649 } else {
650 /* disable hardware flow control */
651 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
652 PIC32_UART_MODE_UEN1);
653 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
654 PIC32_UART_MODE_UEN0);
655 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
656 PIC32_UART_MODE_RTSMD);
657 }
658
659 /* Always 8-bit */
660 new->c_cflag |= CS8;
661
662 /* Mark/Space parity is not supported */
663 new->c_cflag &= ~CMSPAR;
664
665 /* update baud */
666 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
667 quot = uart_get_divisor(port, baud) - 1;
668 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
669 uart_update_timeout(port, new->c_cflag, baud);
670
671 if (tty_termios_baud_rate(new))
672 tty_termios_encode_baud_rate(new, baud, baud);
673
674 /* enable uart */
675 pic32_uart_en_and_unmask(port);
676
677 spin_unlock_irqrestore(&port->lock, flags);
678 }
679
680 /* serial core request to claim uart iomem */
pic32_uart_request_port(struct uart_port * port)681 static int pic32_uart_request_port(struct uart_port *port)
682 {
683 struct platform_device *pdev = to_platform_device(port->dev);
684 struct resource *res_mem;
685
686 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
687 if (unlikely(!res_mem))
688 return -EINVAL;
689
690 if (!request_mem_region(port->mapbase, resource_size(res_mem),
691 "pic32_uart_mem"))
692 return -EBUSY;
693
694 port->membase = devm_ioremap(port->dev, port->mapbase,
695 resource_size(res_mem));
696 if (!port->membase) {
697 dev_err(port->dev, "Unable to map registers\n");
698 release_mem_region(port->mapbase, resource_size(res_mem));
699 return -ENOMEM;
700 }
701
702 return 0;
703 }
704
705 /* serial core request to release uart iomem */
pic32_uart_release_port(struct uart_port * port)706 static void pic32_uart_release_port(struct uart_port *port)
707 {
708 struct platform_device *pdev = to_platform_device(port->dev);
709 struct resource *res_mem;
710 unsigned int res_size;
711
712 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
713 if (unlikely(!res_mem))
714 return;
715 res_size = resource_size(res_mem);
716
717 release_mem_region(port->mapbase, res_size);
718 }
719
720 /* serial core request to do any port required auto-configuration */
pic32_uart_config_port(struct uart_port * port,int flags)721 static void pic32_uart_config_port(struct uart_port *port, int flags)
722 {
723 if (flags & UART_CONFIG_TYPE) {
724 if (pic32_uart_request_port(port))
725 return;
726 port->type = PORT_PIC32;
727 }
728 }
729
730 /* serial core request to check that port information in serinfo are suitable */
pic32_uart_verify_port(struct uart_port * port,struct serial_struct * serinfo)731 static int pic32_uart_verify_port(struct uart_port *port,
732 struct serial_struct *serinfo)
733 {
734 if (port->type != PORT_PIC32)
735 return -EINVAL;
736 if (port->irq != serinfo->irq)
737 return -EINVAL;
738 if (port->iotype != serinfo->io_type)
739 return -EINVAL;
740 if (port->mapbase != (unsigned long)serinfo->iomem_base)
741 return -EINVAL;
742
743 return 0;
744 }
745
746 /* serial core callbacks */
747 static const struct uart_ops pic32_uart_ops = {
748 .tx_empty = pic32_uart_tx_empty,
749 .get_mctrl = pic32_uart_get_mctrl,
750 .set_mctrl = pic32_uart_set_mctrl,
751 .start_tx = pic32_uart_start_tx,
752 .stop_tx = pic32_uart_stop_tx,
753 .stop_rx = pic32_uart_stop_rx,
754 .break_ctl = pic32_uart_break_ctl,
755 .startup = pic32_uart_startup,
756 .shutdown = pic32_uart_shutdown,
757 .set_termios = pic32_uart_set_termios,
758 .type = pic32_uart_type,
759 .release_port = pic32_uart_release_port,
760 .request_port = pic32_uart_request_port,
761 .config_port = pic32_uart_config_port,
762 .verify_port = pic32_uart_verify_port,
763 };
764
765 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
766 /* output given char */
pic32_console_putchar(struct uart_port * port,unsigned char ch)767 static void pic32_console_putchar(struct uart_port *port, unsigned char ch)
768 {
769 struct pic32_sport *sport = to_pic32_sport(port);
770
771 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
772 return;
773
774 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
775 return;
776
777 /* wait for tx empty */
778 pic32_wait_deplete_txbuf(sport);
779
780 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
781 }
782
783 /* console core request to output given string */
pic32_console_write(struct console * co,const char * s,unsigned int count)784 static void pic32_console_write(struct console *co, const char *s,
785 unsigned int count)
786 {
787 struct pic32_sport *sport = pic32_sports[co->index];
788
789 /* call uart helper to deal with \r\n */
790 uart_console_write(&sport->port, s, count, pic32_console_putchar);
791 }
792
793 /* console core request to setup given console, find matching uart
794 * port and setup it.
795 */
pic32_console_setup(struct console * co,char * options)796 static int pic32_console_setup(struct console *co, char *options)
797 {
798 struct pic32_sport *sport;
799 int baud = 115200;
800 int bits = 8;
801 int parity = 'n';
802 int flow = 'n';
803 int ret = 0;
804
805 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
806 return -ENODEV;
807
808 sport = pic32_sports[co->index];
809 if (!sport)
810 return -ENODEV;
811
812 ret = clk_prepare_enable(sport->clk);
813 if (ret)
814 return ret;
815
816 if (options)
817 uart_parse_options(options, &baud, &parity, &bits, &flow);
818
819 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
820 }
821
822 static struct uart_driver pic32_uart_driver;
823 static struct console pic32_console = {
824 .name = PIC32_SDEV_NAME,
825 .write = pic32_console_write,
826 .device = uart_console_device,
827 .setup = pic32_console_setup,
828 .flags = CON_PRINTBUFFER,
829 .index = -1,
830 .data = &pic32_uart_driver,
831 };
832 #define PIC32_SCONSOLE (&pic32_console)
833
pic32_console_init(void)834 static int __init pic32_console_init(void)
835 {
836 register_console(&pic32_console);
837 return 0;
838 }
839 console_initcall(pic32_console_init);
840
841 /*
842 * Late console initialization.
843 */
pic32_late_console_init(void)844 static int __init pic32_late_console_init(void)
845 {
846 if (!(pic32_console.flags & CON_ENABLED))
847 register_console(&pic32_console);
848
849 return 0;
850 }
851
852 core_initcall(pic32_late_console_init);
853
854 #else
855 #define PIC32_SCONSOLE NULL
856 #endif
857
858 static struct uart_driver pic32_uart_driver = {
859 .owner = THIS_MODULE,
860 .driver_name = PIC32_DEV_NAME,
861 .dev_name = PIC32_SDEV_NAME,
862 .nr = PIC32_MAX_UARTS,
863 .cons = PIC32_SCONSOLE,
864 };
865
pic32_uart_probe(struct platform_device * pdev)866 static int pic32_uart_probe(struct platform_device *pdev)
867 {
868 struct device *dev = &pdev->dev;
869 struct device_node *np = dev->of_node;
870 struct pic32_sport *sport;
871 int uart_idx = 0;
872 struct resource *res_mem;
873 struct uart_port *port;
874 int ret;
875
876 uart_idx = of_alias_get_id(np, "serial");
877 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
878 return -EINVAL;
879
880 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
881 if (!res_mem)
882 return -EINVAL;
883
884 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
885 if (!sport)
886 return -ENOMEM;
887
888 sport->idx = uart_idx;
889 sport->irq_fault = irq_of_parse_and_map(np, 0);
890 sport->irq_rx = irq_of_parse_and_map(np, 1);
891 sport->irq_tx = irq_of_parse_and_map(np, 2);
892 sport->clk = devm_clk_get(&pdev->dev, NULL);
893 sport->dev = &pdev->dev;
894
895 /* Hardware flow control: gpios
896 * !Note: Basically, CTS is needed for reading the status.
897 */
898 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN);
899 if (IS_ERR(sport->cts_gpiod))
900 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n");
901 gpiod_set_consumer_name(sport->cts_gpiod, "CTS");
902
903 pic32_sports[uart_idx] = sport;
904 port = &sport->port;
905 port->iotype = UPIO_MEM;
906 port->mapbase = res_mem->start;
907 port->ops = &pic32_uart_ops;
908 port->flags = UPF_BOOT_AUTOCONF;
909 port->dev = &pdev->dev;
910 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
911 port->uartclk = clk_get_rate(sport->clk);
912 port->line = uart_idx;
913
914 ret = uart_add_one_port(&pic32_uart_driver, port);
915 if (ret) {
916 port->membase = NULL;
917 dev_err(port->dev, "%s: uart add port error!\n", __func__);
918 goto err;
919 }
920
921 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
922 if (uart_console_enabled(port)) {
923 /* The peripheral clock has been enabled by console_setup,
924 * so disable it till the port is used.
925 */
926 clk_disable_unprepare(sport->clk);
927 }
928 #endif
929
930 platform_set_drvdata(pdev, port);
931
932 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
933 __func__, uart_idx);
934
935 return 0;
936 err:
937 /* automatic unroll of sport and gpios */
938 return ret;
939 }
940
pic32_uart_remove(struct platform_device * pdev)941 static int pic32_uart_remove(struct platform_device *pdev)
942 {
943 struct uart_port *port = platform_get_drvdata(pdev);
944 struct pic32_sport *sport = to_pic32_sport(port);
945
946 uart_remove_one_port(&pic32_uart_driver, port);
947 clk_disable_unprepare(sport->clk);
948 platform_set_drvdata(pdev, NULL);
949 pic32_sports[sport->idx] = NULL;
950
951 /* automatic unroll of sport and gpios */
952 return 0;
953 }
954
955 static const struct of_device_id pic32_serial_dt_ids[] = {
956 { .compatible = "microchip,pic32mzda-uart" },
957 { /* sentinel */ }
958 };
959 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
960
961 static struct platform_driver pic32_uart_platform_driver = {
962 .probe = pic32_uart_probe,
963 .remove = pic32_uart_remove,
964 .driver = {
965 .name = PIC32_DEV_NAME,
966 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
967 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
968 },
969 };
970
pic32_uart_init(void)971 static int __init pic32_uart_init(void)
972 {
973 int ret;
974
975 ret = uart_register_driver(&pic32_uart_driver);
976 if (ret) {
977 pr_err("failed to register %s:%d\n",
978 pic32_uart_driver.driver_name, ret);
979 return ret;
980 }
981
982 ret = platform_driver_register(&pic32_uart_platform_driver);
983 if (ret) {
984 pr_err("fail to register pic32 uart\n");
985 uart_unregister_driver(&pic32_uart_driver);
986 }
987
988 return ret;
989 }
990 arch_initcall(pic32_uart_init);
991
pic32_uart_exit(void)992 static void __exit pic32_uart_exit(void)
993 {
994 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
995 unregister_console(&pic32_console);
996 #endif
997 platform_driver_unregister(&pic32_uart_platform_driver);
998 uart_unregister_driver(&pic32_uart_driver);
999 }
1000 module_exit(pic32_uart_exit);
1001
1002 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
1003 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
1004 MODULE_LICENSE("GPL v2");
1005