1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
25
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
28
29 #include <drm/display/drm_dp.h>
30 #include <drm/drm_connector.h>
31
32 struct drm_device;
33 struct drm_dp_aux;
34 struct drm_panel;
35
36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
37 int lane_count);
38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
39 int lane_count);
40 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
41 int lane);
42 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
43 int lane);
44 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
45 int lane);
46
47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
48 enum drm_dp_phy dp_phy, bool uhbr);
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 enum drm_dp_phy dp_phy, bool uhbr);
51
52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
54 void drm_dp_lttpr_link_train_clock_recovery_delay(void);
55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
59
60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
61 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
62 int lane_count);
63 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
64 int lane_count);
65 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
66 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
67 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
68
69 u8 drm_dp_link_rate_to_bw_code(int link_rate);
70 int drm_dp_bw_code_to_link_rate(u8 link_bw);
71
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
73
74 /**
75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
76 *
77 * This structure represents a DP VSC SDP of drm
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
80 *
81 * @sdp_type: secondary-data packet type
82 * @revision: revision number
83 * @length: number of valid data bytes
84 * @pixelformat: pixel encoding format
85 * @colorimetry: colorimetry format
86 * @bpc: bit per color
87 * @dynamic_range: dynamic range information
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
89 */
90 struct drm_dp_vsc_sdp {
91 unsigned char sdp_type;
92 unsigned char revision;
93 unsigned char length;
94 enum dp_pixelformat pixelformat;
95 enum dp_colorimetry colorimetry;
96 int bpc;
97 enum dp_dynamic_range dynamic_range;
98 enum dp_content_type content_type;
99 };
100
101 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
102 const struct drm_dp_vsc_sdp *vsc);
103
104 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
105
106 static inline int
drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])107 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
108 {
109 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
110 }
111
112 static inline u8
drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])113 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
114 {
115 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
116 }
117
118 static inline bool
drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])119 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
120 {
121 return dpcd[DP_DPCD_REV] >= 0x11 &&
122 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
123 }
124
125 static inline bool
drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])126 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
127 {
128 return dpcd[DP_DPCD_REV] >= 0x11 &&
129 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
130 }
131
132 static inline bool
drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])133 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
134 {
135 return dpcd[DP_DPCD_REV] >= 0x12 &&
136 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
137 }
138
139 static inline bool
drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])140 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
141 {
142 return dpcd[DP_DPCD_REV] >= 0x11 ||
143 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
144 }
145
146 static inline bool
drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])147 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
148 {
149 return dpcd[DP_DPCD_REV] >= 0x14 &&
150 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
151 }
152
153 static inline u8
drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])154 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
155 {
156 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
157 DP_TRAINING_PATTERN_MASK;
158 }
159
160 static inline bool
drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])161 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
162 {
163 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
164 }
165
166 /* DP/eDP DSC support */
167 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
168 bool is_edp);
169 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
170 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
171 u8 dsc_bpc[3]);
172
173 static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])174 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
175 {
176 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
177 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
178 }
179
180 static inline u16
drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])181 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
182 {
183 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
184 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
185 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8);
186 }
187
188 static inline u32
drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])189 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
190 {
191 /* Max Slicewidth = Number of Pixels * 320 */
192 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
193 DP_DSC_SLICE_WIDTH_MULTIPLIER;
194 }
195
196 /* Forward Error Correction Support on DP 1.4 */
197 static inline bool
drm_dp_sink_supports_fec(const u8 fec_capable)198 drm_dp_sink_supports_fec(const u8 fec_capable)
199 {
200 return fec_capable & DP_FEC_CAPABLE;
201 }
202
203 static inline bool
drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])204 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
205 {
206 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
207 }
208
209 static inline bool
drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])210 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
211 {
212 return dpcd[DP_EDP_CONFIGURATION_CAP] &
213 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
214 }
215
216 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
217 static inline bool
drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])218 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
219 {
220 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
221 DP_MSA_TIMING_PAR_IGNORED;
222 }
223
224 /**
225 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
226 * @edp_dpcd: The DPCD to check
227 *
228 * Note that currently this function will return %false for panels which support various DPCD
229 * backlight features but which require the brightness be set through PWM, and don't support setting
230 * the brightness level via the DPCD.
231 *
232 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
233 * otherwise
234 */
235 static inline bool
drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])236 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
237 {
238 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
239 }
240
241 /*
242 * DisplayPort AUX channel
243 */
244
245 /**
246 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
247 * @address: address of the (first) register to access
248 * @request: contains the type of transaction (see DP_AUX_* macros)
249 * @reply: upon completion, contains the reply type of the transaction
250 * @buffer: pointer to a transmission or reception buffer
251 * @size: size of @buffer
252 */
253 struct drm_dp_aux_msg {
254 unsigned int address;
255 u8 request;
256 u8 reply;
257 void *buffer;
258 size_t size;
259 };
260
261 struct cec_adapter;
262 struct edid;
263 struct drm_connector;
264
265 /**
266 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
267 * @lock: mutex protecting this struct
268 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
269 * @connector: the connector this CEC adapter is associated with
270 * @unregister_work: unregister the CEC adapter
271 */
272 struct drm_dp_aux_cec {
273 struct mutex lock;
274 struct cec_adapter *adap;
275 struct drm_connector *connector;
276 struct delayed_work unregister_work;
277 };
278
279 /**
280 * struct drm_dp_aux - DisplayPort AUX channel
281 *
282 * An AUX channel can also be used to transport I2C messages to a sink. A
283 * typical application of that is to access an EDID that's present in the sink
284 * device. The @transfer() function can also be used to execute such
285 * transactions. The drm_dp_aux_register() function registers an I2C adapter
286 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
287 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
288 * transfers by default; if a partial response is received, the adapter will
289 * drop down to the size given by the partial response for this transaction
290 * only.
291 */
292 struct drm_dp_aux {
293 /**
294 * @name: user-visible name of this AUX channel and the
295 * I2C-over-AUX adapter.
296 *
297 * It's also used to specify the name of the I2C adapter. If set
298 * to %NULL, dev_name() of @dev will be used.
299 */
300 const char *name;
301
302 /**
303 * @ddc: I2C adapter that can be used for I2C-over-AUX
304 * communication
305 */
306 struct i2c_adapter ddc;
307
308 /**
309 * @dev: pointer to struct device that is the parent for this
310 * AUX channel.
311 */
312 struct device *dev;
313
314 /**
315 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
316 * Beware, this may be %NULL before drm_dp_aux_register() has been
317 * called.
318 *
319 * It should be set to the &drm_device that will be using this AUX
320 * channel as early as possible. For many graphics drivers this should
321 * happen before drm_dp_aux_init(), however it's perfectly fine to set
322 * this field later so long as it's assigned before calling
323 * drm_dp_aux_register().
324 */
325 struct drm_device *drm_dev;
326
327 /**
328 * @crtc: backpointer to the crtc that is currently using this
329 * AUX channel
330 */
331 struct drm_crtc *crtc;
332
333 /**
334 * @hw_mutex: internal mutex used for locking transfers.
335 *
336 * Note that if the underlying hardware is shared among multiple
337 * channels, the driver needs to do additional locking to
338 * prevent concurrent access.
339 */
340 struct mutex hw_mutex;
341
342 /**
343 * @crc_work: worker that captures CRCs for each frame
344 */
345 struct work_struct crc_work;
346
347 /**
348 * @crc_count: counter of captured frame CRCs
349 */
350 u8 crc_count;
351
352 /**
353 * @transfer: transfers a message representing a single AUX
354 * transaction.
355 *
356 * This is a hardware-specific implementation of how
357 * transactions are executed that the drivers must provide.
358 *
359 * A pointer to a &drm_dp_aux_msg structure describing the
360 * transaction is passed into this function. Upon success, the
361 * implementation should return the number of payload bytes that
362 * were transferred, or a negative error-code on failure.
363 *
364 * Helpers will propagate these errors, with the exception of
365 * the %-EBUSY error, which causes a transaction to be retried.
366 * On a short, helpers will return %-EPROTO to make it simpler
367 * to check for failure.
368 *
369 * The @transfer() function must only modify the reply field of
370 * the &drm_dp_aux_msg structure. The retry logic and i2c
371 * helpers assume this is the case.
372 *
373 * Also note that this callback can be called no matter the
374 * state @dev is in and also no matter what state the panel is
375 * in. It's expected:
376 *
377 * - If the @dev providing the AUX bus is currently unpowered then
378 * it will power itself up for the transfer.
379 *
380 * - If we're on eDP (using a drm_panel) and the panel is not in a
381 * state where it can respond (it's not powered or it's in a
382 * low power state) then this function may return an error, but
383 * not crash. It's up to the caller of this code to make sure that
384 * the panel is powered on if getting an error back is not OK. If a
385 * drm_panel driver is initiating a DP AUX transfer it may power
386 * itself up however it wants. All other code should ensure that
387 * the pre_enable() bridge chain (which eventually calls the
388 * drm_panel prepare function) has powered the panel.
389 */
390 ssize_t (*transfer)(struct drm_dp_aux *aux,
391 struct drm_dp_aux_msg *msg);
392
393 /**
394 * @wait_hpd_asserted: wait for HPD to be asserted
395 *
396 * This is mainly useful for eDP panels drivers to wait for an eDP
397 * panel to finish powering on. This is an optional function.
398 *
399 * This function will efficiently wait for the HPD signal to be
400 * asserted. The `wait_us` parameter that is passed in says that we
401 * know that the HPD signal is expected to be asserted within `wait_us`
402 * microseconds. This function could wait for longer than `wait_us` if
403 * the logic in the DP controller has a long debouncing time. The
404 * important thing is that if this function returns success that the
405 * DP controller is ready to send AUX transactions.
406 *
407 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
408 * expired and HPD wasn't asserted. This function should not print
409 * timeout errors to the log.
410 *
411 * The semantics of this function are designed to match the
412 * readx_poll_timeout() function. That means a `wait_us` of 0 means
413 * to wait forever. Like readx_poll_timeout(), this function may sleep.
414 *
415 * NOTE: this function specifically reports the state of the HPD pin
416 * that's associated with the DP AUX channel. This is different from
417 * the HPD concept in much of the rest of DRM which is more about
418 * physical presence of a display. For eDP, for instance, a display is
419 * assumed always present even if the HPD pin is deasserted.
420 */
421 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
422
423 /**
424 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
425 */
426 unsigned i2c_nack_count;
427 /**
428 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
429 */
430 unsigned i2c_defer_count;
431 /**
432 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
433 */
434 struct drm_dp_aux_cec cec;
435 /**
436 * @is_remote: Is this AUX CH actually using sideband messaging.
437 */
438 bool is_remote;
439 };
440
441 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
442 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
443 void *buffer, size_t size);
444 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
445 void *buffer, size_t size);
446
447 /**
448 * drm_dp_dpcd_readb() - read a single byte from the DPCD
449 * @aux: DisplayPort AUX channel
450 * @offset: address of the register to read
451 * @valuep: location where the value of the register will be stored
452 *
453 * Returns the number of bytes transferred (1) on success, or a negative
454 * error code on failure.
455 */
drm_dp_dpcd_readb(struct drm_dp_aux * aux,unsigned int offset,u8 * valuep)456 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
457 unsigned int offset, u8 *valuep)
458 {
459 return drm_dp_dpcd_read(aux, offset, valuep, 1);
460 }
461
462 /**
463 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
464 * @aux: DisplayPort AUX channel
465 * @offset: address of the register to write
466 * @value: value to write to the register
467 *
468 * Returns the number of bytes transferred (1) on success, or a negative
469 * error code on failure.
470 */
drm_dp_dpcd_writeb(struct drm_dp_aux * aux,unsigned int offset,u8 value)471 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
472 unsigned int offset, u8 value)
473 {
474 return drm_dp_dpcd_write(aux, offset, &value, 1);
475 }
476
477 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
478 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
479
480 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
481 u8 status[DP_LINK_STATUS_SIZE]);
482
483 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
484 enum drm_dp_phy dp_phy,
485 u8 link_status[DP_LINK_STATUS_SIZE]);
486
487 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
488 u8 real_edid_checksum);
489
490 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
491 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
492 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
493 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
494 const u8 port_cap[4], u8 type);
495 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
496 const u8 port_cap[4],
497 const struct edid *edid);
498 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
499 const u8 port_cap[4]);
500 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
501 const u8 port_cap[4],
502 const struct edid *edid);
503 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
504 const u8 port_cap[4],
505 const struct edid *edid);
506 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
507 const u8 port_cap[4],
508 const struct edid *edid);
509 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
510 const u8 port_cap[4]);
511 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
512 const u8 port_cap[4]);
513 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
514 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
515 const u8 port_cap[4]);
516 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
517 void drm_dp_downstream_debug(struct seq_file *m,
518 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
519 const u8 port_cap[4],
520 const struct edid *edid,
521 struct drm_dp_aux *aux);
522 enum drm_mode_subconnector
523 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
524 const u8 port_cap[4]);
525 void drm_dp_set_subconnector_property(struct drm_connector *connector,
526 enum drm_connector_status status,
527 const u8 *dpcd,
528 const u8 port_cap[4]);
529
530 struct drm_dp_desc;
531 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
532 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
533 const struct drm_dp_desc *desc);
534 int drm_dp_read_sink_count(struct drm_dp_aux *aux);
535
536 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
537 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
538 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
539 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
540 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
541 enum drm_dp_phy dp_phy,
542 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
543 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
544 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
545 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
546 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
547 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
548
549 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
550 void drm_dp_aux_init(struct drm_dp_aux *aux);
551 int drm_dp_aux_register(struct drm_dp_aux *aux);
552 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
553
554 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
555 int drm_dp_stop_crc(struct drm_dp_aux *aux);
556
557 struct drm_dp_dpcd_ident {
558 u8 oui[3];
559 u8 device_id[6];
560 u8 hw_rev;
561 u8 sw_major_rev;
562 u8 sw_minor_rev;
563 } __packed;
564
565 /**
566 * struct drm_dp_desc - DP branch/sink device descriptor
567 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
568 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
569 */
570 struct drm_dp_desc {
571 struct drm_dp_dpcd_ident ident;
572 u32 quirks;
573 };
574
575 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
576 bool is_branch);
577
578 /**
579 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
580 *
581 * Display Port sink and branch devices in the wild have a variety of bugs, try
582 * to collect them here. The quirks are shared, but it's up to the drivers to
583 * implement workarounds for them.
584 */
585 enum drm_dp_quirk {
586 /**
587 * @DP_DPCD_QUIRK_CONSTANT_N:
588 *
589 * The device requires main link attributes Mvid and Nvid to be limited
590 * to 16 bits. So will give a constant value (0x8000) for compatability.
591 */
592 DP_DPCD_QUIRK_CONSTANT_N,
593 /**
594 * @DP_DPCD_QUIRK_NO_PSR:
595 *
596 * The device does not support PSR even if reports that it supports or
597 * driver still need to implement proper handling for such device.
598 */
599 DP_DPCD_QUIRK_NO_PSR,
600 /**
601 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
602 *
603 * The device does not set SINK_COUNT to a non-zero value.
604 * The driver should ignore SINK_COUNT during detection. Note that
605 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
606 */
607 DP_DPCD_QUIRK_NO_SINK_COUNT,
608 /**
609 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
610 *
611 * The device supports MST DSC despite not supporting Virtual DPCD.
612 * The DSC caps can be read from the physical aux instead.
613 */
614 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
615 /**
616 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
617 *
618 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
619 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
620 */
621 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
622 };
623
624 /**
625 * drm_dp_has_quirk() - does the DP device have a specific quirk
626 * @desc: Device descriptor filled by drm_dp_read_desc()
627 * @quirk: Quirk to query for
628 *
629 * Return true if DP device identified by @desc has @quirk.
630 */
631 static inline bool
drm_dp_has_quirk(const struct drm_dp_desc * desc,enum drm_dp_quirk quirk)632 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
633 {
634 return desc->quirks & BIT(quirk);
635 }
636
637 /**
638 * struct drm_edp_backlight_info - Probed eDP backlight info struct
639 * @pwmgen_bit_count: The pwmgen bit count
640 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
641 * @max: The maximum backlight level that may be set
642 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
643 * @aux_enable: Does the panel support the AUX enable cap?
644 * @aux_set: Does the panel support setting the brightness through AUX?
645 *
646 * This structure contains various data about an eDP backlight, which can be populated by using
647 * drm_edp_backlight_init().
648 */
649 struct drm_edp_backlight_info {
650 u8 pwmgen_bit_count;
651 u8 pwm_freq_pre_divider;
652 u16 max;
653
654 bool lsb_reg_used : 1;
655 bool aux_enable : 1;
656 bool aux_set : 1;
657 };
658
659 int
660 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
661 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
662 u16 *current_level, u8 *current_mode);
663 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
664 u16 level);
665 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
666 u16 level);
667 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
668
669 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
670 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
671
672 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
673
674 #else
675
drm_panel_dp_aux_backlight(struct drm_panel * panel,struct drm_dp_aux * aux)676 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
677 struct drm_dp_aux *aux)
678 {
679 return 0;
680 }
681
682 #endif
683
684 #ifdef CONFIG_DRM_DP_CEC
685 void drm_dp_cec_irq(struct drm_dp_aux *aux);
686 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
687 struct drm_connector *connector);
688 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
689 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
690 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
691 #else
drm_dp_cec_irq(struct drm_dp_aux * aux)692 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
693 {
694 }
695
696 static inline void
drm_dp_cec_register_connector(struct drm_dp_aux * aux,struct drm_connector * connector)697 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
698 struct drm_connector *connector)
699 {
700 }
701
drm_dp_cec_unregister_connector(struct drm_dp_aux * aux)702 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
703 {
704 }
705
drm_dp_cec_set_edid(struct drm_dp_aux * aux,const struct edid * edid)706 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
707 const struct edid *edid)
708 {
709 }
710
drm_dp_cec_unset_edid(struct drm_dp_aux * aux)711 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
712 {
713 }
714
715 #endif
716
717 /**
718 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
719 * @link_rate: Requested Link rate from DPCD 0x219
720 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
721 * @phy_pattern: DP Phy test pattern from DPCD 0x248
722 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
723 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
724 * @enhanced_frame_cap: flag for enhanced frame capability.
725 */
726 struct drm_dp_phy_test_params {
727 int link_rate;
728 u8 num_lanes;
729 u8 phy_pattern;
730 u8 hbr2_reset[2];
731 u8 custom80[10];
732 bool enhanced_frame_cap;
733 };
734
735 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
736 struct drm_dp_phy_test_params *data);
737 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
738 struct drm_dp_phy_test_params *data, u8 dp_rev);
739 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
740 const u8 port_cap[4]);
741 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
742 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
743 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
744 u8 frl_mode);
745 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
746 u8 frl_type);
747 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
748 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
749
750 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
751 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
752 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
753 struct drm_connector *connector);
754 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
755 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
756 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
757 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
758 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
759 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
760 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
761 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
762 const u8 port_cap[4], u8 color_spc);
763 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
764
765 #endif /* _DRM_DP_HELPER_H_ */
766