1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Copyright (C) 2013 Freescale Semiconductor, Inc.
6 //
7 // Based on stmp3xxx_spdif_dai.c
8 // Vladimir Barinov <vbarinov@embeddedalley.com>
9 // Copyright 2008 SigmaTel, Inc
10 // Copyright 2008 Embedded Alley Solutions, Inc
11
12 #include <linux/bitrev.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/regmap.h>
19 #include <linux/pm_runtime.h>
20
21 #include <sound/asoundef.h>
22 #include <sound/dmaengine_pcm.h>
23 #include <sound/soc.h>
24
25 #include "fsl_spdif.h"
26 #include "fsl_utils.h"
27 #include "imx-pcm.h"
28
29 #define FSL_SPDIF_TXFIFO_WML 0x8
30 #define FSL_SPDIF_RXFIFO_WML 0x8
31
32 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
33 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
34 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
35 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
36 INT_LOSS_LOCK | INT_DPLL_LOCKED)
37
38 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
39
40 /* Index list for the values that has if (DPLL Locked) condition */
41 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
42 #define SRPC_NODPLL_START1 0x5
43 #define SRPC_NODPLL_START2 0xc
44
45 #define DEFAULT_RXCLK_SRC 1
46
47 #define RX_SAMPLE_RATE_KCONTROL "RX Sample Rate"
48
49 /**
50 * struct fsl_spdif_soc_data: soc specific data
51 *
52 * @imx: for imx platform
53 * @shared_root_clock: flag of sharing a clock source with others;
54 * so the driver shouldn't set root clock rate
55 * @raw_capture_mode: if raw capture mode support
56 * @cchannel_192b: if there are registers for 192bits C channel data
57 * @interrupts: interrupt number
58 * @tx_burst: tx maxburst size
59 * @rx_burst: rx maxburst size
60 * @tx_formats: tx supported data format
61 */
62 struct fsl_spdif_soc_data {
63 bool imx;
64 bool shared_root_clock;
65 bool raw_capture_mode;
66 bool cchannel_192b;
67 u32 interrupts;
68 u32 tx_burst;
69 u32 rx_burst;
70 u64 tx_formats;
71 };
72
73 /*
74 * SPDIF control structure
75 * Defines channel status, subcode and Q sub
76 */
77 struct spdif_mixer_control {
78 /* spinlock to access control data */
79 spinlock_t ctl_lock;
80
81 /* IEC958 channel tx status bit */
82 unsigned char ch_status[4];
83
84 /* User bits */
85 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
86
87 /* Q subcode part of user bits */
88 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
89
90 /* Buffer offset for U/Q */
91 u32 upos;
92 u32 qpos;
93
94 /* Ready buffer index of the two buffers */
95 u32 ready_buf;
96 };
97
98 /**
99 * struct fsl_spdif_priv - Freescale SPDIF private data
100 * @soc: SPDIF soc data
101 * @fsl_spdif_control: SPDIF control data
102 * @cpu_dai_drv: cpu dai driver
103 * @snd_card: sound card pointer
104 * @rxrate_kcontrol: kcontrol for RX Sample Rate
105 * @pdev: platform device pointer
106 * @regmap: regmap handler
107 * @dpll_locked: dpll lock flag
108 * @txrate: the best rates for playback
109 * @txclk_df: STC_TXCLK_DF dividers value for playback
110 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
111 * @txclk_src: STC_TXCLK_SRC values for playback
112 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
113 * @txclk: tx clock sources for playback
114 * @rxclk: rx clock sources for capture
115 * @coreclk: core clock for register access via DMA
116 * @sysclk: system clock for rx clock rate measurement
117 * @spbaclk: SPBA clock (optional, depending on SoC design)
118 * @dma_params_tx: DMA parameters for transmit channel
119 * @dma_params_rx: DMA parameters for receive channel
120 * @regcache_srpc: regcache for SRPC
121 * @bypass: status of bypass input to output
122 * @pll8k_clk: PLL clock for the rate of multiply of 8kHz
123 * @pll11k_clk: PLL clock for the rate of multiply of 11kHz
124 */
125 struct fsl_spdif_priv {
126 const struct fsl_spdif_soc_data *soc;
127 struct spdif_mixer_control fsl_spdif_control;
128 struct snd_soc_dai_driver cpu_dai_drv;
129 struct snd_card *snd_card;
130 struct snd_kcontrol *rxrate_kcontrol;
131 struct platform_device *pdev;
132 struct regmap *regmap;
133 bool dpll_locked;
134 u32 txrate[SPDIF_TXRATE_MAX];
135 u8 txclk_df[SPDIF_TXRATE_MAX];
136 u16 sysclk_df[SPDIF_TXRATE_MAX];
137 u8 txclk_src[SPDIF_TXRATE_MAX];
138 u8 rxclk_src;
139 struct clk *txclk[STC_TXCLK_SRC_MAX];
140 struct clk *rxclk;
141 struct clk *coreclk;
142 struct clk *sysclk;
143 struct clk *spbaclk;
144 struct snd_dmaengine_dai_dma_data dma_params_tx;
145 struct snd_dmaengine_dai_dma_data dma_params_rx;
146 /* regcache for SRPC */
147 u32 regcache_srpc;
148 bool bypass;
149 struct clk *pll8k_clk;
150 struct clk *pll11k_clk;
151 };
152
153 static struct fsl_spdif_soc_data fsl_spdif_vf610 = {
154 .imx = false,
155 .shared_root_clock = false,
156 .raw_capture_mode = false,
157 .interrupts = 1,
158 .tx_burst = FSL_SPDIF_TXFIFO_WML,
159 .rx_burst = FSL_SPDIF_RXFIFO_WML,
160 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
161 };
162
163 static struct fsl_spdif_soc_data fsl_spdif_imx35 = {
164 .imx = true,
165 .shared_root_clock = false,
166 .raw_capture_mode = false,
167 .interrupts = 1,
168 .tx_burst = FSL_SPDIF_TXFIFO_WML,
169 .rx_burst = FSL_SPDIF_RXFIFO_WML,
170 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
171 };
172
173 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {
174 .imx = true,
175 .shared_root_clock = true,
176 .raw_capture_mode = false,
177 .interrupts = 1,
178 .tx_burst = FSL_SPDIF_TXFIFO_WML,
179 .rx_burst = FSL_SPDIF_RXFIFO_WML,
180 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
181
182 };
183
184 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = {
185 .imx = true,
186 .shared_root_clock = true,
187 .raw_capture_mode = false,
188 .interrupts = 2,
189 .tx_burst = 2, /* Applied for EDMA */
190 .rx_burst = 2, /* Applied for EDMA */
191 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
192 };
193
194 static struct fsl_spdif_soc_data fsl_spdif_imx8mm = {
195 .imx = true,
196 .shared_root_clock = false,
197 .raw_capture_mode = true,
198 .interrupts = 1,
199 .tx_burst = FSL_SPDIF_TXFIFO_WML,
200 .rx_burst = FSL_SPDIF_RXFIFO_WML,
201 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
202 };
203
204 static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
205 .imx = true,
206 .shared_root_clock = true,
207 .raw_capture_mode = false,
208 .interrupts = 1,
209 .tx_burst = 2, /* Applied for EDMA */
210 .rx_burst = 2, /* Applied for EDMA */
211 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
212 .cchannel_192b = true,
213 };
214
215 /* Check if clk is a root clock that does not share clock source with others */
fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv * spdif,int clk)216 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
217 {
218 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;
219 }
220
221 /* DPLL locked and lock loss interrupt handler */
spdif_irq_dpll_lock(struct fsl_spdif_priv * spdif_priv)222 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
223 {
224 struct regmap *regmap = spdif_priv->regmap;
225 struct platform_device *pdev = spdif_priv->pdev;
226 u32 locked;
227
228 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
229 locked &= SRPC_DPLL_LOCKED;
230
231 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
232 locked ? "locked" : "loss lock");
233
234 spdif_priv->dpll_locked = locked ? true : false;
235
236 if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) {
237 snd_ctl_notify(spdif_priv->snd_card,
238 SNDRV_CTL_EVENT_MASK_VALUE,
239 &spdif_priv->rxrate_kcontrol->id);
240 }
241 }
242
243 /* Receiver found illegal symbol interrupt handler */
spdif_irq_sym_error(struct fsl_spdif_priv * spdif_priv)244 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
245 {
246 struct regmap *regmap = spdif_priv->regmap;
247 struct platform_device *pdev = spdif_priv->pdev;
248
249 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
250
251 /* Clear illegal symbol if DPLL unlocked since no audio stream */
252 if (!spdif_priv->dpll_locked)
253 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
254 }
255
256 /* U/Q Channel receive register full */
spdif_irq_uqrx_full(struct fsl_spdif_priv * spdif_priv,char name)257 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
258 {
259 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
260 struct regmap *regmap = spdif_priv->regmap;
261 struct platform_device *pdev = spdif_priv->pdev;
262 u32 *pos, size, val, reg;
263
264 switch (name) {
265 case 'U':
266 pos = &ctrl->upos;
267 size = SPDIF_UBITS_SIZE;
268 reg = REG_SPDIF_SRU;
269 break;
270 case 'Q':
271 pos = &ctrl->qpos;
272 size = SPDIF_QSUB_SIZE;
273 reg = REG_SPDIF_SRQ;
274 break;
275 default:
276 dev_err(&pdev->dev, "unsupported channel name\n");
277 return;
278 }
279
280 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
281
282 if (*pos >= size * 2) {
283 *pos = 0;
284 } else if (unlikely((*pos % size) + 3 > size)) {
285 dev_err(&pdev->dev, "User bit receive buffer overflow\n");
286 return;
287 }
288
289 regmap_read(regmap, reg, &val);
290 ctrl->subcode[*pos++] = val >> 16;
291 ctrl->subcode[*pos++] = val >> 8;
292 ctrl->subcode[*pos++] = val;
293 }
294
295 /* U/Q Channel sync found */
spdif_irq_uq_sync(struct fsl_spdif_priv * spdif_priv)296 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
297 {
298 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
299 struct platform_device *pdev = spdif_priv->pdev;
300
301 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
302
303 /* U/Q buffer reset */
304 if (ctrl->qpos == 0)
305 return;
306
307 /* Set ready to this buffer */
308 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
309 }
310
311 /* U/Q Channel framing error */
spdif_irq_uq_err(struct fsl_spdif_priv * spdif_priv)312 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
313 {
314 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
315 struct regmap *regmap = spdif_priv->regmap;
316 struct platform_device *pdev = spdif_priv->pdev;
317 u32 val;
318
319 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
320
321 /* Read U/Q data to clear the irq and do buffer reset */
322 regmap_read(regmap, REG_SPDIF_SRU, &val);
323 regmap_read(regmap, REG_SPDIF_SRQ, &val);
324
325 /* Drop this U/Q buffer */
326 ctrl->ready_buf = 0;
327 ctrl->upos = 0;
328 ctrl->qpos = 0;
329 }
330
331 /* Get spdif interrupt status and clear the interrupt */
spdif_intr_status_clear(struct fsl_spdif_priv * spdif_priv)332 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
333 {
334 struct regmap *regmap = spdif_priv->regmap;
335 u32 val, val2;
336
337 regmap_read(regmap, REG_SPDIF_SIS, &val);
338 regmap_read(regmap, REG_SPDIF_SIE, &val2);
339
340 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
341
342 return val;
343 }
344
spdif_isr(int irq,void * devid)345 static irqreturn_t spdif_isr(int irq, void *devid)
346 {
347 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
348 struct platform_device *pdev = spdif_priv->pdev;
349 u32 sis;
350
351 sis = spdif_intr_status_clear(spdif_priv);
352
353 if (sis & INT_DPLL_LOCKED)
354 spdif_irq_dpll_lock(spdif_priv);
355
356 if (sis & INT_TXFIFO_UNOV)
357 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
358
359 if (sis & INT_TXFIFO_RESYNC)
360 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
361
362 if (sis & INT_CNEW)
363 dev_dbg(&pdev->dev, "isr: cstatus new\n");
364
365 if (sis & INT_VAL_NOGOOD)
366 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
367
368 if (sis & INT_SYM_ERR)
369 spdif_irq_sym_error(spdif_priv);
370
371 if (sis & INT_BIT_ERR)
372 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
373
374 if (sis & INT_URX_FUL)
375 spdif_irq_uqrx_full(spdif_priv, 'U');
376
377 if (sis & INT_URX_OV)
378 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
379
380 if (sis & INT_QRX_FUL)
381 spdif_irq_uqrx_full(spdif_priv, 'Q');
382
383 if (sis & INT_QRX_OV)
384 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
385
386 if (sis & INT_UQ_SYNC)
387 spdif_irq_uq_sync(spdif_priv);
388
389 if (sis & INT_UQ_ERR)
390 spdif_irq_uq_err(spdif_priv);
391
392 if (sis & INT_RXFIFO_UNOV)
393 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
394
395 if (sis & INT_RXFIFO_RESYNC)
396 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
397
398 if (sis & INT_LOSS_LOCK)
399 spdif_irq_dpll_lock(spdif_priv);
400
401 /* FIXME: Write Tx FIFO to clear TxEm */
402 if (sis & INT_TX_EM)
403 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
404
405 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
406 if (sis & INT_RXFIFO_FUL)
407 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
408
409 return IRQ_HANDLED;
410 }
411
spdif_softreset(struct fsl_spdif_priv * spdif_priv)412 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
413 {
414 struct regmap *regmap = spdif_priv->regmap;
415 u32 val, cycle = 1000;
416
417 regcache_cache_bypass(regmap, true);
418
419 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
420
421 /*
422 * RESET bit would be cleared after finishing its reset procedure,
423 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
424 */
425 do {
426 regmap_read(regmap, REG_SPDIF_SCR, &val);
427 } while ((val & SCR_SOFT_RESET) && cycle--);
428
429 regcache_cache_bypass(regmap, false);
430 regcache_mark_dirty(regmap);
431 regcache_sync(regmap);
432
433 if (cycle)
434 return 0;
435 else
436 return -EBUSY;
437 }
438
spdif_set_cstatus(struct spdif_mixer_control * ctrl,u8 mask,u8 cstatus)439 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
440 u8 mask, u8 cstatus)
441 {
442 ctrl->ch_status[3] &= ~mask;
443 ctrl->ch_status[3] |= cstatus & mask;
444 }
445
spdif_write_channel_status(struct fsl_spdif_priv * spdif_priv)446 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
447 {
448 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
449 struct regmap *regmap = spdif_priv->regmap;
450 struct platform_device *pdev = spdif_priv->pdev;
451 u32 ch_status;
452
453 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
454 (bitrev8(ctrl->ch_status[1]) << 8) |
455 bitrev8(ctrl->ch_status[2]);
456 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
457
458 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
459
460 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
461 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
462
463 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
464
465 if (spdif_priv->soc->cchannel_192b) {
466 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) |
467 (bitrev8(ctrl->ch_status[1]) << 16) |
468 (bitrev8(ctrl->ch_status[2]) << 8) |
469 bitrev8(ctrl->ch_status[3]);
470
471 regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000);
472
473 /*
474 * The first 32bit should be in REG_SPDIF_STCCA_31_0 register,
475 * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP
476 * then can get correct result with HDMI analyzer capture.
477 * There is a hardware bug here.
478 */
479 regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status);
480 }
481 }
482
483 /* Set SPDIF PhaseConfig register for rx clock */
spdif_set_rx_clksrc(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel,int dpll_locked)484 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
485 enum spdif_gainsel gainsel, int dpll_locked)
486 {
487 struct regmap *regmap = spdif_priv->regmap;
488 u8 clksrc = spdif_priv->rxclk_src;
489
490 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
491 return -EINVAL;
492
493 regmap_update_bits(regmap, REG_SPDIF_SRPC,
494 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
495 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
496
497 return 0;
498 }
499
500 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum spdif_txrate index);
501
spdif_set_sample_rate(struct snd_pcm_substream * substream,int sample_rate)502 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
503 int sample_rate)
504 {
505 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
506 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
507 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
508 struct regmap *regmap = spdif_priv->regmap;
509 struct platform_device *pdev = spdif_priv->pdev;
510 unsigned long csfs = 0;
511 u32 stc, mask, rate;
512 u16 sysclk_df;
513 u8 clk, txclk_df;
514 int ret;
515
516 switch (sample_rate) {
517 case 32000:
518 rate = SPDIF_TXRATE_32000;
519 csfs = IEC958_AES3_CON_FS_32000;
520 break;
521 case 44100:
522 rate = SPDIF_TXRATE_44100;
523 csfs = IEC958_AES3_CON_FS_44100;
524 break;
525 case 48000:
526 rate = SPDIF_TXRATE_48000;
527 csfs = IEC958_AES3_CON_FS_48000;
528 break;
529 case 88200:
530 rate = SPDIF_TXRATE_88200;
531 csfs = IEC958_AES3_CON_FS_88200;
532 break;
533 case 96000:
534 rate = SPDIF_TXRATE_96000;
535 csfs = IEC958_AES3_CON_FS_96000;
536 break;
537 case 176400:
538 rate = SPDIF_TXRATE_176400;
539 csfs = IEC958_AES3_CON_FS_176400;
540 break;
541 case 192000:
542 rate = SPDIF_TXRATE_192000;
543 csfs = IEC958_AES3_CON_FS_192000;
544 break;
545 default:
546 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
547 return -EINVAL;
548 }
549
550 ret = fsl_spdif_probe_txclk(spdif_priv, rate);
551 if (ret)
552 return ret;
553
554 clk = spdif_priv->txclk_src[rate];
555 if (clk >= STC_TXCLK_SRC_MAX) {
556 dev_err(&pdev->dev, "tx clock source is out of range\n");
557 return -EINVAL;
558 }
559
560 txclk_df = spdif_priv->txclk_df[rate];
561 if (txclk_df == 0) {
562 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
563 return -EINVAL;
564 }
565
566 sysclk_df = spdif_priv->sysclk_df[rate];
567
568 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))
569 goto clk_set_bypass;
570
571 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
572 ret = clk_set_rate(spdif_priv->txclk[clk],
573 64 * sample_rate * txclk_df);
574 if (ret) {
575 dev_err(&pdev->dev, "failed to set tx clock rate\n");
576 return ret;
577 }
578
579 clk_set_bypass:
580 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
581 (64 * sample_rate * txclk_df * sysclk_df));
582 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
583 clk_get_rate(spdif_priv->txclk[clk]));
584
585 /* set fs field in consumer channel status */
586 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
587
588 /* select clock source and divisor */
589 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
590 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
591 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
592 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
593 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
594
595 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
596 spdif_priv->txrate[rate], sample_rate);
597
598 return 0;
599 }
600
fsl_spdif_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)601 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
602 struct snd_soc_dai *cpu_dai)
603 {
604 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
605 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
606 struct platform_device *pdev = spdif_priv->pdev;
607 struct regmap *regmap = spdif_priv->regmap;
608 u32 scr, mask;
609 int ret;
610
611 /* Reset module and interrupts only for first initialization */
612 if (!snd_soc_dai_active(cpu_dai)) {
613 ret = spdif_softreset(spdif_priv);
614 if (ret) {
615 dev_err(&pdev->dev, "failed to soft reset\n");
616 return ret;
617 }
618
619 /* Disable all the interrupts */
620 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
621 }
622
623 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
624 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
625 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
626 SCR_TXFIFO_FSEL_IF8;
627 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
628 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
629 SCR_TXFIFO_FSEL_MASK;
630 } else {
631 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
632 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
633 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
634 }
635 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
636
637 /* Power up SPDIF module */
638 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
639
640 return 0;
641 }
642
fsl_spdif_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)643 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
644 struct snd_soc_dai *cpu_dai)
645 {
646 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
647 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
648 struct regmap *regmap = spdif_priv->regmap;
649 u32 scr, mask;
650
651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
652 scr = 0;
653 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
654 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
655 SCR_TXFIFO_FSEL_MASK;
656 /* Disable TX clock */
657 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);
658 } else {
659 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
660 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
661 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
662 }
663 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
664
665 /* Power down SPDIF module only if tx&rx are both inactive */
666 if (!snd_soc_dai_active(cpu_dai)) {
667 spdif_intr_status_clear(spdif_priv);
668 regmap_update_bits(regmap, REG_SPDIF_SCR,
669 SCR_LOW_POWER, SCR_LOW_POWER);
670 }
671 }
672
spdif_reparent_rootclk(struct fsl_spdif_priv * spdif_priv,unsigned int sample_rate)673 static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsigned int sample_rate)
674 {
675 struct platform_device *pdev = spdif_priv->pdev;
676 struct clk *clk;
677 int ret;
678
679 /* Reparent clock if required condition is true */
680 if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT))
681 return 0;
682
683 /* Get root clock */
684 clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT];
685
686 /* Disable clock first, for it was enabled by pm_runtime */
687 clk_disable_unprepare(clk);
688 fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk,
689 spdif_priv->pll11k_clk, sample_rate);
690 ret = clk_prepare_enable(clk);
691 if (ret)
692 return ret;
693
694 return 0;
695 }
fsl_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)696 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
697 struct snd_pcm_hw_params *params,
698 struct snd_soc_dai *dai)
699 {
700 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
701 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
702 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
703 struct platform_device *pdev = spdif_priv->pdev;
704 u32 sample_rate = params_rate(params);
705 int ret = 0;
706
707 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
708 ret = spdif_reparent_rootclk(spdif_priv, sample_rate);
709 if (ret) {
710 dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n",
711 __func__, sample_rate);
712 return ret;
713 }
714
715 ret = spdif_set_sample_rate(substream, sample_rate);
716 if (ret) {
717 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
718 __func__, sample_rate);
719 return ret;
720 }
721 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
722 IEC958_AES3_CON_CLOCK_1000PPM);
723 spdif_write_channel_status(spdif_priv);
724 } else {
725 /* Setup rx clock source */
726 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
727 }
728
729 return ret;
730 }
731
fsl_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)732 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
733 int cmd, struct snd_soc_dai *dai)
734 {
735 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
736 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
737 struct regmap *regmap = spdif_priv->regmap;
738 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
739 u32 intr = SIE_INTR_FOR(tx);
740 u32 dmaen = SCR_DMA_xX_EN(tx);
741
742 switch (cmd) {
743 case SNDRV_PCM_TRIGGER_START:
744 case SNDRV_PCM_TRIGGER_RESUME:
745 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
746 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
747 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
748 break;
749 case SNDRV_PCM_TRIGGER_STOP:
750 case SNDRV_PCM_TRIGGER_SUSPEND:
751 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
752 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
753 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
754 regmap_write(regmap, REG_SPDIF_STL, 0x0);
755 regmap_write(regmap, REG_SPDIF_STR, 0x0);
756 break;
757 default:
758 return -EINVAL;
759 }
760
761 return 0;
762 }
763
764 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
765 .startup = fsl_spdif_startup,
766 .hw_params = fsl_spdif_hw_params,
767 .trigger = fsl_spdif_trigger,
768 .shutdown = fsl_spdif_shutdown,
769 };
770
771
772 /*
773 * FSL SPDIF IEC958 controller(mixer) functions
774 *
775 * Channel status get/put control
776 * User bit value get/put control
777 * Valid bit value get control
778 * DPLL lock status get control
779 * User bit sync mode selection control
780 */
781
fsl_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)782 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
783 struct snd_ctl_elem_info *uinfo)
784 {
785 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
786 uinfo->count = 1;
787
788 return 0;
789 }
790
fsl_spdif_pb_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)791 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
792 struct snd_ctl_elem_value *uvalue)
793 {
794 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
795 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
796 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
797
798 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
799 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
800 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
801 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
802
803 return 0;
804 }
805
fsl_spdif_pb_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)806 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
807 struct snd_ctl_elem_value *uvalue)
808 {
809 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
810 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
811 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
812
813 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
814 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
815 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
816 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
817
818 spdif_write_channel_status(spdif_priv);
819
820 return 0;
821 }
822
823 /* Get channel status from SPDIF_RX_CCHAN register */
fsl_spdif_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)824 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
825 struct snd_ctl_elem_value *ucontrol)
826 {
827 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
828 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
829 struct regmap *regmap = spdif_priv->regmap;
830 u32 cstatus, val;
831
832 regmap_read(regmap, REG_SPDIF_SIS, &val);
833 if (!(val & INT_CNEW))
834 return -EAGAIN;
835
836 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
837 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
838 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
839 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
840
841 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
842 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
843 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
844 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
845
846 /* Clear intr */
847 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
848
849 return 0;
850 }
851
852 /*
853 * Get User bits (subcode) from chip value which readed out
854 * in UChannel register.
855 */
fsl_spdif_subcode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)856 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
857 struct snd_ctl_elem_value *ucontrol)
858 {
859 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
860 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
861 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
862 unsigned long flags;
863 int ret = -EAGAIN;
864
865 spin_lock_irqsave(&ctrl->ctl_lock, flags);
866 if (ctrl->ready_buf) {
867 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
868 memcpy(&ucontrol->value.iec958.subcode[0],
869 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
870 ret = 0;
871 }
872 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
873
874 return ret;
875 }
876
877 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
fsl_spdif_qinfo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)878 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
879 struct snd_ctl_elem_info *uinfo)
880 {
881 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
882 uinfo->count = SPDIF_QSUB_SIZE;
883
884 return 0;
885 }
886
887 /* Get Q subcode from chip value which readed out in QChannel register */
fsl_spdif_qget(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)888 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
889 struct snd_ctl_elem_value *ucontrol)
890 {
891 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
892 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
893 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
894 unsigned long flags;
895 int ret = -EAGAIN;
896
897 spin_lock_irqsave(&ctrl->ctl_lock, flags);
898 if (ctrl->ready_buf) {
899 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
900 memcpy(&ucontrol->value.bytes.data[0],
901 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
902 ret = 0;
903 }
904 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
905
906 return ret;
907 }
908
909 /* Get valid good bit from interrupt status register */
fsl_spdif_rx_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)910 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,
911 struct snd_ctl_elem_value *ucontrol)
912 {
913 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
914 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
915 struct regmap *regmap = spdif_priv->regmap;
916 u32 val;
917
918 regmap_read(regmap, REG_SPDIF_SIS, &val);
919 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
920 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
921
922 return 0;
923 }
924
fsl_spdif_tx_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)925 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,
926 struct snd_ctl_elem_value *ucontrol)
927 {
928 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
929 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
930 struct regmap *regmap = spdif_priv->regmap;
931 u32 val;
932
933 regmap_read(regmap, REG_SPDIF_SCR, &val);
934 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;
935 val = 1 - val;
936 ucontrol->value.integer.value[0] = val;
937
938 return 0;
939 }
940
fsl_spdif_tx_vbit_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)941 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,
942 struct snd_ctl_elem_value *ucontrol)
943 {
944 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
945 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
946 struct regmap *regmap = spdif_priv->regmap;
947 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;
948
949 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);
950
951 return 0;
952 }
953
fsl_spdif_rx_rcm_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)954 static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol,
955 struct snd_ctl_elem_value *ucontrol)
956 {
957 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
958 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
959 struct regmap *regmap = spdif_priv->regmap;
960 u32 val;
961
962 regmap_read(regmap, REG_SPDIF_SCR, &val);
963 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0;
964 ucontrol->value.integer.value[0] = val;
965
966 return 0;
967 }
968
fsl_spdif_rx_rcm_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)969 static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol,
970 struct snd_ctl_elem_value *ucontrol)
971 {
972 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
973 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
974 struct regmap *regmap = spdif_priv->regmap;
975 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0);
976
977 if (val)
978 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE;
979 else
980 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE;
981
982 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val);
983
984 return 0;
985 }
986
fsl_spdif_bypass_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)987 static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol,
988 struct snd_ctl_elem_value *ucontrol)
989 {
990 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
991 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);
992
993 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0;
994
995 return 0;
996 }
997
fsl_spdif_bypass_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)998 static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol,
999 struct snd_ctl_elem_value *ucontrol)
1000 {
1001 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1002 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);
1003 struct snd_soc_card *card = dai->component->card;
1004 bool set = (ucontrol->value.integer.value[0] != 0);
1005 struct regmap *regmap = priv->regmap;
1006 struct snd_soc_pcm_runtime *rtd;
1007 u32 scr, mask;
1008 int stream;
1009
1010 rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
1011
1012 if (priv->bypass == set)
1013 return 0; /* nothing to do */
1014
1015 if (snd_soc_dai_active(dai)) {
1016 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n");
1017 return -EBUSY;
1018 }
1019
1020 pm_runtime_get_sync(dai->dev);
1021
1022 if (set) {
1023 /* Disable interrupts */
1024 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
1025
1026 /* Configure BYPASS mode */
1027 scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF;
1028 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK |
1029 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK;
1030 /* Power up SPDIF module */
1031 mask |= SCR_LOW_POWER;
1032 } else {
1033 /* Power down SPDIF module, disable TX */
1034 scr = SCR_LOW_POWER | SCR_TXSEL_OFF;
1035 mask = SCR_LOW_POWER | SCR_TXSEL_MASK;
1036 }
1037
1038 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
1039
1040 /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */
1041 for_each_pcm_streams(stream)
1042 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1);
1043
1044 priv->bypass = set;
1045 pm_runtime_put_sync(dai->dev);
1046
1047 return 0;
1048 }
1049
1050 /* DPLL lock information */
fsl_spdif_rxrate_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1051 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
1052 struct snd_ctl_elem_info *uinfo)
1053 {
1054 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1055 uinfo->count = 1;
1056 uinfo->value.integer.min = 16000;
1057 uinfo->value.integer.max = 192000;
1058
1059 return 0;
1060 }
1061
1062 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
1063 24, 16, 12, 8, 6, 4, 3,
1064 };
1065
1066 /* Get RX data clock rate given the SPDIF bus_clk */
spdif_get_rxclk_rate(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel)1067 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
1068 enum spdif_gainsel gainsel)
1069 {
1070 struct regmap *regmap = spdif_priv->regmap;
1071 struct platform_device *pdev = spdif_priv->pdev;
1072 u64 tmpval64, busclk_freq = 0;
1073 u32 freqmeas, phaseconf;
1074 u8 clksrc;
1075
1076 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
1077 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
1078
1079 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
1080
1081 /* Get bus clock from system */
1082 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
1083 busclk_freq = clk_get_rate(spdif_priv->sysclk);
1084
1085 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
1086 tmpval64 = (u64) busclk_freq * freqmeas;
1087 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
1088 do_div(tmpval64, 128 * 1024);
1089
1090 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
1091 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
1092 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
1093
1094 return (int)tmpval64;
1095 }
1096
1097 /*
1098 * Get DPLL lock or not info from stable interrupt status register.
1099 * User application must use this control to get locked,
1100 * then can do next PCM operation
1101 */
fsl_spdif_rxrate_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1102 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
1103 struct snd_ctl_elem_value *ucontrol)
1104 {
1105 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1106 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
1107 int rate = 0;
1108
1109 if (spdif_priv->dpll_locked)
1110 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
1111
1112 ucontrol->value.integer.value[0] = rate;
1113
1114 return 0;
1115 }
1116
1117 /*
1118 * User bit sync mode:
1119 * 1 CD User channel subcode
1120 * 0 Non-CD data
1121 */
fsl_spdif_usync_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1122 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
1123 struct snd_ctl_elem_value *ucontrol)
1124 {
1125 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1126 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
1127 struct regmap *regmap = spdif_priv->regmap;
1128 u32 val;
1129
1130 regmap_read(regmap, REG_SPDIF_SRCD, &val);
1131 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
1132
1133 return 0;
1134 }
1135
1136 /*
1137 * User bit sync mode:
1138 * 1 CD User channel subcode
1139 * 0 Non-CD data
1140 */
fsl_spdif_usync_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1141 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
1142 struct snd_ctl_elem_value *ucontrol)
1143 {
1144 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1145 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
1146 struct regmap *regmap = spdif_priv->regmap;
1147 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
1148
1149 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
1150
1151 return 0;
1152 }
1153
1154 /* FSL SPDIF IEC958 controller defines */
1155 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
1156 /* Status cchanel controller */
1157 {
1158 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1159 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1160 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1161 SNDRV_CTL_ELEM_ACCESS_WRITE |
1162 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1163 .info = fsl_spdif_info,
1164 .get = fsl_spdif_pb_get,
1165 .put = fsl_spdif_pb_put,
1166 },
1167 {
1168 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1169 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
1170 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1171 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1172 .info = fsl_spdif_info,
1173 .get = fsl_spdif_capture_get,
1174 },
1175 /* User bits controller */
1176 {
1177 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1178 .name = "IEC958 Subcode Capture Default",
1179 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1180 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1181 .info = fsl_spdif_info,
1182 .get = fsl_spdif_subcode_get,
1183 },
1184 {
1185 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1186 .name = "IEC958 Q-subcode Capture Default",
1187 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1188 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1189 .info = fsl_spdif_qinfo,
1190 .get = fsl_spdif_qget,
1191 },
1192 /* Valid bit error controller */
1193 {
1194 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1195 .name = "IEC958 RX V-Bit Errors",
1196 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1197 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1198 .info = snd_ctl_boolean_mono_info,
1199 .get = fsl_spdif_rx_vbit_get,
1200 },
1201 {
1202 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1203 .name = "IEC958 TX V-Bit",
1204 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1205 SNDRV_CTL_ELEM_ACCESS_WRITE |
1206 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1207 .info = snd_ctl_boolean_mono_info,
1208 .get = fsl_spdif_tx_vbit_get,
1209 .put = fsl_spdif_tx_vbit_put,
1210 },
1211 /* DPLL lock info get controller */
1212 {
1213 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1214 .name = RX_SAMPLE_RATE_KCONTROL,
1215 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1216 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1217 .info = fsl_spdif_rxrate_info,
1218 .get = fsl_spdif_rxrate_get,
1219 },
1220 /* RX bypass controller */
1221 {
1222 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1223 .name = "Bypass Mode",
1224 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
1225 .info = snd_ctl_boolean_mono_info,
1226 .get = fsl_spdif_bypass_get,
1227 .put = fsl_spdif_bypass_put,
1228 },
1229 /* User bit sync mode set/get controller */
1230 {
1231 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1232 .name = "IEC958 USyncMode CDText",
1233 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1234 SNDRV_CTL_ELEM_ACCESS_WRITE |
1235 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1236 .info = snd_ctl_boolean_mono_info,
1237 .get = fsl_spdif_usync_get,
1238 .put = fsl_spdif_usync_put,
1239 },
1240 };
1241
1242 static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = {
1243 {
1244 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1245 .name = "IEC958 Raw Capture Mode",
1246 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1247 SNDRV_CTL_ELEM_ACCESS_WRITE |
1248 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1249 .info = snd_ctl_boolean_mono_info,
1250 .get = fsl_spdif_rx_rcm_get,
1251 .put = fsl_spdif_rx_rcm_put,
1252 },
1253 };
1254
fsl_spdif_dai_probe(struct snd_soc_dai * dai)1255 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
1256 {
1257 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
1258
1259 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
1260 &spdif_private->dma_params_rx);
1261
1262 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
1263
1264 if (spdif_private->soc->raw_capture_mode)
1265 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm,
1266 ARRAY_SIZE(fsl_spdif_ctrls_rcm));
1267
1268 spdif_private->snd_card = dai->component->card->snd_card;
1269 spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card,
1270 RX_SAMPLE_RATE_KCONTROL);
1271 if (!spdif_private->rxrate_kcontrol)
1272 dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n",
1273 RX_SAMPLE_RATE_KCONTROL);
1274
1275 /*Clear the val bit for Tx*/
1276 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,
1277 SCR_VAL_MASK, SCR_VAL_CLEAR);
1278
1279 return 0;
1280 }
1281
1282 static struct snd_soc_dai_driver fsl_spdif_dai = {
1283 .probe = &fsl_spdif_dai_probe,
1284 .playback = {
1285 .stream_name = "CPU-Playback",
1286 .channels_min = 2,
1287 .channels_max = 2,
1288 .rates = FSL_SPDIF_RATES_PLAYBACK,
1289 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
1290 },
1291 .capture = {
1292 .stream_name = "CPU-Capture",
1293 .channels_min = 2,
1294 .channels_max = 2,
1295 .rates = FSL_SPDIF_RATES_CAPTURE,
1296 .formats = FSL_SPDIF_FORMATS_CAPTURE,
1297 },
1298 .ops = &fsl_spdif_dai_ops,
1299 };
1300
1301 static const struct snd_soc_component_driver fsl_spdif_component = {
1302 .name = "fsl-spdif",
1303 .legacy_dai_naming = 1,
1304 };
1305
1306 /* FSL SPDIF REGMAP */
1307 static const struct reg_default fsl_spdif_reg_defaults[] = {
1308 {REG_SPDIF_SCR, 0x00000400},
1309 {REG_SPDIF_SRCD, 0x00000000},
1310 {REG_SPDIF_SIE, 0x00000000},
1311 {REG_SPDIF_STL, 0x00000000},
1312 {REG_SPDIF_STR, 0x00000000},
1313 {REG_SPDIF_STCSCH, 0x00000000},
1314 {REG_SPDIF_STCSCL, 0x00000000},
1315 {REG_SPDIF_STCSPH, 0x00000000},
1316 {REG_SPDIF_STCSPL, 0x00000000},
1317 {REG_SPDIF_STC, 0x00020f00},
1318 };
1319
fsl_spdif_readable_reg(struct device * dev,unsigned int reg)1320 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1321 {
1322 switch (reg) {
1323 case REG_SPDIF_SCR:
1324 case REG_SPDIF_SRCD:
1325 case REG_SPDIF_SRPC:
1326 case REG_SPDIF_SIE:
1327 case REG_SPDIF_SIS:
1328 case REG_SPDIF_SRL:
1329 case REG_SPDIF_SRR:
1330 case REG_SPDIF_SRCSH:
1331 case REG_SPDIF_SRCSL:
1332 case REG_SPDIF_SRU:
1333 case REG_SPDIF_SRQ:
1334 case REG_SPDIF_STCSCH:
1335 case REG_SPDIF_STCSCL:
1336 case REG_SPDIF_STCSPH:
1337 case REG_SPDIF_STCSPL:
1338 case REG_SPDIF_SRFM:
1339 case REG_SPDIF_STC:
1340 case REG_SPDIF_SRCCA_31_0:
1341 case REG_SPDIF_SRCCA_63_32:
1342 case REG_SPDIF_SRCCA_95_64:
1343 case REG_SPDIF_SRCCA_127_96:
1344 case REG_SPDIF_SRCCA_159_128:
1345 case REG_SPDIF_SRCCA_191_160:
1346 case REG_SPDIF_STCCA_31_0:
1347 case REG_SPDIF_STCCA_63_32:
1348 case REG_SPDIF_STCCA_95_64:
1349 case REG_SPDIF_STCCA_127_96:
1350 case REG_SPDIF_STCCA_159_128:
1351 case REG_SPDIF_STCCA_191_160:
1352 return true;
1353 default:
1354 return false;
1355 }
1356 }
1357
fsl_spdif_volatile_reg(struct device * dev,unsigned int reg)1358 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1359 {
1360 switch (reg) {
1361 case REG_SPDIF_SRPC:
1362 case REG_SPDIF_SIS:
1363 case REG_SPDIF_SRL:
1364 case REG_SPDIF_SRR:
1365 case REG_SPDIF_SRCSH:
1366 case REG_SPDIF_SRCSL:
1367 case REG_SPDIF_SRU:
1368 case REG_SPDIF_SRQ:
1369 case REG_SPDIF_SRFM:
1370 case REG_SPDIF_SRCCA_31_0:
1371 case REG_SPDIF_SRCCA_63_32:
1372 case REG_SPDIF_SRCCA_95_64:
1373 case REG_SPDIF_SRCCA_127_96:
1374 case REG_SPDIF_SRCCA_159_128:
1375 case REG_SPDIF_SRCCA_191_160:
1376 return true;
1377 default:
1378 return false;
1379 }
1380 }
1381
fsl_spdif_writeable_reg(struct device * dev,unsigned int reg)1382 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1383 {
1384 switch (reg) {
1385 case REG_SPDIF_SCR:
1386 case REG_SPDIF_SRCD:
1387 case REG_SPDIF_SRPC:
1388 case REG_SPDIF_SIE:
1389 case REG_SPDIF_SIC:
1390 case REG_SPDIF_STL:
1391 case REG_SPDIF_STR:
1392 case REG_SPDIF_STCSCH:
1393 case REG_SPDIF_STCSCL:
1394 case REG_SPDIF_STCSPH:
1395 case REG_SPDIF_STCSPL:
1396 case REG_SPDIF_STC:
1397 case REG_SPDIF_STCCA_31_0:
1398 case REG_SPDIF_STCCA_63_32:
1399 case REG_SPDIF_STCCA_95_64:
1400 case REG_SPDIF_STCCA_127_96:
1401 case REG_SPDIF_STCCA_159_128:
1402 case REG_SPDIF_STCCA_191_160:
1403 return true;
1404 default:
1405 return false;
1406 }
1407 }
1408
1409 static const struct regmap_config fsl_spdif_regmap_config = {
1410 .reg_bits = 32,
1411 .reg_stride = 4,
1412 .val_bits = 32,
1413
1414 .max_register = REG_SPDIF_STCCA_191_160,
1415 .reg_defaults = fsl_spdif_reg_defaults,
1416 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1417 .readable_reg = fsl_spdif_readable_reg,
1418 .volatile_reg = fsl_spdif_volatile_reg,
1419 .writeable_reg = fsl_spdif_writeable_reg,
1420 .cache_type = REGCACHE_FLAT,
1421 };
1422
fsl_spdif_txclk_caldiv(struct fsl_spdif_priv * spdif_priv,struct clk * clk,u64 savesub,enum spdif_txrate index,bool round)1423 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1424 struct clk *clk, u64 savesub,
1425 enum spdif_txrate index, bool round)
1426 {
1427 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
1428 192000, };
1429 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1430 u64 rate_ideal, rate_actual, sub;
1431 u32 arate;
1432 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
1433 u8 txclk_df;
1434
1435 /* The sysclk has an extra divisor [2, 512] */
1436 sysclk_dfmin = is_sysclk ? 2 : 1;
1437 sysclk_dfmax = is_sysclk ? 512 : 1;
1438
1439 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1440 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1441 rate_ideal = rate[index] * txclk_df * 64ULL;
1442 if (round)
1443 rate_actual = clk_round_rate(clk, rate_ideal);
1444 else
1445 rate_actual = clk_get_rate(clk);
1446
1447 arate = rate_actual / 64;
1448 arate /= txclk_df * sysclk_df;
1449
1450 if (arate == rate[index]) {
1451 /* We are lucky */
1452 savesub = 0;
1453 spdif_priv->txclk_df[index] = txclk_df;
1454 spdif_priv->sysclk_df[index] = sysclk_df;
1455 spdif_priv->txrate[index] = arate;
1456 goto out;
1457 } else if (arate / rate[index] == 1) {
1458 /* A little bigger than expect */
1459 sub = (u64)(arate - rate[index]) * 100000;
1460 do_div(sub, rate[index]);
1461 if (sub >= savesub)
1462 continue;
1463 savesub = sub;
1464 spdif_priv->txclk_df[index] = txclk_df;
1465 spdif_priv->sysclk_df[index] = sysclk_df;
1466 spdif_priv->txrate[index] = arate;
1467 } else if (rate[index] / arate == 1) {
1468 /* A little smaller than expect */
1469 sub = (u64)(rate[index] - arate) * 100000;
1470 do_div(sub, rate[index]);
1471 if (sub >= savesub)
1472 continue;
1473 savesub = sub;
1474 spdif_priv->txclk_df[index] = txclk_df;
1475 spdif_priv->sysclk_df[index] = sysclk_df;
1476 spdif_priv->txrate[index] = arate;
1477 }
1478 }
1479 }
1480
1481 out:
1482 return savesub;
1483 }
1484
fsl_spdif_probe_txclk(struct fsl_spdif_priv * spdif_priv,enum spdif_txrate index)1485 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1486 enum spdif_txrate index)
1487 {
1488 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
1489 192000, };
1490 struct platform_device *pdev = spdif_priv->pdev;
1491 struct device *dev = &pdev->dev;
1492 u64 savesub = 100000, ret;
1493 struct clk *clk;
1494 int i;
1495
1496 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1497 clk = spdif_priv->txclk[i];
1498 if (IS_ERR(clk)) {
1499 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1500 return PTR_ERR(clk);
1501 }
1502 if (!clk_get_rate(clk))
1503 continue;
1504
1505 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1506 fsl_spdif_can_set_clk_rate(spdif_priv, i));
1507 if (savesub == ret)
1508 continue;
1509
1510 savesub = ret;
1511 spdif_priv->txclk_src[index] = i;
1512
1513 /* To quick catch a divisor, we allow a 0.1% deviation */
1514 if (savesub < 100)
1515 break;
1516 }
1517
1518 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1519 spdif_priv->txclk_src[index], rate[index]);
1520 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n",
1521 spdif_priv->txclk_df[index], rate[index]);
1522 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk))
1523 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n",
1524 spdif_priv->sysclk_df[index], rate[index]);
1525 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n",
1526 rate[index], spdif_priv->txrate[index]);
1527
1528 return 0;
1529 }
1530
fsl_spdif_probe(struct platform_device * pdev)1531 static int fsl_spdif_probe(struct platform_device *pdev)
1532 {
1533 struct fsl_spdif_priv *spdif_priv;
1534 struct spdif_mixer_control *ctrl;
1535 struct resource *res;
1536 void __iomem *regs;
1537 int irq, ret, i;
1538 char tmp[16];
1539
1540 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1541 if (!spdif_priv)
1542 return -ENOMEM;
1543
1544 spdif_priv->pdev = pdev;
1545
1546 spdif_priv->soc = of_device_get_match_data(&pdev->dev);
1547
1548 /* Initialize this copy of the CPU DAI driver structure */
1549 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1550 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1551 spdif_priv->cpu_dai_drv.playback.formats =
1552 spdif_priv->soc->tx_formats;
1553
1554 /* Get the addresses and IRQ */
1555 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1556 if (IS_ERR(regs))
1557 return PTR_ERR(regs);
1558
1559 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config);
1560 if (IS_ERR(spdif_priv->regmap)) {
1561 dev_err(&pdev->dev, "regmap init failed\n");
1562 return PTR_ERR(spdif_priv->regmap);
1563 }
1564
1565 for (i = 0; i < spdif_priv->soc->interrupts; i++) {
1566 irq = platform_get_irq(pdev, i);
1567 if (irq < 0)
1568 return irq;
1569
1570 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1571 dev_name(&pdev->dev), spdif_priv);
1572 if (ret) {
1573 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1574 return ret;
1575 }
1576 }
1577
1578 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1579 sprintf(tmp, "rxtx%d", i);
1580 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp);
1581 if (IS_ERR(spdif_priv->txclk[i])) {
1582 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i);
1583 return PTR_ERR(spdif_priv->txclk[i]);
1584 }
1585 }
1586
1587 /* Get system clock for rx clock rate calculation */
1588 spdif_priv->sysclk = spdif_priv->txclk[5];
1589 if (IS_ERR(spdif_priv->sysclk)) {
1590 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1591 return PTR_ERR(spdif_priv->sysclk);
1592 }
1593
1594 /* Get core clock for data register access via DMA */
1595 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1596 if (IS_ERR(spdif_priv->coreclk)) {
1597 dev_err(&pdev->dev, "no core clock in devicetree\n");
1598 return PTR_ERR(spdif_priv->coreclk);
1599 }
1600
1601 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1602 if (IS_ERR(spdif_priv->spbaclk))
1603 dev_warn(&pdev->dev, "no spba clock in devicetree\n");
1604
1605 /* Select clock source for rx/tx clock */
1606 spdif_priv->rxclk = spdif_priv->txclk[1];
1607 if (IS_ERR(spdif_priv->rxclk)) {
1608 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1609 return PTR_ERR(spdif_priv->rxclk);
1610 }
1611 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1612
1613 fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk,
1614 &spdif_priv->pll11k_clk);
1615
1616 /* Initial spinlock for control data */
1617 ctrl = &spdif_priv->fsl_spdif_control;
1618 spin_lock_init(&ctrl->ctl_lock);
1619
1620 /* Init tx channel status default value */
1621 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1622 IEC958_AES0_CON_EMPHASIS_5015;
1623 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1624 ctrl->ch_status[2] = 0x00;
1625 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1626 IEC958_AES3_CON_CLOCK_1000PPM;
1627
1628 spdif_priv->dpll_locked = false;
1629
1630 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst;
1631 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst;
1632 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1633 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1634
1635 /* Register with ASoC */
1636 dev_set_drvdata(&pdev->dev, spdif_priv);
1637 pm_runtime_enable(&pdev->dev);
1638 regcache_cache_only(spdif_priv->regmap, true);
1639
1640 /*
1641 * Register platform component before registering cpu dai for there
1642 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1643 */
1644 ret = imx_pcm_dma_init(pdev);
1645 if (ret) {
1646 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
1647 goto err_pm_disable;
1648 }
1649
1650 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1651 &spdif_priv->cpu_dai_drv, 1);
1652 if (ret) {
1653 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1654 goto err_pm_disable;
1655 }
1656
1657 return ret;
1658
1659 err_pm_disable:
1660 pm_runtime_disable(&pdev->dev);
1661 return ret;
1662 }
1663
fsl_spdif_remove(struct platform_device * pdev)1664 static int fsl_spdif_remove(struct platform_device *pdev)
1665 {
1666 pm_runtime_disable(&pdev->dev);
1667
1668 return 0;
1669 }
1670
1671 #ifdef CONFIG_PM
fsl_spdif_runtime_suspend(struct device * dev)1672 static int fsl_spdif_runtime_suspend(struct device *dev)
1673 {
1674 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1675 int i;
1676
1677 /* Disable all the interrupts */
1678 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);
1679
1680 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1681 &spdif_priv->regcache_srpc);
1682 regcache_cache_only(spdif_priv->regmap, true);
1683
1684 for (i = 0; i < STC_TXCLK_SRC_MAX; i++)
1685 clk_disable_unprepare(spdif_priv->txclk[i]);
1686
1687 if (!IS_ERR(spdif_priv->spbaclk))
1688 clk_disable_unprepare(spdif_priv->spbaclk);
1689 clk_disable_unprepare(spdif_priv->coreclk);
1690
1691 return 0;
1692 }
1693
fsl_spdif_runtime_resume(struct device * dev)1694 static int fsl_spdif_runtime_resume(struct device *dev)
1695 {
1696 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1697 int ret;
1698 int i;
1699
1700 ret = clk_prepare_enable(spdif_priv->coreclk);
1701 if (ret) {
1702 dev_err(dev, "failed to enable core clock\n");
1703 return ret;
1704 }
1705
1706 if (!IS_ERR(spdif_priv->spbaclk)) {
1707 ret = clk_prepare_enable(spdif_priv->spbaclk);
1708 if (ret) {
1709 dev_err(dev, "failed to enable spba clock\n");
1710 goto disable_core_clk;
1711 }
1712 }
1713
1714 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1715 ret = clk_prepare_enable(spdif_priv->txclk[i]);
1716 if (ret)
1717 goto disable_tx_clk;
1718 }
1719
1720 regcache_cache_only(spdif_priv->regmap, false);
1721 regcache_mark_dirty(spdif_priv->regmap);
1722
1723 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1724 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1725 spdif_priv->regcache_srpc);
1726
1727 ret = regcache_sync(spdif_priv->regmap);
1728 if (ret)
1729 goto disable_tx_clk;
1730
1731 return 0;
1732
1733 disable_tx_clk:
1734 for (i--; i >= 0; i--)
1735 clk_disable_unprepare(spdif_priv->txclk[i]);
1736 if (!IS_ERR(spdif_priv->spbaclk))
1737 clk_disable_unprepare(spdif_priv->spbaclk);
1738 disable_core_clk:
1739 clk_disable_unprepare(spdif_priv->coreclk);
1740
1741 return ret;
1742 }
1743 #endif /* CONFIG_PM */
1744
1745 static const struct dev_pm_ops fsl_spdif_pm = {
1746 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1747 pm_runtime_force_resume)
1748 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,
1749 NULL)
1750 };
1751
1752 static const struct of_device_id fsl_spdif_dt_ids[] = {
1753 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1754 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1755 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1756 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
1757 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
1758 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },
1759 {}
1760 };
1761 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1762
1763 static struct platform_driver fsl_spdif_driver = {
1764 .driver = {
1765 .name = "fsl-spdif-dai",
1766 .of_match_table = fsl_spdif_dt_ids,
1767 .pm = &fsl_spdif_pm,
1768 },
1769 .probe = fsl_spdif_probe,
1770 .remove = fsl_spdif_remove,
1771 };
1772
1773 module_platform_driver(fsl_spdif_driver);
1774
1775 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1776 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1777 MODULE_LICENSE("GPL v2");
1778 MODULE_ALIAS("platform:fsl-spdif-dai");
1779