1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 */
5
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16
17 #include <linux/dma-mapping.h>
18
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/initval.h>
24 #include <sound/dmaengine_pcm.h>
25
26 #include "jz4740-i2s.h"
27
28 #define JZ_REG_AIC_CONF 0x00
29 #define JZ_REG_AIC_CTRL 0x04
30 #define JZ_REG_AIC_I2S_FMT 0x10
31 #define JZ_REG_AIC_FIFO_STATUS 0x14
32 #define JZ_REG_AIC_I2S_STATUS 0x1c
33 #define JZ_REG_AIC_CLK_DIV 0x30
34 #define JZ_REG_AIC_FIFO 0x34
35
36 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
37 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
38 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
39 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
40 #define JZ_AIC_CONF_I2S BIT(4)
41 #define JZ_AIC_CONF_RESET BIT(3)
42 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
43 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
44 #define JZ_AIC_CONF_ENABLE BIT(0)
45
46 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
47 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
48 #define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24
49 #define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16
50
51 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
52 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
53 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
54 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
55 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
56 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
57 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
58 #define JZ_AIC_CTRL_TFLUSH BIT(8)
59 #define JZ_AIC_CTRL_RFLUSH BIT(7)
60 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
61 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
62 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
63 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
64 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
65 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
66 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
67
68 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
69 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
70
71 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
72 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
73 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
74 #define JZ_AIC_I2S_FMT_MSB BIT(0)
75
76 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
77
78 #define JZ_AIC_CLK_DIV_MASK 0xf
79 #define I2SDIV_DV_SHIFT 0
80 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
81 #define I2SDIV_IDV_SHIFT 8
82 #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)
83
84 enum jz47xx_i2s_version {
85 JZ_I2S_JZ4740,
86 JZ_I2S_JZ4760,
87 JZ_I2S_JZ4770,
88 JZ_I2S_JZ4780,
89 };
90
91 struct i2s_soc_info {
92 enum jz47xx_i2s_version version;
93 struct snd_soc_dai_driver *dai;
94
95 bool shared_fifo_flush;
96 };
97
98 struct jz4740_i2s {
99 void __iomem *base;
100
101 struct clk *clk_aic;
102 struct clk *clk_i2s;
103
104 struct snd_dmaengine_dai_dma_data playback_dma_data;
105 struct snd_dmaengine_dai_dma_data capture_dma_data;
106
107 const struct i2s_soc_info *soc_info;
108 };
109
jz4740_i2s_read(const struct jz4740_i2s * i2s,unsigned int reg)110 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
111 unsigned int reg)
112 {
113 return readl(i2s->base + reg);
114 }
115
jz4740_i2s_write(const struct jz4740_i2s * i2s,unsigned int reg,uint32_t value)116 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
117 unsigned int reg, uint32_t value)
118 {
119 writel(value, i2s->base + reg);
120 }
121
jz4740_i2s_set_bits(const struct jz4740_i2s * i2s,unsigned int reg,uint32_t bits)122 static inline void jz4740_i2s_set_bits(const struct jz4740_i2s *i2s,
123 unsigned int reg, uint32_t bits)
124 {
125 uint32_t value = jz4740_i2s_read(i2s, reg);
126 value |= bits;
127 jz4740_i2s_write(i2s, reg, value);
128 }
129
jz4740_i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)130 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
131 struct snd_soc_dai *dai)
132 {
133 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
134 uint32_t conf;
135 int ret;
136
137 /*
138 * When we can flush FIFOs independently, only flush the FIFO
139 * that is starting up. We can do this when the DAI is active
140 * because it does not disturb other active substreams.
141 */
142 if (!i2s->soc_info->shared_fifo_flush) {
143 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
144 jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH);
145 else
146 jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH);
147 }
148
149 if (snd_soc_dai_active(dai))
150 return 0;
151
152 /*
153 * When there is a shared flush bit for both FIFOs, the TFLUSH
154 * bit flushes both FIFOs. Flushing while the DAI is active would
155 * cause FIFO underruns in other active substreams so we have to
156 * guard this behind the snd_soc_dai_active() check.
157 */
158 if (i2s->soc_info->shared_fifo_flush)
159 jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH);
160
161 ret = clk_prepare_enable(i2s->clk_i2s);
162 if (ret)
163 return ret;
164
165 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
166 conf |= JZ_AIC_CONF_ENABLE;
167 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
168
169 return 0;
170 }
171
jz4740_i2s_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)172 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
173 struct snd_soc_dai *dai)
174 {
175 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
176 uint32_t conf;
177
178 if (snd_soc_dai_active(dai))
179 return;
180
181 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
182 conf &= ~JZ_AIC_CONF_ENABLE;
183 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
184
185 clk_disable_unprepare(i2s->clk_i2s);
186 }
187
jz4740_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)188 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
189 struct snd_soc_dai *dai)
190 {
191 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
192
193 uint32_t ctrl;
194 uint32_t mask;
195
196 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
197 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
198 else
199 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
200
201 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
202
203 switch (cmd) {
204 case SNDRV_PCM_TRIGGER_START:
205 case SNDRV_PCM_TRIGGER_RESUME:
206 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
207 ctrl |= mask;
208 break;
209 case SNDRV_PCM_TRIGGER_STOP:
210 case SNDRV_PCM_TRIGGER_SUSPEND:
211 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
212 ctrl &= ~mask;
213 break;
214 default:
215 return -EINVAL;
216 }
217
218 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
219
220 return 0;
221 }
222
jz4740_i2s_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)223 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
224 {
225 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
226
227 uint32_t format = 0;
228 uint32_t conf;
229
230 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
231
232 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
233
234 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
235 case SND_SOC_DAIFMT_BP_FP:
236 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
237 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
238 break;
239 case SND_SOC_DAIFMT_BC_FP:
240 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
241 break;
242 case SND_SOC_DAIFMT_BP_FC:
243 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
244 break;
245 case SND_SOC_DAIFMT_BC_FC:
246 break;
247 default:
248 return -EINVAL;
249 }
250
251 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
252 case SND_SOC_DAIFMT_MSB:
253 format |= JZ_AIC_I2S_FMT_MSB;
254 break;
255 case SND_SOC_DAIFMT_I2S:
256 break;
257 default:
258 return -EINVAL;
259 }
260
261 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
262 case SND_SOC_DAIFMT_NB_NF:
263 break;
264 default:
265 return -EINVAL;
266 }
267
268 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
269 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
270
271 return 0;
272 }
273
jz4740_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)274 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
275 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
276 {
277 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
278 unsigned int sample_size;
279 uint32_t ctrl, div_reg;
280 int div;
281
282 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
283
284 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
285 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
286
287 switch (params_format(params)) {
288 case SNDRV_PCM_FORMAT_S8:
289 sample_size = 0;
290 break;
291 case SNDRV_PCM_FORMAT_S16:
292 sample_size = 1;
293 break;
294 default:
295 return -EINVAL;
296 }
297
298 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
299 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
300 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
301 if (params_channels(params) == 1)
302 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
303 else
304 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
305
306 div_reg &= ~I2SDIV_DV_MASK;
307 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
308 } else {
309 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
310 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
311
312 if (i2s->soc_info->version >= JZ_I2S_JZ4770) {
313 div_reg &= ~I2SDIV_IDV_MASK;
314 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT;
315 } else {
316 div_reg &= ~I2SDIV_DV_MASK;
317 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
318 }
319 }
320
321 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
322 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
323
324 return 0;
325 }
326
jz4740_i2s_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)327 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
328 unsigned int freq, int dir)
329 {
330 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
331 struct clk *parent;
332 int ret = 0;
333
334 switch (clk_id) {
335 case JZ4740_I2S_CLKSRC_EXT:
336 parent = clk_get(NULL, "ext");
337 if (IS_ERR(parent))
338 return PTR_ERR(parent);
339 clk_set_parent(i2s->clk_i2s, parent);
340 break;
341 case JZ4740_I2S_CLKSRC_PLL:
342 parent = clk_get(NULL, "pll half");
343 if (IS_ERR(parent))
344 return PTR_ERR(parent);
345 clk_set_parent(i2s->clk_i2s, parent);
346 ret = clk_set_rate(i2s->clk_i2s, freq);
347 break;
348 default:
349 return -EINVAL;
350 }
351 clk_put(parent);
352
353 return ret;
354 }
355
jz4740_i2s_suspend(struct snd_soc_component * component)356 static int jz4740_i2s_suspend(struct snd_soc_component *component)
357 {
358 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
359 uint32_t conf;
360
361 if (snd_soc_component_active(component)) {
362 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
363 conf &= ~JZ_AIC_CONF_ENABLE;
364 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
365
366 clk_disable_unprepare(i2s->clk_i2s);
367 }
368
369 clk_disable_unprepare(i2s->clk_aic);
370
371 return 0;
372 }
373
jz4740_i2s_resume(struct snd_soc_component * component)374 static int jz4740_i2s_resume(struct snd_soc_component *component)
375 {
376 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
377 uint32_t conf;
378 int ret;
379
380 ret = clk_prepare_enable(i2s->clk_aic);
381 if (ret)
382 return ret;
383
384 if (snd_soc_component_active(component)) {
385 ret = clk_prepare_enable(i2s->clk_i2s);
386 if (ret) {
387 clk_disable_unprepare(i2s->clk_aic);
388 return ret;
389 }
390
391 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
392 conf |= JZ_AIC_CONF_ENABLE;
393 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
394 }
395
396 return 0;
397 }
398
jz4740_i2s_dai_probe(struct snd_soc_dai * dai)399 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
400 {
401 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
402 uint32_t conf;
403 int ret;
404
405 ret = clk_prepare_enable(i2s->clk_aic);
406 if (ret)
407 return ret;
408
409 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
410 &i2s->capture_dma_data);
411
412 if (i2s->soc_info->version >= JZ_I2S_JZ4760) {
413 conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
414 (8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
415 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
416 JZ_AIC_CONF_I2S |
417 JZ_AIC_CONF_INTERNAL_CODEC;
418 } else {
419 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
420 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
421 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
422 JZ_AIC_CONF_I2S |
423 JZ_AIC_CONF_INTERNAL_CODEC;
424 }
425
426 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
427 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
428
429 return 0;
430 }
431
jz4740_i2s_dai_remove(struct snd_soc_dai * dai)432 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
433 {
434 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
435
436 clk_disable_unprepare(i2s->clk_aic);
437 return 0;
438 }
439
440 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
441 .startup = jz4740_i2s_startup,
442 .shutdown = jz4740_i2s_shutdown,
443 .trigger = jz4740_i2s_trigger,
444 .hw_params = jz4740_i2s_hw_params,
445 .set_fmt = jz4740_i2s_set_fmt,
446 .set_sysclk = jz4740_i2s_set_sysclk,
447 };
448
449 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
450 SNDRV_PCM_FMTBIT_S16_LE)
451
452 static struct snd_soc_dai_driver jz4740_i2s_dai = {
453 .probe = jz4740_i2s_dai_probe,
454 .remove = jz4740_i2s_dai_remove,
455 .playback = {
456 .channels_min = 1,
457 .channels_max = 2,
458 .rates = SNDRV_PCM_RATE_8000_48000,
459 .formats = JZ4740_I2S_FMTS,
460 },
461 .capture = {
462 .channels_min = 2,
463 .channels_max = 2,
464 .rates = SNDRV_PCM_RATE_8000_48000,
465 .formats = JZ4740_I2S_FMTS,
466 },
467 .symmetric_rate = 1,
468 .ops = &jz4740_i2s_dai_ops,
469 };
470
471 static const struct i2s_soc_info jz4740_i2s_soc_info = {
472 .version = JZ_I2S_JZ4740,
473 .dai = &jz4740_i2s_dai,
474 .shared_fifo_flush = true,
475 };
476
477 static const struct i2s_soc_info jz4760_i2s_soc_info = {
478 .version = JZ_I2S_JZ4760,
479 .dai = &jz4740_i2s_dai,
480 };
481
482 static struct snd_soc_dai_driver jz4770_i2s_dai = {
483 .probe = jz4740_i2s_dai_probe,
484 .remove = jz4740_i2s_dai_remove,
485 .playback = {
486 .channels_min = 1,
487 .channels_max = 2,
488 .rates = SNDRV_PCM_RATE_8000_48000,
489 .formats = JZ4740_I2S_FMTS,
490 },
491 .capture = {
492 .channels_min = 2,
493 .channels_max = 2,
494 .rates = SNDRV_PCM_RATE_8000_48000,
495 .formats = JZ4740_I2S_FMTS,
496 },
497 .ops = &jz4740_i2s_dai_ops,
498 };
499
500 static const struct i2s_soc_info jz4770_i2s_soc_info = {
501 .version = JZ_I2S_JZ4770,
502 .dai = &jz4770_i2s_dai,
503 };
504
505 static const struct i2s_soc_info jz4780_i2s_soc_info = {
506 .version = JZ_I2S_JZ4780,
507 .dai = &jz4770_i2s_dai,
508 };
509
510 static const struct snd_soc_component_driver jz4740_i2s_component = {
511 .name = "jz4740-i2s",
512 .suspend = jz4740_i2s_suspend,
513 .resume = jz4740_i2s_resume,
514 .legacy_dai_naming = 1,
515 };
516
517 static const struct of_device_id jz4740_of_matches[] = {
518 { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info },
519 { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info },
520 { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info },
521 { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info },
522 { /* sentinel */ }
523 };
524 MODULE_DEVICE_TABLE(of, jz4740_of_matches);
525
jz4740_i2s_dev_probe(struct platform_device * pdev)526 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
527 {
528 struct device *dev = &pdev->dev;
529 struct jz4740_i2s *i2s;
530 struct resource *mem;
531 int ret;
532
533 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
534 if (!i2s)
535 return -ENOMEM;
536
537 i2s->soc_info = device_get_match_data(dev);
538
539 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
540 if (IS_ERR(i2s->base))
541 return PTR_ERR(i2s->base);
542
543 i2s->playback_dma_data.maxburst = 16;
544 i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO;
545
546 i2s->capture_dma_data.maxburst = 16;
547 i2s->capture_dma_data.addr = mem->start + JZ_REG_AIC_FIFO;
548
549 i2s->clk_aic = devm_clk_get(dev, "aic");
550 if (IS_ERR(i2s->clk_aic))
551 return PTR_ERR(i2s->clk_aic);
552
553 i2s->clk_i2s = devm_clk_get(dev, "i2s");
554 if (IS_ERR(i2s->clk_i2s))
555 return PTR_ERR(i2s->clk_i2s);
556
557 platform_set_drvdata(pdev, i2s);
558
559 ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component,
560 i2s->soc_info->dai, 1);
561 if (ret)
562 return ret;
563
564 return devm_snd_dmaengine_pcm_register(dev, NULL,
565 SND_DMAENGINE_PCM_FLAG_COMPAT);
566 }
567
568 static struct platform_driver jz4740_i2s_driver = {
569 .probe = jz4740_i2s_dev_probe,
570 .driver = {
571 .name = "jz4740-i2s",
572 .of_match_table = jz4740_of_matches,
573 },
574 };
575
576 module_platform_driver(jz4740_i2s_driver);
577
578 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
579 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
580 MODULE_LICENSE("GPL");
581 MODULE_ALIAS("platform:jz4740-i2s");
582