1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 3 /* 4 * Copyright (c) 2022 MediaTek Corporation. All rights reserved. 5 * 6 * Header file for the mt8186 DSP register definition 7 */ 8 9 #ifndef __MT8186_H 10 #define __MT8186_H 11 12 struct mtk_adsp_chip_info; 13 struct snd_sof_dev; 14 15 #define DSP_REG_BAR 4 16 #define DSP_SECREG_BAR 5 17 #define DSP_BUSREG_BAR 6 18 19 /***************************************************************************** 20 * R E G I S T E R TABLE 21 *****************************************************************************/ 22 /* dsp cfg */ 23 #define ADSP_CFGREG_SW_RSTN 0x0000 24 #define SW_DBG_RSTN_C0 BIT(0) 25 #define SW_RSTN_C0 BIT(4) 26 #define ADSP_HIFI_IO_CONFIG 0x000C 27 #define TRACEMEMREADY BIT(15) 28 #define RUNSTALL BIT(31) 29 #define ADSP_IRQ_MASK 0x0030 30 #define ADSP_DVFSRC_REQ 0x0040 31 #define ADSP_DDREN_REQ_0 0x0044 32 #define ADSP_SEMAPHORE 0x0064 33 #define ADSP_WDT_CON_C0 0x007C 34 #define ADSP_MBOX_IRQ_EN 0x009C 35 #define DSP_MBOX0_IRQ_EN BIT(0) 36 #define DSP_MBOX1_IRQ_EN BIT(1) 37 #define DSP_MBOX2_IRQ_EN BIT(2) 38 #define DSP_MBOX3_IRQ_EN BIT(3) 39 #define DSP_MBOX4_IRQ_EN BIT(4) 40 #define DSP_PDEBUGPC 0x013C 41 #define ADSP_CK_EN 0x1000 42 #define CORE_CLK_EN BIT(0) 43 #define COREDBG_EN BIT(1) 44 #define TIMER_EN BIT(3) 45 #define DMA_EN BIT(4) 46 #define UART_EN BIT(5) 47 #define ADSP_UART_CTRL 0x1010 48 #define UART_BCLK_CG BIT(0) 49 #define UART_RSTN BIT(3) 50 51 /* dsp sec */ 52 #define ADSP_PRID 0x0 53 #define ADSP_ALTVEC_C0 0x04 54 #define ADSP_ALTVECSEL 0x0C 55 #define ADSP_ALTVECSEL_C0 BIT(1) 56 57 /* dsp bus */ 58 #define ADSP_SRAM_POOL_CON 0x190 59 #define DSP_SRAM_POOL_PD_MASK 0xF00F /* [0:3] and [12:15] */ 60 #define DSP_C0_EMI_MAP_ADDR 0xA00 /* ADSP Core0 To EMI Address Remap */ 61 #define DSP_C0_DMAEMI_MAP_ADDR 0xA08 /* DMA0 To EMI Address Remap */ 62 63 /* DSP memories */ 64 #define MBOX_OFFSET 0x500000 /* DRAM */ 65 #define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */ 66 #define DSP_DRAM_SIZE 0xA00000 /* 16M */ 67 68 /*remap dram between AP and DSP view, 4KB aligned*/ 69 #define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x4E100000 /* MT8186 DSP view */ 70 #define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8186 DSP view */ 71 #define DRAM_REMAP_SHIFT 12 72 #define DRAM_REMAP_MASK 0xFFF 73 74 #define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/ 75 #define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/ 76 #define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL) 77 78 void mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr); 79 void mt8186_sof_hifixdsp_shutdown(struct snd_sof_dev *sdev); 80 #endif 81