1 // SPDX-License-Identifier: GPL-2.0
2 #include <stdio.h>
3 #include <stdlib.h>
4 #include "util/evsel.h"
5 #include "util/env.h"
6 #include "util/pmu.h"
7 #include "linux/string.h"
8 #include "evsel.h"
9 #include "util/debug.h"
10 #include "env.h"
11
12 #define IBS_FETCH_L3MISSONLY (1ULL << 59)
13 #define IBS_OP_L3MISSONLY (1ULL << 16)
14
arch_evsel__set_sample_weight(struct evsel * evsel)15 void arch_evsel__set_sample_weight(struct evsel *evsel)
16 {
17 evsel__set_sample_bit(evsel, WEIGHT_STRUCT);
18 }
19
arch_evsel__fixup_new_cycles(struct perf_event_attr * attr)20 void arch_evsel__fixup_new_cycles(struct perf_event_attr *attr)
21 {
22 struct perf_env env = { .total_mem = 0, } ;
23
24 if (!perf_env__cpuid(&env))
25 return;
26
27 /*
28 * On AMD, precise cycles event sampling internally uses IBS pmu.
29 * But IBS does not have filtering capabilities and perf by default
30 * sets exclude_guest = 1. This makes IBS pmu event init fail and
31 * thus perf ends up doing non-precise sampling. Avoid it by clearing
32 * exclude_guest.
33 */
34 if (env.cpuid && strstarts(env.cpuid, "AuthenticAMD"))
35 attr->exclude_guest = 0;
36
37 free(env.cpuid);
38 }
39
40 /* Check whether the evsel's PMU supports the perf metrics */
evsel__sys_has_perf_metrics(const struct evsel * evsel)41 bool evsel__sys_has_perf_metrics(const struct evsel *evsel)
42 {
43 const char *pmu_name = evsel->pmu_name ? evsel->pmu_name : "cpu";
44
45 /*
46 * The PERF_TYPE_RAW type is the core PMU type, e.g., "cpu" PMU
47 * on a non-hybrid machine, "cpu_core" PMU on a hybrid machine.
48 * The slots event is only available for the core PMU, which
49 * supports the perf metrics feature.
50 * Checking both the PERF_TYPE_RAW type and the slots event
51 * should be good enough to detect the perf metrics feature.
52 */
53 if ((evsel->core.attr.type == PERF_TYPE_RAW) &&
54 pmu_have_event(pmu_name, "slots"))
55 return true;
56
57 return false;
58 }
59
arch_evsel__must_be_in_group(const struct evsel * evsel)60 bool arch_evsel__must_be_in_group(const struct evsel *evsel)
61 {
62 if (!evsel__sys_has_perf_metrics(evsel))
63 return false;
64
65 return evsel->name &&
66 (strcasestr(evsel->name, "slots") ||
67 strcasestr(evsel->name, "topdown"));
68 }
69
arch_evsel__hw_name(struct evsel * evsel,char * bf,size_t size)70 int arch_evsel__hw_name(struct evsel *evsel, char *bf, size_t size)
71 {
72 u64 event = evsel->core.attr.config & PERF_HW_EVENT_MASK;
73 u64 pmu = evsel->core.attr.config >> PERF_PMU_TYPE_SHIFT;
74 const char *event_name;
75
76 if (event < PERF_COUNT_HW_MAX && evsel__hw_names[event])
77 event_name = evsel__hw_names[event];
78 else
79 event_name = "unknown-hardware";
80
81 /* The PMU type is not required for the non-hybrid platform. */
82 if (!pmu)
83 return scnprintf(bf, size, "%s", event_name);
84
85 return scnprintf(bf, size, "%s/%s/",
86 evsel->pmu_name ? evsel->pmu_name : "cpu",
87 event_name);
88 }
89
ibs_l3miss_warn(void)90 static void ibs_l3miss_warn(void)
91 {
92 pr_warning(
93 "WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled\n"
94 "and tagged operation does not cause L3 Miss. This causes sampling period skew.\n");
95 }
96
arch__post_evsel_config(struct evsel * evsel,struct perf_event_attr * attr)97 void arch__post_evsel_config(struct evsel *evsel, struct perf_event_attr *attr)
98 {
99 struct perf_pmu *evsel_pmu, *ibs_fetch_pmu, *ibs_op_pmu;
100 static int warned_once;
101
102 if (warned_once || !x86__is_amd_cpu())
103 return;
104
105 evsel_pmu = evsel__find_pmu(evsel);
106 if (!evsel_pmu)
107 return;
108
109 ibs_fetch_pmu = perf_pmu__find("ibs_fetch");
110 ibs_op_pmu = perf_pmu__find("ibs_op");
111
112 if (ibs_fetch_pmu && ibs_fetch_pmu->type == evsel_pmu->type) {
113 if (attr->config & IBS_FETCH_L3MISSONLY) {
114 ibs_l3miss_warn();
115 warned_once = 1;
116 }
117 } else if (ibs_op_pmu && ibs_op_pmu->type == evsel_pmu->type) {
118 if (attr->config & IBS_OP_L3MISSONLY) {
119 ibs_l3miss_warn();
120 warned_once = 1;
121 }
122 }
123 }
124