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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * tools/testing/selftests/kvm/include/x86_64/svm.h
4  * This is a copy of arch/x86/include/asm/svm.h
5  *
6  */
7 
8 #ifndef SELFTEST_KVM_SVM_H
9 #define SELFTEST_KVM_SVM_H
10 
11 enum {
12 	INTERCEPT_INTR,
13 	INTERCEPT_NMI,
14 	INTERCEPT_SMI,
15 	INTERCEPT_INIT,
16 	INTERCEPT_VINTR,
17 	INTERCEPT_SELECTIVE_CR0,
18 	INTERCEPT_STORE_IDTR,
19 	INTERCEPT_STORE_GDTR,
20 	INTERCEPT_STORE_LDTR,
21 	INTERCEPT_STORE_TR,
22 	INTERCEPT_LOAD_IDTR,
23 	INTERCEPT_LOAD_GDTR,
24 	INTERCEPT_LOAD_LDTR,
25 	INTERCEPT_LOAD_TR,
26 	INTERCEPT_RDTSC,
27 	INTERCEPT_RDPMC,
28 	INTERCEPT_PUSHF,
29 	INTERCEPT_POPF,
30 	INTERCEPT_CPUID,
31 	INTERCEPT_RSM,
32 	INTERCEPT_IRET,
33 	INTERCEPT_INTn,
34 	INTERCEPT_INVD,
35 	INTERCEPT_PAUSE,
36 	INTERCEPT_HLT,
37 	INTERCEPT_INVLPG,
38 	INTERCEPT_INVLPGA,
39 	INTERCEPT_IOIO_PROT,
40 	INTERCEPT_MSR_PROT,
41 	INTERCEPT_TASK_SWITCH,
42 	INTERCEPT_FERR_FREEZE,
43 	INTERCEPT_SHUTDOWN,
44 	INTERCEPT_VMRUN,
45 	INTERCEPT_VMMCALL,
46 	INTERCEPT_VMLOAD,
47 	INTERCEPT_VMSAVE,
48 	INTERCEPT_STGI,
49 	INTERCEPT_CLGI,
50 	INTERCEPT_SKINIT,
51 	INTERCEPT_RDTSCP,
52 	INTERCEPT_ICEBP,
53 	INTERCEPT_WBINVD,
54 	INTERCEPT_MONITOR,
55 	INTERCEPT_MWAIT,
56 	INTERCEPT_MWAIT_COND,
57 	INTERCEPT_XSETBV,
58 	INTERCEPT_RDPRU,
59 };
60 
61 struct hv_vmcb_enlightenments {
62 	struct __packed hv_enlightenments_control {
63 		u32 nested_flush_hypercall:1;
64 		u32 msr_bitmap:1;
65 		u32 enlightened_npt_tlb: 1;
66 		u32 reserved:29;
67 	} __packed hv_enlightenments_control;
68 	u32 hv_vp_id;
69 	u64 hv_vm_id;
70 	u64 partition_assist_page;
71 	u64 reserved;
72 } __packed;
73 
74 /*
75  * Hyper-V uses the software reserved clean bit in VMCB
76  */
77 #define HV_VMCB_NESTED_ENLIGHTENMENTS (1U << 31)
78 
79 struct __attribute__ ((__packed__)) vmcb_control_area {
80 	u32 intercept_cr;
81 	u32 intercept_dr;
82 	u32 intercept_exceptions;
83 	u64 intercept;
84 	u8 reserved_1[40];
85 	u16 pause_filter_thresh;
86 	u16 pause_filter_count;
87 	u64 iopm_base_pa;
88 	u64 msrpm_base_pa;
89 	u64 tsc_offset;
90 	u32 asid;
91 	u8 tlb_ctl;
92 	u8 reserved_2[3];
93 	u32 int_ctl;
94 	u32 int_vector;
95 	u32 int_state;
96 	u8 reserved_3[4];
97 	u32 exit_code;
98 	u32 exit_code_hi;
99 	u64 exit_info_1;
100 	u64 exit_info_2;
101 	u32 exit_int_info;
102 	u32 exit_int_info_err;
103 	u64 nested_ctl;
104 	u64 avic_vapic_bar;
105 	u8 reserved_4[8];
106 	u32 event_inj;
107 	u32 event_inj_err;
108 	u64 nested_cr3;
109 	u64 virt_ext;
110 	u32 clean;
111 	u32 reserved_5;
112 	u64 next_rip;
113 	u8 insn_len;
114 	u8 insn_bytes[15];
115 	u64 avic_backing_page;	/* Offset 0xe0 */
116 	u8 reserved_6[8];	/* Offset 0xe8 */
117 	u64 avic_logical_id;	/* Offset 0xf0 */
118 	u64 avic_physical_id;	/* Offset 0xf8 */
119 	u8 reserved_7[8];
120 	u64 vmsa_pa;		/* Used for an SEV-ES guest */
121 	u8 reserved_8[720];
122 	/*
123 	 * Offset 0x3e0, 32 bytes reserved
124 	 * for use by hypervisor/software.
125 	 */
126 	union {
127 		struct hv_vmcb_enlightenments hv_enlightenments;
128 		u8 reserved_sw[32];
129 	};
130 };
131 
132 
133 #define TLB_CONTROL_DO_NOTHING 0
134 #define TLB_CONTROL_FLUSH_ALL_ASID 1
135 #define TLB_CONTROL_FLUSH_ASID 3
136 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
137 
138 #define V_TPR_MASK 0x0f
139 
140 #define V_IRQ_SHIFT 8
141 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
142 
143 #define V_GIF_SHIFT 9
144 #define V_GIF_MASK (1 << V_GIF_SHIFT)
145 
146 #define V_INTR_PRIO_SHIFT 16
147 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
148 
149 #define V_IGN_TPR_SHIFT 20
150 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
151 
152 #define V_INTR_MASKING_SHIFT 24
153 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
154 
155 #define V_GIF_ENABLE_SHIFT 25
156 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
157 
158 #define AVIC_ENABLE_SHIFT 31
159 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
160 
161 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
162 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
163 
164 #define SVM_INTERRUPT_SHADOW_MASK 1
165 
166 #define SVM_IOIO_STR_SHIFT 2
167 #define SVM_IOIO_REP_SHIFT 3
168 #define SVM_IOIO_SIZE_SHIFT 4
169 #define SVM_IOIO_ASIZE_SHIFT 7
170 
171 #define SVM_IOIO_TYPE_MASK 1
172 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
173 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
174 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
175 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
176 
177 #define SVM_VM_CR_VALID_MASK	0x001fULL
178 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
179 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
180 
181 #define SVM_NESTED_CTL_NP_ENABLE	BIT(0)
182 #define SVM_NESTED_CTL_SEV_ENABLE	BIT(1)
183 
184 struct __attribute__ ((__packed__)) vmcb_seg {
185 	u16 selector;
186 	u16 attrib;
187 	u32 limit;
188 	u64 base;
189 };
190 
191 struct __attribute__ ((__packed__)) vmcb_save_area {
192 	struct vmcb_seg es;
193 	struct vmcb_seg cs;
194 	struct vmcb_seg ss;
195 	struct vmcb_seg ds;
196 	struct vmcb_seg fs;
197 	struct vmcb_seg gs;
198 	struct vmcb_seg gdtr;
199 	struct vmcb_seg ldtr;
200 	struct vmcb_seg idtr;
201 	struct vmcb_seg tr;
202 	u8 reserved_1[43];
203 	u8 cpl;
204 	u8 reserved_2[4];
205 	u64 efer;
206 	u8 reserved_3[112];
207 	u64 cr4;
208 	u64 cr3;
209 	u64 cr0;
210 	u64 dr7;
211 	u64 dr6;
212 	u64 rflags;
213 	u64 rip;
214 	u8 reserved_4[88];
215 	u64 rsp;
216 	u8 reserved_5[24];
217 	u64 rax;
218 	u64 star;
219 	u64 lstar;
220 	u64 cstar;
221 	u64 sfmask;
222 	u64 kernel_gs_base;
223 	u64 sysenter_cs;
224 	u64 sysenter_esp;
225 	u64 sysenter_eip;
226 	u64 cr2;
227 	u8 reserved_6[32];
228 	u64 g_pat;
229 	u64 dbgctl;
230 	u64 br_from;
231 	u64 br_to;
232 	u64 last_excp_from;
233 	u64 last_excp_to;
234 };
235 
236 struct __attribute__ ((__packed__)) vmcb {
237 	struct vmcb_control_area control;
238 	struct vmcb_save_area save;
239 };
240 
241 #define SVM_VM_CR_SVM_DISABLE 4
242 
243 #define SVM_SELECTOR_S_SHIFT 4
244 #define SVM_SELECTOR_DPL_SHIFT 5
245 #define SVM_SELECTOR_P_SHIFT 7
246 #define SVM_SELECTOR_AVL_SHIFT 8
247 #define SVM_SELECTOR_L_SHIFT 9
248 #define SVM_SELECTOR_DB_SHIFT 10
249 #define SVM_SELECTOR_G_SHIFT 11
250 
251 #define SVM_SELECTOR_TYPE_MASK (0xf)
252 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
253 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
254 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
255 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
256 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
257 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
258 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
259 
260 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
261 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
262 #define SVM_SELECTOR_CODE_MASK (1 << 3)
263 
264 #define INTERCEPT_CR0_READ	0
265 #define INTERCEPT_CR3_READ	3
266 #define INTERCEPT_CR4_READ	4
267 #define INTERCEPT_CR8_READ	8
268 #define INTERCEPT_CR0_WRITE	(16 + 0)
269 #define INTERCEPT_CR3_WRITE	(16 + 3)
270 #define INTERCEPT_CR4_WRITE	(16 + 4)
271 #define INTERCEPT_CR8_WRITE	(16 + 8)
272 
273 #define INTERCEPT_DR0_READ	0
274 #define INTERCEPT_DR1_READ	1
275 #define INTERCEPT_DR2_READ	2
276 #define INTERCEPT_DR3_READ	3
277 #define INTERCEPT_DR4_READ	4
278 #define INTERCEPT_DR5_READ	5
279 #define INTERCEPT_DR6_READ	6
280 #define INTERCEPT_DR7_READ	7
281 #define INTERCEPT_DR0_WRITE	(16 + 0)
282 #define INTERCEPT_DR1_WRITE	(16 + 1)
283 #define INTERCEPT_DR2_WRITE	(16 + 2)
284 #define INTERCEPT_DR3_WRITE	(16 + 3)
285 #define INTERCEPT_DR4_WRITE	(16 + 4)
286 #define INTERCEPT_DR5_WRITE	(16 + 5)
287 #define INTERCEPT_DR6_WRITE	(16 + 6)
288 #define INTERCEPT_DR7_WRITE	(16 + 7)
289 
290 #define SVM_EVTINJ_VEC_MASK 0xff
291 
292 #define SVM_EVTINJ_TYPE_SHIFT 8
293 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
294 
295 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
296 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
297 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
298 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
299 
300 #define SVM_EVTINJ_VALID (1 << 31)
301 #define SVM_EVTINJ_VALID_ERR (1 << 11)
302 
303 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
304 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
305 
306 #define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
307 #define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
308 #define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
309 #define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
310 
311 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
312 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
313 
314 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
315 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
316 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
317 
318 #define SVM_EXITINFO_REG_MASK 0x0F
319 
320 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
321 
322 #endif /* SELFTEST_KVM_SVM_H */
323