1047 static u32 *setup_predicate_disable_wa(const struct intel_context *ce, u32 *cs)  in setup_predicate_disable_wa()  argument
1050 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT | (4 - 2);  in setup_predicate_disable_wa()
1051 	*cs++ = lrc_indirect_bb(ce) + DG2_PREDICATE_RESULT_WA;  in setup_predicate_disable_wa()
1052 	*cs++ = 0;  in setup_predicate_disable_wa()
1053 	*cs++ = 0; /* No predication */  in setup_predicate_disable_wa()
1056 	*cs++ = MI_BATCH_BUFFER_END | BIT(15);  in setup_predicate_disable_wa()
1057 	*cs++ = MI_SET_PREDICATE | MI_SET_PREDICATE_DISABLE;  in setup_predicate_disable_wa()
1060 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT | (4 - 2);  in setup_predicate_disable_wa()
1061 	*cs++ = lrc_indirect_bb(ce) + DG2_PREDICATE_RESULT_WA;  in setup_predicate_disable_wa()
1062 	*cs++ = 0;  in setup_predicate_disable_wa()
1063 	*cs++ = 1; /* enable predication before the next BB */  in setup_predicate_disable_wa()
1065 	*cs++ = MI_BATCH_BUFFER_END;  in setup_predicate_disable_wa()
1066 	GEM_BUG_ON(offset_in_page(cs) > DG2_PREDICATE_RESULT_WA);  in setup_predicate_disable_wa()
1068 	return cs;  in setup_predicate_disable_wa()
1256 gen12_emit_timestamp_wa(const struct intel_context *ce, u32 *cs)  in gen12_emit_timestamp_wa()  argument
1258 	*cs++ = MI_LOAD_REGISTER_MEM_GEN8 |  in gen12_emit_timestamp_wa()
1261 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_timestamp_wa()
1262 	*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +  in gen12_emit_timestamp_wa()
1264 	*cs++ = 0;  in gen12_emit_timestamp_wa()
1266 	*cs++ = MI_LOAD_REGISTER_REG |  in gen12_emit_timestamp_wa()
1269 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_timestamp_wa()
1270 	*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));  in gen12_emit_timestamp_wa()
1272 	*cs++ = MI_LOAD_REGISTER_REG |  in gen12_emit_timestamp_wa()
1275 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_timestamp_wa()
1276 	*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));  in gen12_emit_timestamp_wa()
1278 	return cs;  in gen12_emit_timestamp_wa()
1282 gen12_emit_restore_scratch(const struct intel_context *ce, u32 *cs)  in gen12_emit_restore_scratch()  argument
1286 	*cs++ = MI_LOAD_REGISTER_MEM_GEN8 |  in gen12_emit_restore_scratch()
1289 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_restore_scratch()
1290 	*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +  in gen12_emit_restore_scratch()
1292 	*cs++ = 0;  in gen12_emit_restore_scratch()
1294 	return cs;  in gen12_emit_restore_scratch()
1298 gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs)  in gen12_emit_cmd_buf_wa()  argument
1302 	*cs++ = MI_LOAD_REGISTER_MEM_GEN8 |  in gen12_emit_cmd_buf_wa()
1305 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_cmd_buf_wa()
1306 	*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +  in gen12_emit_cmd_buf_wa()
1308 	*cs++ = 0;  in gen12_emit_cmd_buf_wa()
1310 	*cs++ = MI_LOAD_REGISTER_REG |  in gen12_emit_cmd_buf_wa()
1313 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_cmd_buf_wa()
1314 	*cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));  in gen12_emit_cmd_buf_wa()
1316 	return cs;  in gen12_emit_cmd_buf_wa()
1327 dg2_emit_draw_watermark_setting(u32 *cs)  in dg2_emit_draw_watermark_setting()  argument
1329 	*cs++ = MI_LOAD_REGISTER_IMM(1);  in dg2_emit_draw_watermark_setting()
1330 	*cs++ = i915_mmio_reg_offset(DRAW_WATERMARK);  in dg2_emit_draw_watermark_setting()
1331 	*cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF);  in dg2_emit_draw_watermark_setting()
1333 	return cs;  in dg2_emit_draw_watermark_setting()
1337 gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)  in gen12_emit_indirect_ctx_rcs()  argument
1339 	cs = gen12_emit_timestamp_wa(ce, cs);  in gen12_emit_indirect_ctx_rcs()
1340 	cs = gen12_emit_cmd_buf_wa(ce, cs);  in gen12_emit_indirect_ctx_rcs()
1341 	cs = gen12_emit_restore_scratch(ce, cs);  in gen12_emit_indirect_ctx_rcs()
1345 		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);  in gen12_emit_indirect_ctx_rcs()
1347 	cs = gen12_emit_aux_table_inv(ce->engine, cs);  in gen12_emit_indirect_ctx_rcs()
1353 		cs = dg2_emit_draw_watermark_setting(cs);  in gen12_emit_indirect_ctx_rcs()
1355 	return cs;  in gen12_emit_indirect_ctx_rcs()
1359 gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)  in gen12_emit_indirect_ctx_xcs()  argument
1361 	cs = gen12_emit_timestamp_wa(ce, cs);  in gen12_emit_indirect_ctx_xcs()
1362 	cs = gen12_emit_restore_scratch(ce, cs);  in gen12_emit_indirect_ctx_xcs()
1367 			cs = gen8_emit_pipe_control(cs,  in gen12_emit_indirect_ctx_xcs()
1371 	return gen12_emit_aux_table_inv(ce->engine, cs);  in gen12_emit_indirect_ctx_xcs()
1380 	u32 *cs;  in setup_indirect_ctx_bb()  local
1382 	cs = emit(ce, start);  in setup_indirect_ctx_bb()
1383 	GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs));  in setup_indirect_ctx_bb()
1384 	while ((unsigned long)cs % CACHELINE_BYTES)  in setup_indirect_ctx_bb()
1385 		*cs++ = MI_NOOP;  in setup_indirect_ctx_bb()
1387 	GEM_BUG_ON(cs - start > DG2_PREDICATE_RESULT_BB / sizeof(*start));  in setup_indirect_ctx_bb()
1392 			       (cs - start) * sizeof(*cs));  in setup_indirect_ctx_bb()
1469 		u32 *(*fn)(const struct intel_context *ce, u32 *cs);  in lrc_update_regs()