Lines Matching refs:mpu3050
180 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) in mpu3050_get_freq() argument
184 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) in mpu3050_get_freq()
188 freq /= (mpu3050->divisor + 1); in mpu3050_get_freq()
193 static int mpu3050_start_sampling(struct mpu3050 *mpu3050) in mpu3050_start_sampling() argument
200 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, in mpu3050_start_sampling()
206 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, in mpu3050_start_sampling()
214 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); in mpu3050_start_sampling()
216 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, in mpu3050_start_sampling()
222 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, in mpu3050_start_sampling()
224 mpu3050->fullscale << MPU3050_FS_SHIFT | in mpu3050_start_sampling()
225 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); in mpu3050_start_sampling()
230 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); in mpu3050_start_sampling()
239 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); in mpu3050_start_sampling()
244 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) in mpu3050_set_8khz_samplerate() argument
250 lpf = mpu3050->lpf; in mpu3050_set_8khz_samplerate()
251 divisor = mpu3050->divisor; in mpu3050_set_8khz_samplerate()
253 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ in mpu3050_set_8khz_samplerate()
254 mpu3050->divisor = 0; /* Divide by 1 */ in mpu3050_set_8khz_samplerate()
255 ret = mpu3050_start_sampling(mpu3050); in mpu3050_set_8khz_samplerate()
257 mpu3050->lpf = lpf; in mpu3050_set_8khz_samplerate()
258 mpu3050->divisor = divisor; in mpu3050_set_8khz_samplerate()
268 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_read_raw() local
294 *val = mpu3050->calibration[chan->scan_index-1]; in mpu3050_read_raw()
300 *val = mpu3050_get_freq(mpu3050); in mpu3050_read_raw()
317 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; in mpu3050_read_raw()
325 pm_runtime_get_sync(mpu3050->dev); in mpu3050_read_raw()
326 mutex_lock(&mpu3050->lock); in mpu3050_read_raw()
328 ret = mpu3050_set_8khz_samplerate(mpu3050); in mpu3050_read_raw()
334 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, in mpu3050_read_raw()
337 dev_err(mpu3050->dev, in mpu3050_read_raw()
347 ret = regmap_bulk_read(mpu3050->map, in mpu3050_read_raw()
352 dev_err(mpu3050->dev, in mpu3050_read_raw()
372 mutex_unlock(&mpu3050->lock); in mpu3050_read_raw()
373 pm_runtime_mark_last_busy(mpu3050->dev); in mpu3050_read_raw()
374 pm_runtime_put_autosuspend(mpu3050->dev); in mpu3050_read_raw()
383 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_write_raw() local
404 mpu3050->calibration[chan->scan_index-1] = val; in mpu3050_write_raw()
419 mpu3050->lpf = LPF_256_HZ_NOLPF; in mpu3050_write_raw()
420 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; in mpu3050_write_raw()
424 mpu3050->lpf = LPF_188_HZ; in mpu3050_write_raw()
425 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; in mpu3050_write_raw()
440 mpu3050->fullscale = FS_2000_DPS; in mpu3050_write_raw()
451 mpu3050->fullscale = FS_250_DPS; in mpu3050_write_raw()
454 mpu3050->fullscale = FS_500_DPS; in mpu3050_write_raw()
457 mpu3050->fullscale = FS_1000_DPS; in mpu3050_write_raw()
460 mpu3050->fullscale = FS_2000_DPS; in mpu3050_write_raw()
473 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_trigger_handler() local
489 timestamp = mpu3050->hw_timestamp; in mpu3050_trigger_handler()
493 mutex_lock(&mpu3050->lock); in mpu3050_trigger_handler()
496 if (mpu3050->hw_irq_trigger) { in mpu3050_trigger_handler()
503 ret = regmap_bulk_read(mpu3050->map, in mpu3050_trigger_handler()
512 dev_info(mpu3050->dev, in mpu3050_trigger_handler()
516 ret = regmap_update_bits(mpu3050->map, in mpu3050_trigger_handler()
523 dev_info(mpu3050->dev, "error resetting FIFO\n"); in mpu3050_trigger_handler()
526 mpu3050->pending_fifo_footer = false; in mpu3050_trigger_handler()
530 dev_dbg(mpu3050->dev, in mpu3050_trigger_handler()
547 if (mpu3050->pending_fifo_footer) { in mpu3050_trigger_handler()
557 ret = regmap_bulk_read(mpu3050->map, in mpu3050_trigger_handler()
564 dev_dbg(mpu3050->dev, in mpu3050_trigger_handler()
580 mpu3050->pending_fifo_footer = true; in mpu3050_trigger_handler()
587 ret = regmap_bulk_read(mpu3050->map, in mpu3050_trigger_handler()
597 dev_dbg(mpu3050->dev, in mpu3050_trigger_handler()
628 dev_dbg(mpu3050->dev, in mpu3050_trigger_handler()
634 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, scan.chans, in mpu3050_trigger_handler()
637 dev_err(mpu3050->dev, in mpu3050_trigger_handler()
645 mutex_unlock(&mpu3050->lock); in mpu3050_trigger_handler()
653 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_buffer_preenable() local
655 pm_runtime_get_sync(mpu3050->dev); in mpu3050_buffer_preenable()
658 if (!mpu3050->hw_irq_trigger) in mpu3050_buffer_preenable()
659 return mpu3050_set_8khz_samplerate(mpu3050); in mpu3050_buffer_preenable()
666 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_buffer_postdisable() local
668 pm_runtime_mark_last_busy(mpu3050->dev); in mpu3050_buffer_postdisable()
669 pm_runtime_put_autosuspend(mpu3050->dev); in mpu3050_buffer_postdisable()
683 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_get_mount_matrix() local
685 return &mpu3050->orientation; in mpu3050_get_mount_matrix()
769 static int mpu3050_read_mem(struct mpu3050 *mpu3050, in mpu3050_read_mem() argument
777 ret = regmap_write(mpu3050->map, in mpu3050_read_mem()
783 ret = regmap_write(mpu3050->map, in mpu3050_read_mem()
789 return regmap_bulk_read(mpu3050->map, in mpu3050_read_mem()
795 static int mpu3050_hw_init(struct mpu3050 *mpu3050) in mpu3050_hw_init() argument
802 ret = regmap_update_bits(mpu3050->map, in mpu3050_hw_init()
810 ret = regmap_update_bits(mpu3050->map, in mpu3050_hw_init()
818 ret = regmap_write(mpu3050->map, in mpu3050_hw_init()
825 ret = mpu3050_read_mem(mpu3050, in mpu3050_hw_init()
840 dev_info(mpu3050->dev, in mpu3050_hw_init()
859 static int mpu3050_power_up(struct mpu3050 *mpu3050) in mpu3050_power_up() argument
863 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); in mpu3050_power_up()
865 dev_err(mpu3050->dev, "cannot enable regulators\n"); in mpu3050_power_up()
875 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, in mpu3050_power_up()
878 regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); in mpu3050_power_up()
879 dev_err(mpu3050->dev, "error setting power mode\n"); in mpu3050_power_up()
887 static int mpu3050_power_down(struct mpu3050 *mpu3050) in mpu3050_power_down() argument
898 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, in mpu3050_power_down()
901 dev_err(mpu3050->dev, "error putting to sleep\n"); in mpu3050_power_down()
903 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); in mpu3050_power_down()
905 dev_err(mpu3050->dev, "error disabling regulators\n"); in mpu3050_power_down()
914 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_irq_handler() local
916 if (!mpu3050->hw_irq_trigger) in mpu3050_irq_handler()
920 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); in mpu3050_irq_handler()
929 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_irq_thread() local
934 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); in mpu3050_irq_thread()
936 dev_err(mpu3050->dev, "error reading IRQ status\n"); in mpu3050_irq_thread()
956 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_drdy_trigger_set_state() local
963 ret = regmap_write(mpu3050->map, in mpu3050_drdy_trigger_set_state()
967 dev_err(mpu3050->dev, "error disabling IRQ\n"); in mpu3050_drdy_trigger_set_state()
970 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); in mpu3050_drdy_trigger_set_state()
972 dev_err(mpu3050->dev, "error clearing IRQ status\n"); in mpu3050_drdy_trigger_set_state()
975 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); in mpu3050_drdy_trigger_set_state()
977 dev_err(mpu3050->dev, "error disabling FIFO\n"); in mpu3050_drdy_trigger_set_state()
979 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, in mpu3050_drdy_trigger_set_state()
982 dev_err(mpu3050->dev, "error resetting FIFO\n"); in mpu3050_drdy_trigger_set_state()
984 pm_runtime_mark_last_busy(mpu3050->dev); in mpu3050_drdy_trigger_set_state()
985 pm_runtime_put_autosuspend(mpu3050->dev); in mpu3050_drdy_trigger_set_state()
986 mpu3050->hw_irq_trigger = false; in mpu3050_drdy_trigger_set_state()
991 pm_runtime_get_sync(mpu3050->dev); in mpu3050_drdy_trigger_set_state()
992 mpu3050->hw_irq_trigger = true; in mpu3050_drdy_trigger_set_state()
995 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); in mpu3050_drdy_trigger_set_state()
1000 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL, in mpu3050_drdy_trigger_set_state()
1008 mpu3050->pending_fifo_footer = false; in mpu3050_drdy_trigger_set_state()
1011 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, in mpu3050_drdy_trigger_set_state()
1021 ret = mpu3050_start_sampling(mpu3050); in mpu3050_drdy_trigger_set_state()
1026 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); in mpu3050_drdy_trigger_set_state()
1028 dev_err(mpu3050->dev, "error clearing IRQ status\n"); in mpu3050_drdy_trigger_set_state()
1033 if (mpu3050->irq_actl) in mpu3050_drdy_trigger_set_state()
1035 if (mpu3050->irq_latch) in mpu3050_drdy_trigger_set_state()
1037 if (mpu3050->irq_opendrain) in mpu3050_drdy_trigger_set_state()
1040 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); in mpu3050_drdy_trigger_set_state()
1054 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_trigger_probe() local
1055 struct device *dev = mpu3050->dev; in mpu3050_trigger_probe()
1059 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, in mpu3050_trigger_probe()
1063 if (!mpu3050->trig) in mpu3050_trigger_probe()
1067 mpu3050->irq_opendrain = device_property_read_bool(dev, "drive-open-drain"); in mpu3050_trigger_probe()
1081 mpu3050->irq_actl = true; in mpu3050_trigger_probe()
1086 mpu3050->irq_latch = true; in mpu3050_trigger_probe()
1097 mpu3050->irq_latch = true; in mpu3050_trigger_probe()
1098 mpu3050->irq_actl = true; in mpu3050_trigger_probe()
1113 if (mpu3050->irq_opendrain) in mpu3050_trigger_probe()
1120 mpu3050->trig->name, in mpu3050_trigger_probe()
1121 mpu3050->trig); in mpu3050_trigger_probe()
1127 mpu3050->irq = irq; in mpu3050_trigger_probe()
1128 mpu3050->trig->dev.parent = dev; in mpu3050_trigger_probe()
1129 mpu3050->trig->ops = &mpu3050_trigger_ops; in mpu3050_trigger_probe()
1130 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); in mpu3050_trigger_probe()
1132 ret = iio_trigger_register(mpu3050->trig); in mpu3050_trigger_probe()
1136 indio_dev->trig = iio_trigger_get(mpu3050->trig); in mpu3050_trigger_probe()
1147 struct mpu3050 *mpu3050; in mpu3050_common_probe() local
1151 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); in mpu3050_common_probe()
1154 mpu3050 = iio_priv(indio_dev); in mpu3050_common_probe()
1156 mpu3050->dev = dev; in mpu3050_common_probe()
1157 mpu3050->map = map; in mpu3050_common_probe()
1158 mutex_init(&mpu3050->lock); in mpu3050_common_probe()
1160 mpu3050->fullscale = FS_2000_DPS; in mpu3050_common_probe()
1162 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; in mpu3050_common_probe()
1163 mpu3050->divisor = 99; in mpu3050_common_probe()
1166 ret = iio_read_mount_matrix(dev, &mpu3050->orientation); in mpu3050_common_probe()
1171 mpu3050->regs[0].supply = mpu3050_reg_vdd; in mpu3050_common_probe()
1172 mpu3050->regs[1].supply = mpu3050_reg_vlogic; in mpu3050_common_probe()
1173 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), in mpu3050_common_probe()
1174 mpu3050->regs); in mpu3050_common_probe()
1180 ret = mpu3050_power_up(mpu3050); in mpu3050_common_probe()
1209 ret = mpu3050_hw_init(mpu3050); in mpu3050_common_probe()
1261 mpu3050_power_down(mpu3050); in mpu3050_common_probe()
1269 struct mpu3050 *mpu3050 = iio_priv(indio_dev); in mpu3050_common_remove() local
1275 if (mpu3050->irq) in mpu3050_common_remove()
1276 free_irq(mpu3050->irq, mpu3050); in mpu3050_common_remove()
1278 mpu3050_power_down(mpu3050); in mpu3050_common_remove()