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| /Documentation/admin-guide/LSM/ |
| D | Smack.rst | 9 Smack is the Simplified Mandatory Access Control Kernel.
10 Smack is a kernel based implementation of mandatory access
13 Smack is not the only Mandatory Access Control scheme
14 available for Linux. Those new to Mandatory Access Control
33 access to systems that use them as Smack does.
50 load the Smack access rules
53 report if a process with one label has access
85 Used to make access control decisions. In almost all cases
95 label does not allow all of the access permitted to a process
102 the Smack rule (more below) that permitted the write access
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| /Documentation/security/ |
| D | landlock.rst | 12 Landlock's goal is to create scoped access-control (i.e. sandboxing). To
20 system security policy enforced by other access control mechanisms (e.g. DAC,
21 LSM). Indeed, a Landlock rule shall not interfere with other access-controls
31 Guiding principles for safe access controls
34 * A Landlock rule shall be focused on access control on kernel objects instead
40 * Kernel access check shall not slow down access request from unsandboxed
47 Cf. `File descriptor access rights`_.
52 Inode access rights
55 All access rights are tied to an inode and what can be accessed through it.
64 File descriptor access rights
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| /Documentation/core-api/ |
| D | unaligned-memory-access.rst | 14 when it comes to memory access. This document presents some details about
19 The definition of an unaligned access
26 access.
28 The above may seem a little vague, as memory access can happen in different
32 which will compile to multiple-byte memory access instructions, namely when
47 of memory access. However, we must consider ALL supported architectures;
52 Why unaligned access is bad
55 The effects of performing an unaligned memory access vary from architecture
62 happen. The exception handler is able to correct the unaligned access,
66 unaligned access to be corrected.
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| D | protection-keys.rst | 20 (PKRU). Each of these is a 32-bit register storing two bits (Access Disable
29 access only and have no effect on instruction fetches.
43 directly in order to change access permissions to memory covered
55 gain access, do the update, then remove its write access::
86 That should be true whether something() is a direct access to 'ptr'
91 or when the kernel does the access on the application's behalf like
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| /Documentation/mm/damon/ |
| D | design.rst | 17 and access-aware system operations on top of the operations set layer, and
25 For data access monitoring and additional low level work, DAMON needs a set of
40 Also, if some architectures or devices supporting special optimized access
60 2. Access check of specific address range in the target space.
99 PTE Accessed-bit Based Access Check
103 Accessed-bit for basic access checks. Only one difference is the way of
130 Access Frequency Monitoring
134 duration. The resolution of the access frequency is controlled by setting
136 access to each page per ``sampling interval`` and aggregates the results. In
161 that assumed to have the same access frequencies into a region. As long as the
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| D | index.rst | 4 DAMON: Data Access MONitor
7 DAMON is a Linux kernel subsystem that provides a framework for data access
19 access-aware fashion. Because the features are also exposed to the user space,
26 feature, DAMON users in both kernel and user spaces can do access-aware system
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| /Documentation/arch/arm/ |
| D | mem_alignment.rst | 5 Too many problems popped up because of unnoticed misaligned memory access in
14 unaligned memory access in general. If those access are predictable, you
16 alignment trap can fixup misaligned access for the exception cases, but at
20 trap to SIGBUS any code performing unaligned access (good for debugging bad
21 code), or even fixup the access by software like for kernel code. The later
36 0 A user process performing an unaligned memory access
42 performing the unaligned access. This is of course
47 performing the unaligned access.
59 information on unaligned access occurrences plus the current mode of
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| /Documentation/ABI/testing/ |
| D | sysfs-class-power | 9 Access: Read
18 Access: Read
27 Access: Read
36 Access: Read
58 Access: Read
76 Access: Read
89 Access: Read
98 Access: Read, Write
118 Access: Read
142 Access: Read
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| D | sysfs-class-power-ltc4162l | 7 Access: Read
25 Access: Read
35 Access: Read
45 Access: Read
61 Access: Read, Write
80 Access: Read, Write
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| D | sysfs-driver-input-exc3000 | 6 Access: Read
15 Access: Read
24 Access: Read
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| /Documentation/userspace-api/ |
| D | landlock.rst | 7 Landlock: unprivileged access control
14 filesystem access) for a set of processes. Because Landlock is a stackable
16 in addition to the existing system-wide access-controls. This kind of sandbox
32 file hierarchy, and the related filesystem actions are defined with `access
44 the need to be explicit about the denied-by-default access rights.
74 access rights, which are only supported starting with the second and third
142 for the ruleset creation, by filtering access rights according to the Landlock
146 We now have a ruleset with one rule allowing read access to ``/usr`` while
182 It is recommended setting access rights to file hierarchy leaves as much as
189 access rights per directory enables to change the location of such directory
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| /Documentation/driver-api/mmc/ |
| D | mmc-dev-parts.rst | 15 Read and write access is provided to the two MMC boot partitions. Due to
18 platform, write access is disabled by default to reduce the chance of
21 To enable write access to /dev/mmcblkXbootY, disable the forced read-only
22 access with::
26 To re-enable read-only access::
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| /Documentation/arch/arm64/ |
| D | perf.rst | 95 Perf Userspace PMU Hardware Counter Access
103 Arm64 allows userspace tools to have access to the registers storing the
111 The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu
112 registers is enabled and that the userspace has access to the relevant
115 In order to have access to the hardware counters, the global sysctl
127 index enables the user to access the PMU registers using the `mrs` instruction.
128 Access to the PMU registers is only valid while the sequence lock is unchanged.
132 The userspace access is supported in libperf using the perf_evsel__mmap()
138 On heterogeneous systems such as big.LITTLE, userspace PMU counter access can
144 can be run using the perf tool to check that the access to the registers works
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| /Documentation/devicetree/bindings/spi/ |
| D | sprd,spi-adi.yaml | 15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
21 48 hardware channels to access analog chip. For 2 software read/write channels,
22 users should set ADI registers to access analog chip. For hardware channels,
25 then users can access the mapped analog chip address by this hardware channel
31 the analog chip address where user want to access by hardware components.
33 Since we have multi-subsystems will use unique ADI to access analog chip, when
76 - description: The analog chip address where user want to access by
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| /Documentation/admin-guide/mm/ |
| D | numaperf.rst | 37 pair may be organized into different ranked access classes to represent
40 the highest access class, 0. Any given target may have one or more
46 relationship for the access class "0" memory initiators and targets::
54 A memory initiator may have multiple memory targets in the same access
56 nodes' access characteristics share the same performance relative to other
57 linked initiator nodes. Each target within an initiator's access class,
60 The access class "1" is used to allow differentiation between initiators
62 IO initiators such as GPUs and NICs. Unlike access class 0, only
72 memory node's access class 0 initiators as follows::
77 are linked under the this access's initiators.
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| /Documentation/sound/cards/ |
| D | hdspm.rst | 64 * access-mode -- MMAP (memory mapped), Not interleaved (PCM_NON-INTERLEAVED)
125 * Access -- Read Write
141 * Access -- Read Write
159 * Access -- Read Write
178 * Access -- Read Write
195 * Access -- Read Write
207 * Access -- Read Write
220 * Access -- Read Write
235 * Access -- Read Write
255 * Access -- Read Write
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| /Documentation/admin-guide/mm/damon/ |
| D | index.rst | 4 DAMON: Data Access MONitor
7 :doc:`DAMON </mm/damon/index>` allows light-weight data access monitoring.
8 Using DAMON, users can analyze the memory access patterns of their systems and
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| /Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.yaml | 191 calxeda,smmu-secure-config-access:
195 access to SMMU configuration registers. In this case non-secure aliases of
282 - description: bus clock required for downstream bus access and for
292 - description: interface clock required to access smmu's registers
294 - description: bus clock required for memory access
295 - description: bus clock required for GPU memory access
304 - description: interface clock required to access mnoc's registers
306 - description: interface clock required to access smmu's registers
324 - description: bus clock required for downstream bus access and for
334 - description: interface clock required to access smmu's registers
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| /Documentation/bpf/ |
| D | prog_cgroup_sysctl.rst | 22 ``BPF_PROG_TYPE_CGROUP_SYSCTL`` provides access to the following context from
39 value to the field can be used to access part of sysctl value starting from
40 specified ``file_pos``. Not all sysctl support access with ``file_pos !=
52 * ``0`` means "reject access to sysctl";
53 * ``1`` means "proceed with access".
62 helpers focus on providing access to these properties:
98 See `test_sysctl_prog.c`_ for an example of BPF program in C that access
100 the result to make decision whether to allow or deny access to sysctl.
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| /Documentation/arch/s390/ |
| D | vfio-ap-locking.rst | 30 controls access to all fields contained within each matrix_mdev
46 The KVM Lock (kvm->lock) controls access to the state data for a KVM guest. This
66 The Guests Lock (matrix_dev->guests_lock) controls access to the
71 1. To control access to the KVM pointer (matrix_mdev->kvm) while the vfio_ap
88 It is not necessary to take the Guests Lock to access the KVM pointer if the
91 held in order to access the KVM pointer since it is set and cleared under the
94 needs to access the KVM pointer only for the purposes of setting or clearing IRQ
111 The PQAP Hook Lock is a r/w semaphore that controls access to the function
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | intel,ixp4xx-expansion-bus-controller.yaml | 10 The IXP4xx expansion bus controller handles access to devices on the
37 description: The IXP4xx has a peculiar MMIO access scheme, as it changes
38 the access pattern for words (swizzling) on the bus depending on whether
92 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
94 intel,ixp4xx-eb-byte-access = <0>;
105 intel,ixp4xx-eb-byte-access = <1>;
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| /Documentation/powerpc/ |
| D | cxlflash.rst | 27 user space application direct access to Flash storage.
33 special path for user space access, and performing error recovery. It
46 either raw access to the entire LUN (referred to as direct
47 or physical LUN access) or access to a kernel/AFU-mediated
48 partition of the LUN (referred to as virtual LUN access). The
90 access to the Flash from user space (without requiring a system call).
93 block library to enable this user space access. The driver supports
115 Applications intending to get access to the CXL Flash from user
121 specifically for devices (LUNs) operating in user space access
135 device (LUN) via user space access need to use the services provided
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| /Documentation/networking/ |
| D | xdp-rx-metadata.rst | 5 This document describes how an eXpress Data Path (XDP) program can access
12 XDP has access to a set of kfuncs to manipulate the metadata in an XDP frame.
79 ``skbs``. However, TC-BPF programs can access the XDP metadata area using
91 access to the original hardware descriptor and can't access any of
100 that will also only have access to the custom metadata.
105 Adding programs that access metadata kfuncs to the ``BPF_MAP_TYPE_PROG_ARRAY``
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| /Documentation/mm/ |
| D | hmm.rst | 11 allowing a device to transparently access program addresses coherently with
40 Split address space happens because devices can only access memory allocated
77 buses only allow basic memory access from device to main memory; even cache
78 coherency is often optional. Access to device memory from a CPU is even more
81 If we only consider the PCIE bus, then a device can access main memory (often
84 in the other direction: the CPU can only access a limited range of the device
90 The final limitation is latency. Access to main memory from the device has an
100 access any memory but we must also permit any memory to be migrated to device
101 memory while the device is using it (blocking CPU access while it happens).
131 Note that any CPU access to a device page triggers a page fault and a migration
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| /Documentation/admin-guide/cgroup-v1/ |
| D | devices.rst | 9 on device files. A device cgroup associates a device access
13 either an integer or * for all. Access is a composition of r
19 never receive a device access which is denied by its parent.
61 access permissions than its parent. Every time an entry is written to
65 more access than the cgroup's parent, it'll be removed from the whitelist.
129 implementation. Removal or addition of exceptions that will reduce the access
132 on current parent's access rules.
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