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/drivers/usb/roles/
Dintel-xhci-usb-role-switch.c61 u32 glk, val; in intel_xhci_usb_set_role() local
69 status = acpi_acquire_global_lock(ACPI_WAIT_FOREVER, &glk); in intel_xhci_usb_set_role()
108 acpi_release_global_lock(glk); in intel_xhci_usb_set_role()
/drivers/firmware/
Dqemu_fw_cfg.c134 u32 glk = -1U; in fw_cfg_read_blob() local
140 status = acpi_acquire_global_lock(ACPI_WAIT_FOREVER, &glk); in fw_cfg_read_blob()
155 acpi_release_global_lock(glk); in fw_cfg_read_blob()
164 u32 glk = -1U; in fw_cfg_write_blob() local
171 status = acpi_acquire_global_lock(ACPI_WAIT_FOREVER, &glk); in fw_cfg_write_blob()
194 acpi_release_global_lock(glk); in fw_cfg_write_blob()
/drivers/gpu/drm/i915/gt/
Dintel_workarounds.c457 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ in gen9_ctx_workarounds_init()
458 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ in gen9_ctx_workarounds_init()
463 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ in gen9_ctx_workarounds_init()
469 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ in gen9_ctx_workarounds_init()
475 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ in gen9_ctx_workarounds_init()
509 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ in gen9_ctx_workarounds_init()
523 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ in gen9_ctx_workarounds_init()
531 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ in gen9_ctx_workarounds_init()
619 /* WaToEnableHwFixForPushConstHWBug:glk */ in glk_ctx_workarounds_init()
1108 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml in gen9_wa_init_mcr()
[all …]
Dintel_lrc.c1643 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ in gen9_init_indirectctx_bb()
1667 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ in gen9_init_indirectctx_bb()
1670 /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */ in gen9_init_indirectctx_bb()
1680 /* WaMediaPoolStateCmdInWABB:bxt,glk */ in gen9_init_indirectctx_bb()
Dintel_gtt.c413 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ in gtt_write_workarounds()
Dintel_mocs.c563 /* WaDisableSkipCaching:skl,bxt,kbl,glk */ in get_mocs_settings()
/drivers/gpu/drm/i915/
Dintel_clock_gating.c64 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ in gen9_init_clock_gating()
68 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl in gen9_init_clock_gating()
69 * Display WA #0859: skl,bxt,kbl,glk,cfl in gen9_init_clock_gating()
121 * WaDisablePWMClockGating:glk in glk_init_clock_gating()
810 CG_FUNCS(glk);
Di915_reg.h1357 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
2658 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
2659 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
3597 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
3623 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
3638 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
3648 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
3726 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
3727 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
3728 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
[all …]
/drivers/gpu/drm/ci/
Dtest.yml190 i915:glk:
196 GPU_VERSION: glk
/drivers/hwmon/
Dasus-ec-sensors.c531 u32 glk; member
559 &data->mutex.glk)); in lock_via_global_acpi_lock()
564 return ACPI_SUCCESS(acpi_release_global_lock(data->mutex.glk)); in unlock_global_acpi_lock()
696 state->lock_data.mutex.glk = 0; in setup_lock_data()
/drivers/gpu/drm/i915/display/
Dintel_cdclk.h49 /* forced minimum cdclk for glk+ audio w/a */
Dintel_display_core.h370 /* VLV/CHV/BXT/GLK DSI MMIO register base address */
Dintel_gmbus.c629 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ in do_gmbus_xfer()
742 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ in do_gmbus_xfer()
Dintel_color.c285 * Display WA #1184: skl,glk in skl_read_csc()
510 * On GLK both pipe CSC and degamma LUT are controlled in ilk_assign_csc()
1493 * The pipe degamma table in GLK+ onwards doesn't in glk_load_degamma_lut()
2557 * On GLK+ both pipe CSC and degamma LUT are controlled in glk_assign_luts()
2608 /* On GLK+ degamma LUT is controlled by csc_enable */ in glk_color_check()
Dintel_fbc.c871 /* Display WA #1105: skl,bxt,kbl,cfl,glk */ in stride_is_valid()
1242 * Display WA #1198: glk+ in __intel_fbc_pre_update()
Dintel_dp_aux.c184 * SKL-GLK: 1.6ms in skl_get_aux_send_ctl()
Dintel_modeset_setup.c906 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl in intel_early_display_was()
Dskl_scaler.c568 * GLK+ scalers don't have a HQ mode so it in intel_atomic_setup_scalers()
/drivers/pinctrl/intel/
Dpinctrl-geminilake.c24 INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, GLK)
26 /* GLK */
/drivers/usb/dwc3/
Ddwc3-pci.c415 { PCI_DEVICE_DATA(INTEL, GLK, &dwc3_pci_intel_swnode) },
/drivers/gpu/drm/i915/soc/
Dintel_dram.c667 * otherwise, this w/a is not needed by bxt/glk. in intel_dram_detect()
/drivers/acpi/
Dec.c818 u32 glk; in acpi_ec_transaction() local
827 status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk); in acpi_ec_transaction()
837 acpi_release_global_lock(glk); in acpi_ec_transaction()
/drivers/gpu/drm/i915/gt/uc/
Dintel_uc_fw.c108 fw_def(GEMINILAKE, 0, guc_mmp(glk, 70, 1, 1)) \
129 fw_def(GEMINILAKE, 0, huc_mmp(glk, 4, 0, 0)) \
/drivers/platform/x86/intel/telemetry/
Dpltdrv.c169 /* GLK specific Data */
/drivers/mfd/
Dintel-lpss-pci.c288 /* GLK */

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