/drivers/gpu/drm/i915/display/ |
D | intel_dpll_mgr.h | 107 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0 111 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1 119 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL 124 * TGL TC PLL 1 port 1 (TC1) 129 * TGL TC PLL 1 port 2 (TC2) 134 * TGL TC PLL 1 port 3 (TC3) 139 * TGL TC PLL 1 port 4 (TC4) 143 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) 147 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) 203 /* tgl */
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D | skl_watermark_regs.h | 15 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ 17 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ 19 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
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D | intel_psr_regs.h | 59 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
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D | intel_display_limits.h | 88 /* tgl+ */
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D | intel_display_power.h | 44 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
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D | intel_dp_aux_backlight.c | 72 # define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE BIT(2) /* Pre-TGL+ */ 79 #define INTEL_EDP_HDR_CONTENT_LUMINANCE 0x346 /* Pre-TGL+ */
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D | intel_dp_mst.c | 196 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ in intel_dp_dsc_mst_compute_link_config() 632 * From TGL spec: "If multi-stream slave transcoder: Configure in intel_mst_post_disable_dp() 995 * Big joiner configuration needs DSC for TGL which is not true for in intel_dp_mst_mode_valid_ctx()
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D | intel_combo_phy.c | 197 * ICL,TGL: in phy_is_master()
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D | icl_dsi_regs.h | 95 /* TGL DSI Chicken register */
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/drivers/media/rc/img-ir/ |
D | img-ir-rc5.c | 14 unsigned int addr, cmd, tgl, start; in img_ir_rc5_scancode() local 20 tgl = (raw >> 11) & 0x01; in img_ir_rc5_scancode() 34 request->toggle = tgl; in img_ir_rc5_scancode()
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/drivers/gpu/drm/i915/gt/ |
D | intel_workarounds.c | 698 * Wa_1409142259:tgl,dg1,adl-p in gen12_ctx_workarounds_init() 699 * Wa_1409347922:tgl,dg1,adl-p in gen12_ctx_workarounds_init() 700 * Wa_1409252684:tgl,dg1,adl-p in gen12_ctx_workarounds_init() 701 * Wa_1409217633:tgl,dg1,adl-p in gen12_ctx_workarounds_init() 702 * Wa_1409207793:tgl,dg1,adl-p in gen12_ctx_workarounds_init() 703 * Wa_1409178076:tgl,dg1,adl-p in gen12_ctx_workarounds_init() 704 * Wa_1408979724:tgl,dg1,adl-p in gen12_ctx_workarounds_init() 705 * Wa_14010443199:tgl,rkl,dg1,adl-p in gen12_ctx_workarounds_init() 706 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p in gen12_ctx_workarounds_init() 707 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p in gen12_ctx_workarounds_init() [all …]
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D | intel_mocs.c | 110 * PTE and those platforms except TGL/RKL will be initialized L3 WB to 123 * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS 127 * For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC. 531 /* For TGL/RKL, Can't be changed now for ABI reasons */ in get_mocs_settings()
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D | intel_tlb.c | 84 /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */ in mmio_invalidate_full()
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D | intel_sseu.c | 274 * Although gen12 architecture supported multiple slices, TGL, RKL, in gen12_sseu_info_init() 293 /* TGL only supports slice-level power gating */ in gen12_sseu_info_init()
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D | selftest_tlb.c | 211 * SZ_64K pages require covering the whole 2M PT (gen8 to tgl/dg1). in create_smem()
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/drivers/gpu/drm/i915/gt/uc/ |
D | intel_uc_fw.c | 69 * firmware as TGL. 96 fw_def(ALDERLAKE_S, 0, guc_maj(tgl, 70, 5, 1)) \ 97 fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 70, 1, 1)) \ 98 fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 69, 0, 3)) \ 100 fw_def(ROCKETLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \ 101 fw_def(TIGERLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \ 116 fw_def(ALDERLAKE_P, 0, huc_raw(tgl)) \ 117 fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ 118 fw_def(ALDERLAKE_S, 0, huc_raw(tgl)) \ 119 fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ [all …]
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/drivers/gpu/drm/imx/dcss/ |
D | dcss-dev.h | 17 #define TGL 0x0C macro 23 #define dcss_toggle(v, c) writel((v), (c) + TGL)
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/drivers/platform/x86/intel/pmc/ |
D | Makefile | 7 icl.o tgl.o adl.o mtl.o
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/drivers/gpu/drm/ci/ |
D | test.yml | 235 i915:tgl: 241 GPU_VERSION: tgl
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/drivers/soundwire/ |
D | dmi-quirks.c | 94 /* TGL devices */
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/drivers/gpu/drm/i915/ |
D | intel_device_info.h | 112 /* TGL */
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/drivers/net/ethernet/stmicro/stmmac/ |
D | Kconfig | 267 stmmac driver. This driver is used for Intel Quark/EHL/TGL.
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/drivers/mfd/ |
D | intel-lpss-pci.c | 319 /* TGL-H */ 501 /* TGL-LP */
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/drivers/platform/x86/intel/ |
D | vsec.c | 423 /* TGL info */
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/drivers/usb/dwc3/ |
D | dwc3-pci.c | 436 { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) },
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