| /arch/mips/math-emu/ |
| D | cp1emu.c | 849 mips_instruction ir) in cop1_cfc() argument
854 switch (MIPSInst_RD(ir)) { in cop1_cfc()
858 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
868 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
876 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
887 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
898 if (MIPSInst_RT(ir)) in cop1_cfc()
899 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()
906 mips_instruction ir) in cop1_ctc() argument
912 if (MIPSInst_RT(ir) == 0) in cop1_ctc()
[all …]
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| D | dsemul.c | 209 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, in mips_dsemul() argument
219 if (ir == 0) in mips_dsemul()
224 union mips_instruction insn = { .word = ir }; in mips_dsemul()
227 if ((ir >> 16) == MM_NOP16) in mips_dsemul()
258 .halfword = { ir >> 16, ir } in mips_dsemul()
267 fr.emul = ir; in mips_dsemul()
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| /arch/mips/kernel/ |
| D | mips-r2-to-r6-emul.c | 78 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir) in mipsr6_emul() argument
80 switch (MIPSInst_OPCODE(ir)) { in mipsr6_emul()
82 if (MIPSInst_RT(ir)) in mipsr6_emul()
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
85 (s32)MIPSInst_SIMM(ir); in mipsr6_emul()
91 if (MIPSInst_RT(ir)) in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
94 (s64)MIPSInst_SIMM(ir); in mipsr6_emul()
[all …]
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| /arch/parisc/math-emu/ |
| D | fpudispatch.c | 182 fpudispatch(u_int ir, u_int excp_code, u_int holder, u_int fpregs[]) in fpudispatch() argument
194 class = get_class(ir); in fpudispatch()
197 subop = get_subop1_PA2_0(ir); in fpudispatch()
199 subop = get_subop1_PA1_1(ir); in fpudispatch()
202 subop = get_subop(ir); in fpudispatch()
209 return(decode_0c(ir,class,subop,fpregs)); in fpudispatch()
211 return(decode_0e(ir,class,subop,fpregs)); in fpudispatch()
213 return(decode_06(ir,fpregs)); in fpudispatch()
215 return(decode_26(ir,fpregs)); in fpudispatch()
217 return(decode_2e(ir,fpregs)); in fpudispatch()
[all …]
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| /arch/arm/boot/dts/rockchip/ |
| D | rk3288-firefly.dts | 14 &ir {
25 ir {
26 ir_int: ir-int {
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| D | rk3288-firefly-beta.dts | 14 &ir {
25 ir {
26 ir_int: ir-int {
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| D | rk3288-rock2-square.dts | 57 ir: ir-receiver { label
58 compatible = "gpio-ir-receiver";
204 ir {
205 ir_int: ir-int {
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| D | rk3288-r89.dts | 44 ir: ir-receiver { label
45 compatible = "gpio-ir-receiver";
295 ir {
296 ir_int: ir-int {
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| D | rk3066a-rayeager.dts | 25 ir: ir-receiver { label
26 compatible = "gpio-ir-receiver";
350 ir {
351 ir_int: ir-int {
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| D | rk3188-radxarock.dts | 74 ir_recv: ir-receiver {
75 compatible = "gpio-ir-receiver";
333 ir-receiver {
334 ir_recv_pin: ir-recv-pin {
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| /arch/arm64/boot/dts/rockchip/ |
| D | rk3308-roc-cc.dts | 22 ir-receiver {
23 compatible = "gpio-ir-receiver";
30 compatible = "pwm-ir-tx";
39 linux,default-trigger = "ir-power-click";
46 linux,default-trigger = "ir-user-click";
158 ir-receiver {
159 ir_recv_pin: ir-recv-pin {
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| D | rk3328-roc-pc.dts | 28 ir-receiver {
29 compatible = "gpio-ir-receiver";
53 ir {
54 ir_int: ir-int {
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| D | rk3399-nanopc-t4.dts | 49 ir-receiver {
50 compatible = "gpio-ir-receiver";
104 ir {
105 ir_rx: ir-rx {
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| D | rk3368-geekbox.dts | 34 ir: ir-receiver { label
35 compatible = "gpio-ir-receiver";
238 ir {
239 ir_int: ir-int {
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| D | rk3368-r88.dts | 59 ir: ir-receiver { label
60 compatible = "gpio-ir-receiver";
265 ir {
266 ir_int: ir-int {
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| D | rk3318-a95x-z2.dts | 35 ir-receiver {
36 compatible = "gpio-ir-receiver";
227 ir {
228 ir_int: ir-int {
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| D | rk3328-rock64.dts | 61 ir-receiver {
62 compatible = "gpio-ir-receiver";
299 ir {
300 ir_int: ir-int {
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| /arch/riscv/include/asm/ |
| D | barrier.h | 24 #define rmb() RISCV_FENCE(ir,ir)
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| /arch/x86/kvm/svm/ |
| D | avic.c | 748 struct amd_svm_iommu_ir *ir; in avic_set_pi_irte_mode() local
763 list_for_each_entry(ir, &svm->ir_list, node) { in avic_set_pi_irte_mode()
765 ret = amd_iommu_activate_guest_mode(ir->data); in avic_set_pi_irte_mode()
767 ret = amd_iommu_deactivate_guest_mode(ir->data); in avic_set_pi_irte_mode()
796 struct amd_svm_iommu_ir *ir; in svm_ir_list_add() local
823 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT); in svm_ir_list_add()
824 if (!ir) { in svm_ir_list_add()
828 ir->data = pi->ir_data; in svm_ir_list_add()
843 list_add(&ir->node, &svm->ir_list); in svm_ir_list_add()
1005 struct amd_svm_iommu_ir *ir; in avic_update_iommu_vcpu_affinity() local
[all …]
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| /arch/x86/pci/ |
| D | irq.c | 129 struct irt_routing_table *ir; in pirq_convert_irt_table() local
135 ir = (struct irt_routing_table *)addr; in pirq_convert_irt_table()
136 if (ir->signature != IRT_SIGNATURE || !ir->used || ir->size < ir->used) in pirq_convert_irt_table()
139 size = struct_size(ir, slots, ir->used); in pirq_convert_irt_table()
144 __pa(ir)); in pirq_convert_irt_table()
146 size = struct_size(rt, slots, ir->used); in pirq_convert_irt_table()
154 rt->exclusive_irqs = ir->exclusive_irqs; in pirq_convert_irt_table()
155 for (i = 0; i < ir->used; i++) in pirq_convert_irt_table()
156 rt->slots[i] = ir->slots[i]; in pirq_convert_irt_table()
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| /arch/arm/boot/dts/allwinner/ |
| D | suniv-f1c100s.dtsi | 278 ir: ir@1c22c00 { label
279 compatible = "allwinner,suniv-f1c100s-ir",
280 "allwinner,sun6i-a31-ir";
283 clock-names = "apb", "ir";
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| /arch/mips/include/asm/ |
| D | dsemul.h | 37 extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
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| /arch/arm/boot/dts/marvell/ |
| D | dove-cubox.dts | 53 ir_recv: ir-receiver {
54 compatible = "gpio-ir-receiver";
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| /arch/powerpc/platforms/4xx/ |
| D | gpio.c | 34 __be32 ir; member
63 return !!(in_be32(®s->ir) & GPIO_MASK(gpio)); in ppc4xx_gpio_get()
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| /arch/arm64/boot/dts/amlogic/ |
| D | meson-gxl-s905w-tx3-mini.dts | 24 &ir {
|