| /arch/powerpc/sysdev/ |
| D | 6xx-suspend.S | 19 mfspr r5, SPRN_HID0
20 rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
21 oris r5, r5, HID0_SLEEP@h
22 mtspr SPRN_HID0, r5
25 lis r5, ret_from_standby@h
26 ori r5, r5, ret_from_standby@l
27 mtlr r5
33 mfmsr r5
34 ori r5, r5, MSR_EE
35 oris r5, r5, MSR_POW@h
[all …]
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| /arch/arm/lib/ |
| D | csumpartialcopygeneric.S | 112 1: load4l r4, r5, r6, r7
113 stmia dst!, {r4, r5, r6, r7}
115 adcs sum, sum, r5
126 load2l r4, r5
127 stmia dst!, {r4, r5}
129 adcs sum, sum, r5
141 mov r5, r4, get_byte_0
144 strb r5, [dst], #1
145 mov r5, r4, get_byte_1
146 strb r5, [dst], #1
[all …]
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| /arch/powerpc/kernel/ |
| D | optprobes_head.S | 50 mfmsr r5
51 PPC_STL r5,_MSR(r1)
52 li r5,0x700
53 PPC_STL r5,_TRAP(r1)
54 li r5,0
55 PPC_STL r5,ORIG_GPR3(r1)
56 PPC_STL r5,RESULT(r1)
57 mfctr r5
58 PPC_STL r5,_CTR(r1)
59 mflr r5
[all …]
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| D | misc_32.S | 37 mulhwu r4,r4,r5
40 mullw r7,r10,r5
44 mullw r9,r3,r5
45 mulhwu r10,r3,r5
97 lwz r5,CPU_SPEC_SETUP(r4)
98 cmpwi 0,r5,0
99 add r5,r5,r3
101 mtctr r5
119 mfspr r5,SPRN_HID0
120 rlwinm r5,r5,0,27,25
[all …]
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| /arch/sh/lib/ |
| D | udivsi3_i4i-Os.S | 29 extu.w r5,r0
30 cmp/eq r5,r0
35 mov.l r5,@-r15
36 shll16 r5
38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
[all …]
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| D | udivsi3_i4i.S | 46 cmp/hi r1,r5
47 extu.w r5,r1
49 cmp/eq r5,r1
52 mov r5,r1
53 shll16 r5
55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
65 mov.b @(r0,r5),r1
[all …]
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| D | udivsi3.S | 16 div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4
19 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
22 div1 r5,r4; rotcl r0
23 div1 r5,r4; rotcl r0
24 div1 r5,r4; rotcl r0
25 rts; div1 r5,r4
29 extu.w r5,r0
30 cmp/eq r5,r0
36 shll16 r5
[all …]
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| D | movmem.S | 31 mov.l @(48,r5),r0
34 mov.l @(60,r5),r0
38 mov.l @(56,r5),r0
42 mov.l @(52,r5),r0
43 add #64,r5
55 mov.l @(52,r5),r0
64 mov.l @(60,r5),r0
70 mov.l @(56,r5),r0
76 mov.l @(52,r5),r0
82 mov.l @(48,r5),r0
[all …]
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| D | memset-sh4.S | 29 mov.b r5,@-r4
31 extu.b r5,r5
32 swap.b r5,r0 ! V0
33 or r0,r5 ! VV
34 swap.w r5,r0 ! VV00
35 or r0,r5 ! VVVV
55 10: mov.l r5,@-r4
66 mov r5, r0
69 mov.l r5,@(4, r4)
70 mov.l r5,@(8, r4)
[all …]
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| /arch/microblaze/kernel/ |
| D | hw_exception_handler.S | 84 lwi r5, r1, 0; \
85 mts rmsr, r5; \
89 lwi r5, r1, PT_R5; \
322 swi r5, r1, PT_R5
329 mfs r5, rmsr;
331 swi r5, r1, 0;
337 andi r5, r4, 0x1F; /* Extract ESR[EXC] */
340 addk r6, r5, r5; /* << 1 */
345 lwi r5, r0, TOPHYS(exception_debug_table)
346 addi r5, r5, 1
[all …]
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| /arch/powerpc/boot/ |
| D | string.S | 13 addi r5,r3,-1
17 stbu r0,1(r5)
23 cmpwi 0,r5,0
25 mtctr r5
36 addi r5,r3,-1
38 1: lbzu r0,1(r5)
41 addi r5,r5,-1
44 stbu r0,1(r5)
61 addi r5,r3,-1
63 1: lbzu r3,1(r5)
[all …]
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| D | util.S | 44 mflr r5
47 mtlr r5
48 addis r5,r6,(timebase_period_ns-0b)@ha
49 lwz r5,(timebase_period_ns-0b)@l(r5)
50 add r4,r4,r5
52 divw r4,r4,r5 /* BUS ticks */
53 1: MFTBU(r5)
56 cmpw 0,r5,r7
59 addze r8,r5
60 2: MFTBU(r5)
[all …]
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| /arch/microblaze/lib/ |
| D | fastcopy.S | 41 addi r3, r5, 0
48 andi r4, r5, 3 /* n = d & 3 */
59 sbi r11, r5, 0 /* *d = h */
61 addi r5, r5, 1 /* d++ */
84 swi r9, r5, 0 /* *(d + 0) = t1 */
85 swi r10, r5, 4 /* *(d + 4) = t2 */
86 swi r11, r5, 8 /* *(d + 8) = t3 */
87 swi r12, r5, 12 /* *(d + 12) = t4 */
92 swi r9, r5, 16 /* *(d + 16) = t1 */
93 swi r10, r5, 20 /* *(d + 20) = t2 */
[all …]
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| D | umodsi3.S | 25 beqid r5, result_is_zero /* result is zero */
31 rsub r18, r5, r6
35 xor r18, r5, r6
37 addik r3, r5, 0
40 rsub r18, r5, r6 /* microblazecmp */
48 and r5, r5, r18
51 rsub r3, r6, r5
54 blti r5, div2
56 add r5, r5, r5 /* left shift logical r5 */
57 bgeid r5, div1
[all …]
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| D | divsi3.S | 24 beqi r5, result_is_zero /* result is zero */
25 bgeid r5, r5_pos
26 xor r28, r5, r6 /* get the sign of the result */
27 rsubi r5, r5, 0 /* make r5 positive */
38 blti r5, div2 /* this traps r5 == 0x80000000 */
40 add r5, r5, r5 /* left shift logical r5 */
41 bgtid r5, div1
45 add r5, r5, r5
|
| /arch/arm/mm/ |
| D | pv-fixup-asm.S | 33 1: ldrd r4, r5, [r7]
35 adc r5, r5, r1
36 strd r4, r5, [r7], #1 << L2_ORDER
44 ldrd r4, r5, [r7]
46 adc r5, r5, r1
47 strd r4, r5, [r7], #1 << L2_ORDER
48 ldrd r4, r5, [r7]
50 adc r5, r5, r1
51 strd r4, r5, [r7]
56 2: ldrd r4, r5, [r7]
[all …]
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| /arch/powerpc/lib/ |
| D | copy_32.S | 45 addi r5,r5,-(16 * n); \
48 addi r5,r5,-(16 * n); \
67 rlwinm. r0 ,r5, 31, 1, 31
74 2: andi. r0, r5, 1
91 cmplwi 0,r5,4
100 add r5,r0,r5
111 add r8,r7,r5
126 clrlwi r5,r8,32-LG_CACHELINE_BYTES
127 addi r5,r5,4
129 2: srwi r0,r5,2
[all …]
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| D | mem_64.S | 25 cmplw cr1,r5,r0
37 cmplw cr1,r5,r0 /* do we get that far? */
43 subf r5,r0,r5
53 3: srdi. r0,r5,6
54 clrldi r5,r5,58
68 5: srwi. r0,r5,3
69 clrlwi r5,r5,29
85 8: cmpwi r5,0
86 PPC_MTOCRF(1,r5)
106 rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
[all …]
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| D | checksum_32.S | 36 adde r5,r5,r0
42 adde r5,r5,r0
49 adde r5,r5,r0
51 adde r5,r5,r6
53 adde r5,r5,r7
56 adde r5,r5,r8
58 adde r5,r5,r0
60 adde r5,r5,r6
62 adde r5,r5,r7
64 23: adde r5,r5,r8
[all …]
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| /arch/powerpc/platforms/83xx/ |
| D | suspend-asm.S | 63 lwz r5, 0(r4)
66 stw r5, SS_MEMSAVE+0(r3)
69 mfspr r5, SPRN_HID0
73 stw r5, SS_HID+0(r3)
78 mfspr r5, SPRN_IABR2
85 stw r5, SS_IABR+4(r3)
92 mfspr r5, SPRN_SPRG1
98 stw r5, SS_SPRG+4(r3)
104 mfspr r5, SPRN_SPRG5
109 stw r5, SS_SPRG+20(r3)
[all …]
|
| /arch/powerpc/mm/book3s32/ |
| D | hash_low.S | 71 lwz r5,PGDIR(r8) /* virt page-table root */
73 lis r5,swapper_pg_dir@ha /* if kernel address, use */
74 addi r5,r5,swapper_pg_dir@l /* kernel page table */
76 112: tophys(r5, r5)
78 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
79 lwz r8,0(r5) /* get pmd entry */
83 lwzx r8,r8,r5 /* Get L1 entry */
115 mfsrin r5,r4
117 rlwinm r5,r5,12,_PAGE_RW /* Ks => _PAGE_RW */
118 andc r5,r5,r0 /* Ks & ~MSR[PR] */
[all …]
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| /arch/arc/kernel/ |
| D | head.S | 26 lr r5, [ARC_REG_IC_BCR]
27 breq r5, 0, 1f ; I$ doesn't exist
39 lr r5, [ARC_REG_DC_CTRL]
40 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
42 bclr r5, r5, 0 ; Enable (+Inv)
44 bset r5, r5, 0 ; Disable (+Inv)
46 sr r5, [ARC_REG_DC_CTRL]
54 lr r5, [status32]
56 bset r5, r5, STATUS_AD_BIT
59 bclr r5, r5, STATUS_AD_BIT
[all …]
|
| /arch/arm/mach-omap1/ |
| D | sleep.S | 78 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
79 bic r5, r5, #PDE_BIT & 0xff
80 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
83 and r5, r5, #PWD_EN_BIT & 0xff
84 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
87 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
88 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
89 orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff
90 str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
93 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
[all …]
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| /arch/arc/lib/ |
| D | memcpy-archs.S | 51 ldb.ab r5, [r1,1]
53 stb.ab r5, [r3,1]
79 ldb.ab r5, [r1,1]
80 stb.ab r5, [r3,1]
92 ldb.ab r5, [r1, 1]
102 MERGE_2 (r5, r5, 24)
103 or r5, r5, r6
112 or r7, r7, r5
113 SHIFT_2 (r5, r6, 8)
116 or r9, r9, r5
[all …]
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| /arch/s390/lib/ |
| D | mem.S | 24 la %r5,1(%r4,%r3)
25 clgr %r2,%r5
37 larl %r5,.Lmemmove_mvc
38 ex %r4,0(%r5)
95 srlg %r5,%r4,8
96 ltgr %r5,%r5
102 brctg %r5,.Lmemset_fill_loop
105 larl %r5,.Lmemset_mvc
106 ex %r4,0(%r5)
130 srlg %r5,%r4,8
[all …]
|