Home
last modified time | relevance | path

Searched refs:ADF_CSR_RD (Results 1 – 14 of 14) sorted by relevance

/drivers/crypto/intel/qat/qat_common/
Dadf_gen4_pm.c32 msg = ADF_CSR_RD(pmisc, ADF_GEN4_PM_HOST_MSG); in send_host_msg()
49 return read_poll_timeout(ADF_CSR_RD, msg, in send_host_msg()
77 val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2); in pm_bh_handler()
93 errmsk2 = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2); in adf_gen4_handle_pm_interrupt()
97 errsou2 = ADF_CSR_RD(pmisc, ADF_GEN4_ERRSOU2); in adf_gen4_handle_pm_interrupt()
102 val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2); in adf_gen4_handle_pm_interrupt()
106 val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT); in adf_gen4_handle_pm_interrupt()
133 val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT); in adf_gen4_enable_pm()
141 val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2); in adf_gen4_enable_pm()
Dadf_gen4_pfvf.c44 val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) & ~vf_mask; in adf_gen4_enable_vf2pf_interrupts()
58 sources = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_SOU); in adf_gen4_disable_pending_vf2pf_interrupts()
63 disabled = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK); in adf_gen4_disable_pending_vf2pf_interrupts()
101 ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & ADF_PFVF_INT), in adf_gen4_pfvf_send()
120 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen4_pfvf_recv()
Dadf_gen2_pfvf.c58 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_enable_vf2pf_interrupts()
67 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_disable_all_vf2pf_interrupts()
78 errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3); in adf_gen2_disable_pending_vf2pf_interrupts()
85 errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3); in adf_gen2_disable_pending_vf2pf_interrupts()
214 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_send()
225 ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & int_bit), in adf_gen2_pfvf_send()
285 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_recv()
Dadf_gen2_hw_data.h32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
38 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
88 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
94 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
Dadf_gen4_hw_data.h29 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
33 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
37 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
Dadf_gen2_hw_data.c36 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i)); in adf_gen2_enable_error_correction()
39 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_AE_MISC_CONTROL(i)); in adf_gen2_enable_error_correction()
46 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_UERRSSMSH(i)); in adf_gen2_enable_error_correction()
49 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_CERRSSMSH(i)); in adf_gen2_enable_error_correction()
Dicp_qat_hal.h128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
Dadf_vf_isr.c142 v_int = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTSOU_OFFSET); in adf_isr()
145 v_mask = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTMSK_OFFSET); in adf_isr()
Dadf_admin.c125 if (ADF_CSR_RD(mailbox, mb_offset) == 1) { in adf_put_admin_msg_sync()
133 ret = read_poll_timeout(ADF_CSR_RD, status, status == 0, in adf_put_admin_msg_sync()
Dadf_gen4_hw_data.c157 ret = read_poll_timeout(ADF_CSR_RD, status, in reset_ring_pair()
Dadf_accel_devices.h246 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) macro
Dqat_hal.c453 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
457 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
463 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
/drivers/crypto/intel/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.c127 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in enable_vf2pf_interrupts()
134 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5) in enable_vf2pf_interrupts()
145 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in disable_all_vf2pf_interrupts()
150 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5) in disable_all_vf2pf_interrupts()
162 errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3); in disable_pending_vf2pf_interrupts()
163 errsou5 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU5); in disable_pending_vf2pf_interrupts()
171 errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3); in disable_pending_vf2pf_interrupts()
172 errmsk5 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5); in disable_pending_vf2pf_interrupts()
/drivers/crypto/intel/qat/qat_4xxx/
Dadf_4xxx_hw_data.c354 csr = ADF_CSR_RD(addr, ADF_GEN4_ERRMSK2); in adf_init_device()
362 ret = read_poll_timeout(ADF_CSR_RD, status, in adf_init_device()