1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2020 Intel Corporation */
3 #include <linux/iopoll.h>
4 #include "adf_accel_devices.h"
5 #include "adf_common_drv.h"
6 #include "adf_gen4_hw_data.h"
7
build_csr_ring_base_addr(dma_addr_t addr,u32 size)8 static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
9 {
10 return BUILD_RING_BASE_ADDR(addr, size);
11 }
12
read_csr_ring_head(void __iomem * csr_base_addr,u32 bank,u32 ring)13 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
14 {
15 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
16 }
17
write_csr_ring_head(void __iomem * csr_base_addr,u32 bank,u32 ring,u32 value)18 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
19 u32 value)
20 {
21 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
22 }
23
read_csr_ring_tail(void __iomem * csr_base_addr,u32 bank,u32 ring)24 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
25 {
26 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
27 }
28
write_csr_ring_tail(void __iomem * csr_base_addr,u32 bank,u32 ring,u32 value)29 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
30 u32 value)
31 {
32 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
33 }
34
read_csr_e_stat(void __iomem * csr_base_addr,u32 bank)35 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
36 {
37 return READ_CSR_E_STAT(csr_base_addr, bank);
38 }
39
write_csr_ring_config(void __iomem * csr_base_addr,u32 bank,u32 ring,u32 value)40 static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,
41 u32 value)
42 {
43 WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
44 }
45
write_csr_ring_base(void __iomem * csr_base_addr,u32 bank,u32 ring,dma_addr_t addr)46 static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
47 dma_addr_t addr)
48 {
49 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
50 }
51
write_csr_int_flag(void __iomem * csr_base_addr,u32 bank,u32 value)52 static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank,
53 u32 value)
54 {
55 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
56 }
57
write_csr_int_srcsel(void __iomem * csr_base_addr,u32 bank)58 static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
59 {
60 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
61 }
62
write_csr_int_col_en(void __iomem * csr_base_addr,u32 bank,u32 value)63 static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value)
64 {
65 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
66 }
67
write_csr_int_col_ctl(void __iomem * csr_base_addr,u32 bank,u32 value)68 static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
69 u32 value)
70 {
71 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
72 }
73
write_csr_int_flag_and_col(void __iomem * csr_base_addr,u32 bank,u32 value)74 static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
75 u32 value)
76 {
77 WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
78 }
79
write_csr_ring_srv_arb_en(void __iomem * csr_base_addr,u32 bank,u32 value)80 static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
81 u32 value)
82 {
83 WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
84 }
85
adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops * csr_ops)86 void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
87 {
88 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
89 csr_ops->read_csr_ring_head = read_csr_ring_head;
90 csr_ops->write_csr_ring_head = write_csr_ring_head;
91 csr_ops->read_csr_ring_tail = read_csr_ring_tail;
92 csr_ops->write_csr_ring_tail = write_csr_ring_tail;
93 csr_ops->read_csr_e_stat = read_csr_e_stat;
94 csr_ops->write_csr_ring_config = write_csr_ring_config;
95 csr_ops->write_csr_ring_base = write_csr_ring_base;
96 csr_ops->write_csr_int_flag = write_csr_int_flag;
97 csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
98 csr_ops->write_csr_int_col_en = write_csr_int_col_en;
99 csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
100 csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
101 csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
102 }
103 EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops);
104
adf_gen4_unpack_ssm_wdtimer(u64 value,u32 * upper,u32 * lower)105 static inline void adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper,
106 u32 *lower)
107 {
108 *lower = lower_32_bits(value);
109 *upper = upper_32_bits(value);
110 }
111
adf_gen4_set_ssm_wdtimer(struct adf_accel_dev * accel_dev)112 void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)
113 {
114 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);
115 u64 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;
116 u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
117 u32 ssm_wdt_pke_high = 0;
118 u32 ssm_wdt_pke_low = 0;
119 u32 ssm_wdt_high = 0;
120 u32 ssm_wdt_low = 0;
121
122 /* Convert 64bit WDT timer value into 32bit values for
123 * mmio write to 32bit CSRs.
124 */
125 adf_gen4_unpack_ssm_wdtimer(timer_val, &ssm_wdt_high, &ssm_wdt_low);
126 adf_gen4_unpack_ssm_wdtimer(timer_val_pke, &ssm_wdt_pke_high,
127 &ssm_wdt_pke_low);
128
129 /* Enable WDT for sym and dc */
130 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low);
131 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high);
132 /* Enable WDT for pke */
133 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low);
134 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high);
135 }
136 EXPORT_SYMBOL_GPL(adf_gen4_set_ssm_wdtimer);
137
adf_pfvf_comms_disabled(struct adf_accel_dev * accel_dev)138 int adf_pfvf_comms_disabled(struct adf_accel_dev *accel_dev)
139 {
140 return 0;
141 }
142 EXPORT_SYMBOL_GPL(adf_pfvf_comms_disabled);
143
reset_ring_pair(void __iomem * csr,u32 bank_number)144 static int reset_ring_pair(void __iomem *csr, u32 bank_number)
145 {
146 u32 status;
147 int ret;
148
149 /* Write rpresetctl register BIT(0) as 1
150 * Since rpresetctl registers have no RW fields, no need to preserve
151 * values for other bits. Just write directly.
152 */
153 ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number),
154 ADF_WQM_CSR_RPRESETCTL_RESET);
155
156 /* Read rpresetsts register and wait for rp reset to complete */
157 ret = read_poll_timeout(ADF_CSR_RD, status,
158 status & ADF_WQM_CSR_RPRESETSTS_STATUS,
159 ADF_RPRESET_POLL_DELAY_US,
160 ADF_RPRESET_POLL_TIMEOUT_US, true,
161 csr, ADF_WQM_CSR_RPRESETSTS(bank_number));
162 if (!ret) {
163 /* When rp reset is done, clear rpresetsts */
164 ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number),
165 ADF_WQM_CSR_RPRESETSTS_STATUS);
166 }
167
168 return ret;
169 }
170
adf_gen4_ring_pair_reset(struct adf_accel_dev * accel_dev,u32 bank_number)171 int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number)
172 {
173 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
174 u32 etr_bar_id = hw_data->get_etr_bar_id(hw_data);
175 void __iomem *csr;
176 int ret;
177
178 if (bank_number >= hw_data->num_banks)
179 return -EINVAL;
180
181 dev_dbg(&GET_DEV(accel_dev),
182 "ring pair reset for bank:%d\n", bank_number);
183
184 csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr;
185 ret = reset_ring_pair(csr, bank_number);
186 if (ret)
187 dev_err(&GET_DEV(accel_dev),
188 "ring pair reset failed (timeout)\n");
189 else
190 dev_dbg(&GET_DEV(accel_dev), "ring pair reset successful\n");
191
192 return ret;
193 }
194 EXPORT_SYMBOL_GPL(adf_gen4_ring_pair_reset);
195