| /drivers/gpu/drm/nouveau/nvkm/core/ |
| D | event.c | 26 nvkm_event_put(struct nvkm_event *event, u32 types, int index) in nvkm_event_put() argument
28 assert_spin_locked(&event->refs_lock); in nvkm_event_put()
30 nvkm_trace(event->subdev, "event: decr %08x on %d\n", types, index); in nvkm_event_put()
34 if (--event->refs[index * event->types_nr + type] == 0) { in nvkm_event_put()
35 nvkm_trace(event->subdev, "event: blocking %d on %d\n", type, index); in nvkm_event_put()
36 if (event->func->fini) in nvkm_event_put()
37 event->func->fini(event, 1 << type, index); in nvkm_event_put()
43 nvkm_event_get(struct nvkm_event *event, u32 types, int index) in nvkm_event_get() argument
45 assert_spin_locked(&event->refs_lock); in nvkm_event_get()
47 nvkm_trace(event->subdev, "event: incr %08x on %d\n", types, index); in nvkm_event_get()
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| /drivers/perf/ |
| D | riscv_pmu.c | 21 static bool riscv_perf_user_access(struct perf_event *event) in riscv_perf_user_access() argument
23 return ((event->attr.type == PERF_TYPE_HARDWARE) || in riscv_perf_user_access()
24 (event->attr.type == PERF_TYPE_HW_CACHE) || in riscv_perf_user_access()
25 (event->attr.type == PERF_TYPE_RAW)) && in riscv_perf_user_access()
26 !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT) && in riscv_perf_user_access()
27 (event->hw.idx != -1); in riscv_perf_user_access()
30 void arch_perf_update_userpage(struct perf_event *event, in arch_perf_update_userpage() argument
40 userpg->cap_user_rdpmc = riscv_perf_user_access(event); in arch_perf_update_userpage()
49 userpg->pmc_width = to_riscv_pmu(event->pmu)->ctr_get_width(event->hw.idx) + 1; in arch_perf_update_userpage()
147 u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event) in riscv_pmu_ctr_get_width_mask() argument
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| D | qcom_l3_pmu.c | 136 static inline u32 get_event_type(struct perf_event *event) in get_event_type() argument
138 return (event->attr.config) & L3_EVTYPE_MASK; in get_event_type()
141 static inline bool event_uses_long_counter(struct perf_event *event) in event_uses_long_counter() argument
143 return !!(event->attr.config & BIT_ULL(L3_EVENT_LC_BIT)); in event_uses_long_counter()
146 static inline int event_num_counters(struct perf_event *event) in event_num_counters() argument
148 return event_uses_long_counter(event) ? 2 : 1; in event_num_counters()
175 void (*start)(struct perf_event *event);
177 void (*stop)(struct perf_event *event, int flags);
179 void (*update)(struct perf_event *event);
193 static void qcom_l3_cache__64bit_counter_start(struct perf_event *event) in qcom_l3_cache__64bit_counter_start() argument
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| D | arm_pmu.c | 108 static inline u64 arm_pmu_event_max_period(struct perf_event *event) in arm_pmu_event_max_period() argument
110 if (event->hw.flags & ARMPMU_EVT_64BIT) in arm_pmu_event_max_period()
112 else if (event->hw.flags & ARMPMU_EVT_63BIT) in arm_pmu_event_max_period()
114 else if (event->hw.flags & ARMPMU_EVT_47BIT) in arm_pmu_event_max_period()
174 armpmu_map_event(struct perf_event *event, in armpmu_map_event() argument
182 u64 config = event->attr.config; in armpmu_map_event()
183 int type = event->attr.type; in armpmu_map_event()
185 if (type == event->pmu->type) in armpmu_map_event()
200 int armpmu_event_set_period(struct perf_event *event) in armpmu_event_set_period() argument
202 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_event_set_period()
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| D | arm_dmc620_pmu.c | 217 GEN_PMU_FORMAT_ATTR(event);
278 unsigned int dmc620_event_to_counter_control(struct perf_event *event) in dmc620_event_to_counter_control() argument
280 struct perf_event_attr *attr = &event->attr; in dmc620_event_to_counter_control()
286 ATTR_CFG_GET_FLD(attr, event)); in dmc620_event_to_counter_control()
293 static int dmc620_get_event_idx(struct perf_event *event) in dmc620_get_event_idx() argument
295 struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); in dmc620_get_event_idx()
298 if (ATTR_CFG_GET_FLD(&event->attr, clkdiv2)) { in dmc620_get_event_idx()
316 u64 dmc620_pmu_read_counter(struct perf_event *event) in dmc620_pmu_read_counter() argument
318 struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); in dmc620_pmu_read_counter()
321 event->hw.idx, DMC620_PMU_COUNTERn_VALUE); in dmc620_pmu_read_counter()
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| D | arm_dsu_pmu.c | 176 DSU_FORMAT_ATTR(event, "config:0-31"),
248 static inline u64 dsu_pmu_read_counter(struct perf_event *event) in dsu_pmu_read_counter() argument
252 struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); in dsu_pmu_read_counter()
253 int idx = event->hw.idx; in dsu_pmu_read_counter()
260 dev_err(event->pmu->dev, in dsu_pmu_read_counter()
275 static void dsu_pmu_write_counter(struct perf_event *event, u64 val) in dsu_pmu_write_counter() argument
278 struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu); in dsu_pmu_write_counter()
279 int idx = event->hw.idx; in dsu_pmu_write_counter()
286 dev_err(event->pmu->dev, in dsu_pmu_write_counter()
300 struct perf_event *event) in dsu_pmu_get_event_idx() argument
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| D | alibaba_uncore_drw_pmu.c | 111 #define GET_DRW_EVENTID(event) FIELD_GET(DRW_CONFIG_EVENTID, (event)->attr.config) argument
209 ALI_DRW_PMU_FORMAT_ATTR(event, "config:0-7"),
274 static int ali_drw_get_counter_idx(struct perf_event *event) in ali_drw_get_counter_idx() argument
276 struct ali_drw_pmu *drw_pmu = to_ali_drw_pmu(event->pmu); in ali_drw_get_counter_idx()
288 static u64 ali_drw_pmu_read_counter(struct perf_event *event) in ali_drw_pmu_read_counter() argument
290 struct ali_drw_pmu *drw_pmu = to_ali_drw_pmu(event->pmu); in ali_drw_pmu_read_counter()
293 if (GET_DRW_EVENTID(event) == ALI_DRW_PMU_CYCLE_EVT_ID) { in ali_drw_pmu_read_counter()
302 ALI_DRW_PMU_COMMON_COUNTERn(event->hw.idx)); in ali_drw_pmu_read_counter()
305 static void ali_drw_pmu_event_update(struct perf_event *event) in ali_drw_pmu_event_update() argument
307 struct hw_perf_event *hwc = &event->hw; in ali_drw_pmu_event_update()
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| D | thunderx2_pmu.c | 111 void (*init_cntr_base)(struct perf_event *event,
113 void (*stop_event)(struct perf_event *event);
114 void (*start_event)(struct perf_event *event, int flags);
137 TX2_PMU_FORMAT_ATTR(event, event, "config:0-4");
138 TX2_PMU_FORMAT_ATTR(event_ccpi2, event, "config:0-9");
322 static void init_cntr_base_l3c(struct perf_event *event, in init_cntr_base_l3c() argument
325 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_l3c()
328 tx2_pmu = pmu_to_tx2_pmu(event->pmu); in init_cntr_base_l3c()
333 + L3C_COUNTER_CTL + (8 * GET_COUNTERID(event, cmask)); in init_cntr_base_l3c()
335 + L3C_COUNTER_DATA + (8 * GET_COUNTERID(event, cmask)); in init_cntr_base_l3c()
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| D | arm_pmuv3.c | 301 PMU_FORMAT_ATTR(event, "config:0-15");
307 static inline bool armv8pmu_event_is_64bit(struct perf_event *event) in armv8pmu_event_is_64bit() argument
309 return event->attr.config1 & 0x1; in armv8pmu_event_is_64bit()
312 static inline bool armv8pmu_event_want_user_access(struct perf_event *event) in armv8pmu_event_want_user_access() argument
314 return event->attr.config1 & 0x2; in armv8pmu_event_want_user_access()
404 static inline bool armv8pmu_event_has_user_read(struct perf_event *event) in armv8pmu_event_has_user_read() argument
406 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT; in armv8pmu_event_has_user_read()
414 static inline bool armv8pmu_event_is_chained(struct perf_event *event) in armv8pmu_event_is_chained() argument
416 int idx = event->hw.idx; in armv8pmu_event_is_chained()
417 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); in armv8pmu_event_is_chained()
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| D | qcom_l2_pmu.c | 75 #define L2_EVT_CODE(event) (((event) & L2_EVT_CODE_MASK) >> L2_EVT_CODE_SHIFT) argument
76 #define L2_EVT_GROUP(event) (((event) & L2_EVT_GRP_MASK) >> L2_EVT_GRP_SHIFT) argument
297 static void l2_cache_event_update(struct perf_event *event) in l2_cache_event_update() argument
299 struct hw_perf_event *hwc = &event->hw; in l2_cache_event_update()
316 local64_add(delta, &event->count); in l2_cache_event_update()
340 struct perf_event *event) in l2_cache_get_event_idx() argument
342 struct hw_perf_event *hwc = &event->hw; in l2_cache_get_event_idx()
375 struct perf_event *event) in l2_cache_clear_event_idx() argument
377 struct hw_perf_event *hwc = &event->hw; in l2_cache_clear_event_idx()
397 struct perf_event *event = cluster->events[idx]; in l2_cache_handle_irq() local
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| D | arm-ccn.c | 154 struct perf_event *event; member
235 static CCN_FORMAT_ATTR(event, "config:16-23");
268 u32 event; member
287 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
293 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
298 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
302 .type = CCN_TYPE_HNF, .event = _event, }
305 .type = CCN_TYPE_XP, .event = _event, \
314 .type = CCN_TYPE_RNI_3P, .event = _event, }
317 .type = CCN_TYPE_SBAS, .event = _event, }
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| D | fsl_imx8_ddr_perf.c | 272 PMU_FORMAT_ATTR(event, "config:0-7");
297 static bool ddr_perf_is_filtered(struct perf_event *event) in ddr_perf_is_filtered() argument
299 return event->attr.config == 0x41 || event->attr.config == 0x42; in ddr_perf_is_filtered()
302 static u32 ddr_perf_filter_val(struct perf_event *event) in ddr_perf_filter_val() argument
304 return event->attr.config1; in ddr_perf_filter_val()
317 static bool ddr_perf_is_enhanced_filtered(struct perf_event *event) in ddr_perf_is_enhanced_filtered() argument
320 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_is_enhanced_filtered()
324 ddr_perf_is_filtered(event); in ddr_perf_is_enhanced_filtered()
327 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event) in ddr_perf_alloc_counter() argument
336 if (event == EVENT_CYCLES_ID) { in ddr_perf_alloc_counter()
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| D | riscv_pmu_sbi.c | 35 PMU_FORMAT_ATTR(event, "config:0-47");
315 static uint8_t pmu_sbi_csr_index(struct perf_event *event) in pmu_sbi_csr_index() argument
317 return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; in pmu_sbi_csr_index()
320 static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) in pmu_sbi_get_filter_flags() argument
325 if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS) in pmu_sbi_get_filter_flags()
327 if (event->attr.exclude_kernel) in pmu_sbi_get_filter_flags()
329 if (event->attr.exclude_user) in pmu_sbi_get_filter_flags()
331 if (guest_events && event->attr.exclude_hv) in pmu_sbi_get_filter_flags()
333 if (event->attr.exclude_host) in pmu_sbi_get_filter_flags()
335 if (event->attr.exclude_guest) in pmu_sbi_get_filter_flags()
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| D | arm-cci.c | 190 #define CCI400_PMU_EVENT_SOURCE(event) \ argument
191 ((event >> CCI400_PMU_EVENT_SOURCE_SHIFT) & \
193 #define CCI400_PMU_EVENT_CODE(event) \ argument
194 ((event >> CCI400_PMU_EVENT_CODE_SHIFT) & CCI400_PMU_EVENT_CODE_MASK)
214 CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),
429 #define CCI5xx_PMU_EVENT_SOURCE(event) \ argument
430 ((event >> CCI5xx_PMU_EVENT_SOURCE_SHIFT) & CCI5xx_PMU_EVENT_SOURCE_MASK)
431 #define CCI5xx_PMU_EVENT_CODE(event) \ argument
432 ((event >> CCI5xx_PMU_EVENT_CODE_SHIFT) & CCI5xx_PMU_EVENT_CODE_MASK)
450 CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),
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| /drivers/firmware/ |
| D | arm_sdei.c | 77 struct sdei_event *event; member
82 #define CROSSCALL_INIT(arg, event) \ argument
84 arg.event = event; \
90 struct sdei_event *event) in sdei_do_local_call() argument
94 CROSSCALL_INIT(arg, event); in sdei_do_local_call()
101 struct sdei_event *event) in sdei_do_cross_call() argument
105 CROSSCALL_INIT(arg, event); in sdei_do_cross_call()
191 static int sdei_api_event_get_info(u32 event, u32 info, u64 *result) in sdei_api_event_get_info() argument
193 return invoke_sdei_fn(SDEI_1_0_FN_SDEI_EVENT_GET_INFO, event, info, 0, in sdei_api_event_get_info()
203 struct sdei_event *event; in sdei_event_create() local
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| /drivers/md/ |
| D | dm-uevent.c | 39 static void dm_uevent_free(struct dm_uevent *event) in dm_uevent_free() argument
41 kmem_cache_free(_dm_event_cache, event); in dm_uevent_free()
46 struct dm_uevent *event; in dm_uevent_alloc() local
48 event = kmem_cache_zalloc(_dm_event_cache, GFP_ATOMIC); in dm_uevent_alloc()
49 if (!event) in dm_uevent_alloc()
52 INIT_LIST_HEAD(&event->elist); in dm_uevent_alloc()
53 event->md = md; in dm_uevent_alloc()
55 return event; in dm_uevent_alloc()
65 struct dm_uevent *event; in dm_build_path_uevent() local
67 event = dm_uevent_alloc(md); in dm_build_path_uevent()
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| /drivers/perf/hisilicon/ |
| D | hisi_uncore_pmu.c | 65 static bool hisi_validate_event_group(struct perf_event *event) in hisi_validate_event_group() argument
67 struct perf_event *sibling, *leader = event->group_leader; in hisi_validate_event_group()
68 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu); in hisi_validate_event_group()
77 if (leader->pmu != event->pmu) in hisi_validate_event_group()
81 if (leader != event) in hisi_validate_event_group()
85 for_each_sibling_event(sibling, event->group_leader) { in hisi_validate_event_group()
88 if (sibling->pmu != event->pmu) in hisi_validate_event_group()
98 int hisi_uncore_pmu_get_event_idx(struct perf_event *event) in hisi_uncore_pmu_get_event_idx() argument
100 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu); in hisi_uncore_pmu_get_event_idx()
133 struct perf_event *event; in hisi_uncore_pmu_isr() local
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| D | hisi_pcie_pmu.c | 88 static u64 hisi_pcie_get_##_name(struct perf_event *event) \
90 return FIELD_GET(GENMASK(_hi, _lo), event->attr._config); \
93 HISI_PCIE_PMU_FILTER_ATTR(event, config, 16, 0);
180 static u32 hisi_pcie_get_real_event(struct perf_event *event) in hisi_pcie_get_real_event() argument
182 return hisi_pcie_get_event(event) & GENMASK(15, 0); in hisi_pcie_get_real_event()
219 static void hisi_pcie_pmu_config_filter(struct perf_event *event) in hisi_pcie_pmu_config_filter() argument
221 struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu); in hisi_pcie_pmu_config_filter()
222 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_config_filter()
227 reg |= FIELD_PREP(HISI_PCIE_EVENT_M, hisi_pcie_get_real_event(event)); in hisi_pcie_pmu_config_filter()
230 port = hisi_pcie_get_port(event); in hisi_pcie_pmu_config_filter()
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| D | hns3_pmu.c | 297 u32 event; member
325 static inline u64 hns3_pmu_get_##_name(struct perf_event *event) \
328 event->attr._config); \
379 struct hns3_pmu_event_attr *event; in hns3_pmu_event_show() local
383 event = eattr->var; in hns3_pmu_event_show()
385 return sysfs_emit(buf, "config=0x%x\n", event->event); in hns3_pmu_event_show()
392 struct hns3_pmu_event_attr *event; in hns3_pmu_filter_mode_show() local
397 event = eattr->var; in hns3_pmu_filter_mode_show()
400 if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_GLOBAL) in hns3_pmu_filter_mode_show()
402 if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT) in hns3_pmu_filter_mode_show()
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| /drivers/dma/idxd/ |
| D | perfmon.c | 37 DEFINE_PERFMON_FORMAT_ATTR(event, "config:4-31");
80 static bool is_idxd_event(struct idxd_pmu *idxd_pmu, struct perf_event *event) in is_idxd_event() argument
82 return &idxd_pmu->pmu == event->pmu; in is_idxd_event()
89 struct perf_event *event; in perfmon_collect_events() local
107 for_each_sibling_event(event, leader) { in perfmon_collect_events()
108 if (!is_idxd_event(idxd_pmu, event) || in perfmon_collect_events()
109 event->state <= PERF_EVENT_STATE_OFF) in perfmon_collect_events()
115 idxd_pmu->event_list[n] = event; in perfmon_collect_events()
124 struct perf_event *event, int idx) in perfmon_assign_hw_event() argument
127 struct hw_perf_event *hwc = &event->hw; in perfmon_assign_hw_event()
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| /drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| D | fweh.c | 85 struct brcmf_fweh_queue_item *event) in brcmf_fweh_queue_event() argument
90 list_add_tail(&event->q, &fweh->event_q); in brcmf_fweh_queue_event()
194 struct brcmf_fweh_queue_item *event = NULL; in brcmf_fweh_dequeue_event() local
199 event = list_first_entry(&fweh->event_q, in brcmf_fweh_dequeue_event()
201 list_del(&event->q); in brcmf_fweh_dequeue_event()
205 return event; in brcmf_fweh_dequeue_event()
218 struct brcmf_fweh_queue_item *event; in brcmf_fweh_event_worker() local
226 while ((event = brcmf_fweh_dequeue_event(fweh))) { in brcmf_fweh_event_worker()
228 brcmf_fweh_event_name(event->code), event->code, in brcmf_fweh_event_worker()
229 event->emsg.ifidx, event->emsg.bsscfgidx, in brcmf_fweh_event_worker()
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| /drivers/net/ethernet/huawei/hinic/ |
| D | hinic_devlink.c | 319 struct hinic_fault_event *event) in chip_fault_show() argument
326 fault_level = (event->event.chip.err_level < FAULT_LEVEL_MAX) ? in chip_fault_show()
327 event->event.chip.err_level : FAULT_LEVEL_MAX; in chip_fault_show()
330 (u32)event->event.chip.func_id); in chip_fault_show()
335 err = devlink_fmsg_u8_pair_put(fmsg, "module_id", event->event.chip.node_id); in chip_fault_show()
339 err = devlink_fmsg_u32_pair_put(fmsg, "err_type", (u32)event->event.chip.err_type); in chip_fault_show()
348 event->event.chip.err_csr_addr); in chip_fault_show()
353 event->event.chip.err_csr_value); in chip_fault_show()
361 struct hinic_fault_event *event) in fault_report_show() argument
369 fault_type = (event->type < FAULT_TYPE_MAX) ? event->type : FAULT_TYPE_MAX; in fault_report_show()
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| /drivers/input/ |
| D | input-compat.c | 15 struct input_event *event) in input_event_from_user() argument
24 event->input_event_sec = compat_event.sec; in input_event_from_user()
25 event->input_event_usec = compat_event.usec; in input_event_from_user()
26 event->type = compat_event.type; in input_event_from_user()
27 event->code = compat_event.code; in input_event_from_user()
28 event->value = compat_event.value; in input_event_from_user()
31 if (copy_from_user(event, buffer, sizeof(struct input_event))) in input_event_from_user()
39 const struct input_event *event) in input_event_to_user() argument
44 compat_event.sec = event->input_event_sec; in input_event_to_user()
45 compat_event.usec = event->input_event_usec; in input_event_to_user()
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| D | mcs_cnf10kb.c | 158 struct mcs_intr_event event; in cnf10kb_mcs_tx_pn_thresh_reached_handler() local
166 event.mcs_id = mcs->mcs_id; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
167 event.intr_mask = MCS_CPM_TX_PN_THRESH_REACHED_INT; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
183 event.sa_id = val & 0x7F; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
185 event.sa_id = (val >> 7) & 0x7F; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
187 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
188 mcs_add_intr_wq_entry(mcs, &event); in cnf10kb_mcs_tx_pn_thresh_reached_handler()
194 struct mcs_intr_event event = { 0 }; in cnf10kb_mcs_tx_pn_wrapped_handler() local
201 event.mcs_id = mcs->mcs_id; in cnf10kb_mcs_tx_pn_wrapped_handler()
202 event.intr_mask = MCS_CPM_TX_PACKET_XPN_EQ0_INT; in cnf10kb_mcs_tx_pn_wrapped_handler()
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| /drivers/char/tpm/eventlog/ |
| D | tpm1.c | 77 struct tcpa_event *event; in tpm1_bios_measurements_start() local
83 event = addr; in tpm1_bios_measurements_start()
90 do_endian_conversion(event->event_size); in tpm1_bios_measurements_start()
92 do_endian_conversion(event->event_type); in tpm1_bios_measurements_start()
111 struct tcpa_event *event = v; in tpm1_bios_measurements_next() local
119 converted_event_size = do_endian_conversion(event->event_size); in tpm1_bios_measurements_next()
127 event = v; in tpm1_bios_measurements_next()
129 converted_event_size = do_endian_conversion(event->event_size); in tpm1_bios_measurements_next()
130 converted_event_type = do_endian_conversion(event->event_type); in tpm1_bios_measurements_next()
143 static int get_event_name(char *dest, struct tcpa_event *event, in get_event_name() argument
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