| /drivers/cpufreq/ |
| D | tegra186-cpufreq.c | 103 u32 ndiv; in tegra186_cpufreq_get() local
110 ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK; in tegra186_cpufreq_get()
115 return (cluster->ref_clk_khz * ndiv) / cluster->div; in tegra186_cpufreq_get()
168 u16 ndiv = data->ndiv[i]; in init_vhint_table() local
170 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) in init_vhint_table()
174 if (i > 0 && ndiv == data->ndiv[i - 1]) in init_vhint_table()
192 u16 ndiv = data->ndiv[i]; in init_vhint_table() local
195 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) in init_vhint_table()
199 if (i > 0 && ndiv == data->ndiv[i - 1]) in init_vhint_table()
203 edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT; in init_vhint_table()
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| D | tegra194-cpufreq.c | 55 void (*set_cpu_ndiv)(struct cpufreq_policy *policy, u64 ndiv);
57 int (*get_cpu_ndiv)(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv);
116 static int tegra234_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv) in tegra234_get_cpu_ndiv() argument
126 *ndiv = readl(freq_core_reg) & NDIV_MASK; in tegra234_get_cpu_ndiv()
131 static void tegra234_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv) in tegra234_set_cpu_ndiv() argument
145 writel(ndiv, freq_core_reg); in tegra234_set_cpu_ndiv()
227 *nltbl, u16 ndiv) in map_ndiv_to_freq() argument
229 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
331 static void tegra194_get_cpu_ndiv_sysreg(void *ndiv) in tegra194_get_cpu_ndiv_sysreg() argument
337 *(u64 *)ndiv = ndiv_val; in tegra194_get_cpu_ndiv_sysreg()
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| D | brcmstb-avs-cpufreq.c | 342 unsigned int *ndiv) in brcm_avs_parse_p1() argument
346 *ndiv = (p1 >> NDIV_INT_SHIFT) & NDIV_INT_MASK; in brcm_avs_parse_p1()
688 unsigned int ndiv, pdiv; in show_brcm_avs_pmap() local
694 brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv); in show_brcm_avs_pmap()
698 pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2, in show_brcm_avs_pmap()
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| /drivers/clk/st/ |
| D | clkgen-pll.c | 46 struct clkgen_field ndiv; member
80 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
115 .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
141 .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
167 .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
211 u32 ndiv; member
220 unsigned long ndiv; member
350 pll->ndiv = n; in clk_pll3200c32_get_params()
359 for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++) in clk_pll3200c32_get_params()
371 *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000; in clk_pll3200c32_get_rate()
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| D | clkgen-fsyn.c | 34 unsigned long ndiv; member
49 struct clkgen_field ndiv; member
110 .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
146 .ndiv = CLKGEN_FIELD(0x2a4, 0x7, 16),
247 u32 ndiv; member
273 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in quadfs_pll_enable()
325 unsigned long nd = fs->ndiv + 16; /* ndiv value */ in clk_fs660c32_vco_get_rate()
339 params.ndiv = CLKGEN_READ(pll, ndiv); in quadfs_pll_fs660c32_recalc_rate()
344 pll->ndiv = params.ndiv; in quadfs_pll_fs660c32_recalc_rate()
373 fs->ndiv = n - 16; /* Converting formula value to reg value */ in clk_fs660c32_vco_get_params()
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| /drivers/media/dvb-frontends/ |
| D | stv0910.c | 798 u32 ndiv = (fphi * odf * idf) / quartz; in set_mclock() local
802 if (ndiv >= 7 && ndiv <= 71) in set_mclock()
804 else if (ndiv >= 72 && ndiv <= 79) in set_mclock()
806 else if (ndiv >= 80 && ndiv <= 87) in set_mclock()
808 else if (ndiv >= 88 && ndiv <= 95) in set_mclock()
810 else if (ndiv >= 96 && ndiv <= 103) in set_mclock()
812 else if (ndiv >= 104 && ndiv <= 111) in set_mclock()
814 else if (ndiv >= 112 && ndiv <= 119) in set_mclock()
816 else if (ndiv >= 120 && ndiv <= 127) in set_mclock()
818 else if (ndiv >= 128 && ndiv <= 135) in set_mclock()
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| D | cx24123.c | 506 u32 ndiv = 0, adiv = 0, vco_div = 0; in cx24123_pll_calculate() local
556 ndiv = (((p->frequency * vco_div * 10) / in cx24123_pll_calculate()
561 if (adiv == 0 && ndiv > 0) in cx24123_pll_calculate()
562 ndiv--; in cx24123_pll_calculate()
567 (pump << 14) | (ndiv << 5) | adiv; in cx24123_pll_calculate()
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| /drivers/clk/bcm/ |
| D | clk-iproc-armpll.c | 144 unsigned int ndiv_int, ndiv_frac, ndiv; in __get_ndiv() local
170 ndiv = (ndiv_int << 20) | ndiv_frac; in __get_ndiv()
172 return ndiv; in __get_ndiv()
191 u64 ndiv; in iproc_arm_pll_recalc_rate() local
213 ndiv = __get_ndiv(pll); in iproc_arm_pll_recalc_rate()
219 pll->rate = (ndiv * parent_rate) >> 20; in iproc_arm_pll_recalc_rate()
225 (unsigned int)(ndiv >> 20), pdiv, mdiv); in iproc_arm_pll_recalc_rate()
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| D | clk-bcm2835.c | 549 u32 *ndiv, u32 *fdiv) in bcm2835_pll_choose_ndiv_and_fdiv() argument
556 *ndiv = div >> A2W_PLL_FRAC_BITS; in bcm2835_pll_choose_ndiv_and_fdiv()
561 u32 ndiv, u32 fdiv, u32 pdiv) in bcm2835_pll_rate_from_divisors() argument
568 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); in bcm2835_pll_rate_from_divisors()
578 u32 ndiv, fdiv; in bcm2835_pll_round_rate() local
582 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); in bcm2835_pll_round_rate()
584 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); in bcm2835_pll_round_rate()
594 u32 ndiv, pdiv, fdiv; in bcm2835_pll_get_rate() local
601 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; in bcm2835_pll_get_rate()
607 ndiv *= 2; in bcm2835_pll_get_rate()
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| D | clk-iproc-pll.c | 454 u64 ndiv, ndiv_int, ndiv_frac; in iproc_pll_recalc_rate() local
474 ndiv = ndiv_int << 20; in iproc_pll_recalc_rate()
480 ndiv += ndiv_frac; in iproc_pll_recalc_rate()
486 rate = (ndiv * parent_rate) >> 20; in iproc_pll_recalc_rate()
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| /drivers/gpu/drm/stm/ |
| D | dw_mipi_dsi-stm.c | 130 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) in dsi_pll_get_clkout_khz() argument
138 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor); in dsi_pll_get_clkout_khz()
143 int *idf, int *ndiv, int *odf) in dsi_pll_get_params() argument
184 *ndiv = n; in dsi_pll_get_params()
246 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; in dw_mipi_dsi_get_lane_mbps() local
271 ndiv = 0; in dw_mipi_dsi_get_lane_mbps()
274 &idf, &ndiv, &odf); in dw_mipi_dsi_get_lane_mbps()
279 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); in dw_mipi_dsi_get_lane_mbps()
283 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); in dw_mipi_dsi_get_lane_mbps()
333 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; in dw_mipi_dsi_stm_mode_valid() local
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| /drivers/phy/st/ |
| D | phy-stm32-usbphyc.c | 132 u8 ndiv; member
207 unsigned long long fvco, ndiv, frac; in stm32_usbphyc_get_pll_params() local
221 ndiv = fvco; in stm32_usbphyc_get_pll_params()
222 do_div(ndiv, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
223 pll_params->ndiv = (u8)ndiv; in stm32_usbphyc_get_pll_params()
227 frac = frac - (ndiv * (1 << 16)); in stm32_usbphyc_get_pll_params()
235 u32 ndiv, frac; in stm32_usbphyc_pll_init() local
246 ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv); in stm32_usbphyc_pll_init()
249 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv; in stm32_usbphyc_pll_init()
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| /drivers/bcma/ |
| D | driver_chipcommon_pmu.c | 355 u32 tmp, div, ndiv, p1, p2, fc; in bcma_pmu_pll_clock() local
379 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; in bcma_pmu_pll_clock()
383 fc = (p1 * ndiv * fc) / p2; in bcma_pmu_pll_clock()
391 u32 tmp, ndiv, p1div, p2div; in bcma_pmu_pll_clock_bcm4706() local
398 ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK) in bcma_pmu_pll_clock_bcm4706()
408 clock = (25000000 / 4) * ndiv * p2div / p1div; in bcma_pmu_pll_clock_bcm4706()
411 clock = (25000000 / 2) * ndiv * p2div / p1div; in bcma_pmu_pll_clock_bcm4706()
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| /drivers/media/tuners/ |
| D | tda18250.c | 429 u8 *ndiv, u8 *icp) in tda18250_pll_calc() argument
452 *ndiv = 0; in tda18250_pll_calc()
458 *ndiv = 1; in tda18250_pll_calc()
464 *ndiv = 0; in tda18250_pll_calc()
468 *ndiv = 0; in tda18250_pll_calc()
472 *ndiv = 1; in tda18250_pll_calc()
478 *ndiv = 0; in tda18250_pll_calc()
487 lopd, scale, fvco, *rdiv, *ndiv, *icp); in tda18250_pll_calc()
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| /drivers/net/wireless/ath/ath9k/ |
| D | ar9002_phy.c | 69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel() local
142 ndiv = (freq * (refDivA >> aModeRefSel)) / 60; in ar9002_hw_set_channel()
143 channelSel = ndiv & 0x1ff; in ar9002_hw_set_channel()
144 channelFrac = (ndiv & 0xfffffe00) * 2; in ar9002_hw_set_channel()
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| /drivers/i2c/busses/ |
| D | i2c-octeon-core.c | 661 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; in octeon_i2c_set_clock() local
690 ndiv = ndiv_idx; in octeon_i2c_set_clock()
696 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); in octeon_i2c_set_clock()
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| /drivers/video/fbdev/savage/ |
| D | savagefb_driver.c | 418 unsigned int *ndiv, unsigned int *r) in SavageCalcClock() argument
457 *ndiv = best_n1 - 2; in SavageCalcClock()
465 unsigned char *ndiv) in common_calc_clock() argument
496 *ndiv = (best_n1 - 2) | (best_n2 << 6); in common_calc_clock()
498 *ndiv = (best_n1 - 2) | (best_n2 << 5); in common_calc_clock()
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