1 /*
2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
3 *
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 * Sven Neumann <neo@directfb.org>
6 *
7 *
8 * Card specific code is based on XFree86's savage driver.
9 * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
10 *
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
14 *
15 * 0.4.0 (neo)
16 * - hardware accelerated clear and move
17 *
18 * 0.3.2 (dok)
19 * - wait for vertical retrace before writing to cr67
20 * at the beginning of savagefb_set_par
21 * - use synchronization registers cr23 and cr26
22 *
23 * 0.3.1 (dok)
24 * - reset 3D engine
25 * - don't return alpha bits for 32bit format
26 *
27 * 0.3.0 (dok)
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
30 * - code cleanup
31 *
32 * 0.2.0 (dok)
33 * - first working version
34 *
35 *
36 * TODO
37 * - clock validations in decode_var
38 *
39 * BUGS
40 * - white margin on bootup
41 *
42 */
43
44 #include <linux/aperture.h>
45 #include <linux/module.h>
46 #include <linux/kernel.h>
47 #include <linux/errno.h>
48 #include <linux/string.h>
49 #include <linux/mm.h>
50 #include <linux/slab.h>
51 #include <linux/delay.h>
52 #include <linux/fb.h>
53 #include <linux/pci.h>
54 #include <linux/init.h>
55 #include <linux/console.h>
56
57 #include <asm/io.h>
58 #include <asm/irq.h>
59
60 #include "savagefb.h"
61
62
63 #define SAVAGEFB_VERSION "0.4.0_2.6"
64
65 /* --------------------------------------------------------------------- */
66
67
68 static char *mode_option = NULL;
69
70 #ifdef MODULE
71
72 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>");
73 MODULE_LICENSE("GPL");
74 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
75
76 #endif
77
78
79 /* --------------------------------------------------------------------- */
80
vgaHWSeqReset(struct savagefb_par * par,int start)81 static void vgaHWSeqReset(struct savagefb_par *par, int start)
82 {
83 if (start)
84 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */
85 else
86 VGAwSEQ(0x00, 0x03, par); /* End Reset */
87 }
88
vgaHWProtect(struct savagefb_par * par,int on)89 static void vgaHWProtect(struct savagefb_par *par, int on)
90 {
91 unsigned char tmp;
92
93 if (on) {
94 /*
95 * Turn off screen and disable sequencer.
96 */
97 tmp = VGArSEQ(0x01, par);
98
99 vgaHWSeqReset(par, 1); /* start synchronous reset */
100 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
101
102 VGAenablePalette(par);
103 } else {
104 /*
105 * Reenable sequencer, then turn on screen.
106 */
107
108 tmp = VGArSEQ(0x01, par);
109
110 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
111 vgaHWSeqReset(par, 0); /* clear synchronous reset */
112
113 VGAdisablePalette(par);
114 }
115 }
116
vgaHWRestore(struct savagefb_par * par,struct savage_reg * reg)117 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)
118 {
119 int i;
120
121 VGAwMISC(reg->MiscOutReg, par);
122
123 for (i = 1; i < 5; i++)
124 VGAwSEQ(i, reg->Sequencer[i], par);
125
126 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
127 CRTC[17] */
128 VGAwCR(17, reg->CRTC[17] & ~0x80, par);
129
130 for (i = 0; i < 25; i++)
131 VGAwCR(i, reg->CRTC[i], par);
132
133 for (i = 0; i < 9; i++)
134 VGAwGR(i, reg->Graphics[i], par);
135
136 VGAenablePalette(par);
137
138 for (i = 0; i < 21; i++)
139 VGAwATTR(i, reg->Attribute[i], par);
140
141 VGAdisablePalette(par);
142 }
143
vgaHWInit(struct fb_var_screeninfo * var,struct savagefb_par * par,struct xtimings * timings,struct savage_reg * reg)144 static void vgaHWInit(struct fb_var_screeninfo *var,
145 struct savagefb_par *par,
146 struct xtimings *timings,
147 struct savage_reg *reg)
148 {
149 reg->MiscOutReg = 0x23;
150
151 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
152 reg->MiscOutReg |= 0x40;
153
154 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
155 reg->MiscOutReg |= 0x80;
156
157 /*
158 * Time Sequencer
159 */
160 reg->Sequencer[0x00] = 0x00;
161 reg->Sequencer[0x01] = 0x01;
162 reg->Sequencer[0x02] = 0x0F;
163 reg->Sequencer[0x03] = 0x00; /* Font select */
164 reg->Sequencer[0x04] = 0x0E; /* Misc */
165
166 /*
167 * CRTC Controller
168 */
169 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
170 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
171 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
172 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
173 reg->CRTC[0x04] = (timings->HSyncStart >> 3);
174 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
175 (((timings->HSyncEnd >> 3)) & 0x1f);
176 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
177 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
178 (((timings->VDisplay - 1) & 0x100) >> 7) |
179 ((timings->VSyncStart & 0x100) >> 6) |
180 (((timings->VSyncStart - 1) & 0x100) >> 5) |
181 0x10 |
182 (((timings->VTotal - 2) & 0x200) >> 4) |
183 (((timings->VDisplay - 1) & 0x200) >> 3) |
184 ((timings->VSyncStart & 0x200) >> 2);
185 reg->CRTC[0x08] = 0x00;
186 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
187
188 if (timings->dblscan)
189 reg->CRTC[0x09] |= 0x80;
190
191 reg->CRTC[0x0a] = 0x00;
192 reg->CRTC[0x0b] = 0x00;
193 reg->CRTC[0x0c] = 0x00;
194 reg->CRTC[0x0d] = 0x00;
195 reg->CRTC[0x0e] = 0x00;
196 reg->CRTC[0x0f] = 0x00;
197 reg->CRTC[0x10] = timings->VSyncStart & 0xff;
198 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
199 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
200 reg->CRTC[0x13] = var->xres_virtual >> 4;
201 reg->CRTC[0x14] = 0x00;
202 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
203 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
204 reg->CRTC[0x17] = 0xc3;
205 reg->CRTC[0x18] = 0xff;
206
207 /*
208 * are these unnecessary?
209 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
210 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
211 */
212
213 /*
214 * Graphics Display Controller
215 */
216 reg->Graphics[0x00] = 0x00;
217 reg->Graphics[0x01] = 0x00;
218 reg->Graphics[0x02] = 0x00;
219 reg->Graphics[0x03] = 0x00;
220 reg->Graphics[0x04] = 0x00;
221 reg->Graphics[0x05] = 0x40;
222 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
223 reg->Graphics[0x07] = 0x0F;
224 reg->Graphics[0x08] = 0xFF;
225
226
227 reg->Attribute[0x00] = 0x00; /* standard colormap translation */
228 reg->Attribute[0x01] = 0x01;
229 reg->Attribute[0x02] = 0x02;
230 reg->Attribute[0x03] = 0x03;
231 reg->Attribute[0x04] = 0x04;
232 reg->Attribute[0x05] = 0x05;
233 reg->Attribute[0x06] = 0x06;
234 reg->Attribute[0x07] = 0x07;
235 reg->Attribute[0x08] = 0x08;
236 reg->Attribute[0x09] = 0x09;
237 reg->Attribute[0x0a] = 0x0A;
238 reg->Attribute[0x0b] = 0x0B;
239 reg->Attribute[0x0c] = 0x0C;
240 reg->Attribute[0x0d] = 0x0D;
241 reg->Attribute[0x0e] = 0x0E;
242 reg->Attribute[0x0f] = 0x0F;
243 reg->Attribute[0x10] = 0x41;
244 reg->Attribute[0x11] = 0xFF;
245 reg->Attribute[0x12] = 0x0F;
246 reg->Attribute[0x13] = 0x00;
247 reg->Attribute[0x14] = 0x00;
248 }
249
250 /* -------------------- Hardware specific routines ------------------------- */
251
252 /*
253 * Hardware Acceleration for SavageFB
254 */
255
256 /* Wait for fifo space */
257 static void
savage3D_waitfifo(struct savagefb_par * par,int space)258 savage3D_waitfifo(struct savagefb_par *par, int space)
259 {
260 int slots = MAXFIFO - space;
261
262 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
263 }
264
265 static void
savage4_waitfifo(struct savagefb_par * par,int space)266 savage4_waitfifo(struct savagefb_par *par, int space)
267 {
268 int slots = MAXFIFO - space;
269
270 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
271 }
272
273 static void
savage2000_waitfifo(struct savagefb_par * par,int space)274 savage2000_waitfifo(struct savagefb_par *par, int space)
275 {
276 int slots = MAXFIFO - space;
277
278 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
279 }
280
281 /* Wait for idle accelerator */
282 static void
savage3D_waitidle(struct savagefb_par * par)283 savage3D_waitidle(struct savagefb_par *par)
284 {
285 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
286 }
287
288 static void
savage4_waitidle(struct savagefb_par * par)289 savage4_waitidle(struct savagefb_par *par)
290 {
291 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
292 }
293
294 static void
savage2000_waitidle(struct savagefb_par * par)295 savage2000_waitidle(struct savagefb_par *par)
296 {
297 while ((savage_in32(0x48C60, par) & 0x009fffff));
298 }
299
300 #ifdef CONFIG_FB_SAVAGE_ACCEL
301 static void
SavageSetup2DEngine(struct savagefb_par * par)302 SavageSetup2DEngine(struct savagefb_par *par)
303 {
304 unsigned long GlobalBitmapDescriptor;
305
306 GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
307 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
308 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
309
310 switch(par->chip) {
311 case S3_SAVAGE3D:
312 case S3_SAVAGE_MX:
313 /* Disable BCI */
314 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
315 /* Setup BCI command overflow buffer */
316 savage_out32(0x48C14,
317 (par->cob_offset >> 11) | (par->cob_index << 29),
318 par);
319 /* Program shadow status update. */
320 savage_out32(0x48C10, 0x78207220, par);
321 savage_out32(0x48C0C, 0, par);
322 /* Enable BCI and command overflow buffer */
323 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
324 break;
325 case S3_SAVAGE4:
326 case S3_TWISTER:
327 case S3_PROSAVAGE:
328 case S3_PROSAVAGEDDR:
329 case S3_SUPERSAVAGE:
330 /* Disable BCI */
331 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
332 /* Program shadow status update */
333 savage_out32(0x48C10, 0x00700040, par);
334 savage_out32(0x48C0C, 0, par);
335 /* Enable BCI without the COB */
336 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
337 break;
338 case S3_SAVAGE2000:
339 /* Disable BCI */
340 savage_out32(0x48C18, 0, par);
341 /* Setup BCI command overflow buffer */
342 savage_out32(0x48C18,
343 (par->cob_offset >> 7) | (par->cob_index),
344 par);
345 /* Disable shadow status update */
346 savage_out32(0x48A30, 0, par);
347 /* Enable BCI and command overflow buffer */
348 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
349 par);
350 break;
351 default:
352 break;
353 }
354 /* Turn on 16-bit register access. */
355 vga_out8(0x3d4, 0x31, par);
356 vga_out8(0x3d5, 0x0c, par);
357
358 /* Set stride to use GBD. */
359 vga_out8(0x3d4, 0x50, par);
360 vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
361
362 /* Enable 2D engine. */
363 vga_out8(0x3d4, 0x40, par);
364 vga_out8(0x3d5, 0x01, par);
365
366 savage_out32(MONO_PAT_0, ~0, par);
367 savage_out32(MONO_PAT_1, ~0, par);
368
369 /* Setup plane masks */
370 savage_out32(0x8128, ~0, par); /* enable all write planes */
371 savage_out32(0x812C, ~0, par); /* enable all read planes */
372 savage_out16(0x8134, 0x27, par);
373 savage_out16(0x8136, 0x07, par);
374
375 /* Now set the GBD */
376 par->bci_ptr = 0;
377 par->SavageWaitFifo(par, 4);
378
379 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
380 BCI_SEND(0);
381 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
382 BCI_SEND(GlobalBitmapDescriptor);
383
384 /*
385 * I don't know why, sending this twice fixes the initial black screen,
386 * prevents X from crashing at least in Toshiba laptops with SavageIX.
387 * --Tony
388 */
389 par->bci_ptr = 0;
390 par->SavageWaitFifo(par, 4);
391
392 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
393 BCI_SEND(0);
394 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
395 BCI_SEND(GlobalBitmapDescriptor);
396 }
397
savagefb_set_clip(struct fb_info * info)398 static void savagefb_set_clip(struct fb_info *info)
399 {
400 struct savagefb_par *par = info->par;
401 int cmd;
402
403 cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
404 par->bci_ptr = 0;
405 par->SavageWaitFifo(par,3);
406 BCI_SEND(cmd);
407 BCI_SEND(BCI_CLIP_TL(0, 0));
408 BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
409 }
410 #else
SavageSetup2DEngine(struct savagefb_par * par)411 static void SavageSetup2DEngine(struct savagefb_par *par) {}
412
413 #endif
414
SavageCalcClock(long freq,int min_m,int min_n1,int max_n1,int min_n2,int max_n2,long freq_min,long freq_max,unsigned int * mdiv,unsigned int * ndiv,unsigned int * r)415 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
416 int min_n2, int max_n2, long freq_min,
417 long freq_max, unsigned int *mdiv,
418 unsigned int *ndiv, unsigned int *r)
419 {
420 long diff, best_diff;
421 unsigned int m;
422 unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
423
424 if (freq < freq_min / (1 << max_n2)) {
425 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
426 freq = freq_min / (1 << max_n2);
427 }
428 if (freq > freq_max / (1 << min_n2)) {
429 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
430 freq = freq_max / (1 << min_n2);
431 }
432
433 /* work out suitable timings */
434 best_diff = freq;
435
436 for (n2=min_n2; n2<=max_n2; n2++) {
437 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
438 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
439 BASE_FREQ;
440 if (m < min_m+2 || m > 127+2)
441 continue;
442 if ((m * BASE_FREQ >= freq_min * n1) &&
443 (m * BASE_FREQ <= freq_max * n1)) {
444 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
445 if (diff < 0)
446 diff = -diff;
447 if (diff < best_diff) {
448 best_diff = diff;
449 best_m = m;
450 best_n1 = n1;
451 best_n2 = n2;
452 }
453 }
454 }
455 }
456
457 *ndiv = best_n1 - 2;
458 *r = best_n2;
459 *mdiv = best_m - 2;
460 }
461
common_calc_clock(long freq,int min_m,int min_n1,int max_n1,int min_n2,int max_n2,long freq_min,long freq_max,unsigned char * mdiv,unsigned char * ndiv)462 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
463 int min_n2, int max_n2, long freq_min,
464 long freq_max, unsigned char *mdiv,
465 unsigned char *ndiv)
466 {
467 long diff, best_diff;
468 unsigned int m;
469 unsigned char n1, n2;
470 unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
471
472 best_diff = freq;
473
474 for (n2 = min_n2; n2 <= max_n2; n2++) {
475 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
476 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
477 BASE_FREQ;
478 if (m < min_m + 2 || m > 127+2)
479 continue;
480 if ((m * BASE_FREQ >= freq_min * n1) &&
481 (m * BASE_FREQ <= freq_max * n1)) {
482 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
483 if (diff < 0)
484 diff = -diff;
485 if (diff < best_diff) {
486 best_diff = diff;
487 best_m = m;
488 best_n1 = n1;
489 best_n2 = n2;
490 }
491 }
492 }
493 }
494
495 if (max_n1 == 63)
496 *ndiv = (best_n1 - 2) | (best_n2 << 6);
497 else
498 *ndiv = (best_n1 - 2) | (best_n2 << 5);
499
500 *mdiv = best_m - 2;
501
502 return 0;
503 }
504
505 #ifdef SAVAGEFB_DEBUG
506 /* This function is used to debug, it prints out the contents of s3 regs */
507
SavagePrintRegs(struct savagefb_par * par)508 static void SavagePrintRegs(struct savagefb_par *par)
509 {
510 unsigned char i;
511 int vgaCRIndex = 0x3d4;
512 int vgaCRReg = 0x3d5;
513
514 printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
515 "xF");
516
517 for (i = 0; i < 0x70; i++) {
518 if (!(i % 16))
519 printk(KERN_DEBUG "\nSR%xx ", i >> 4);
520 vga_out8(0x3c4, i, par);
521 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
522 }
523
524 printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
525 "xD xE xF");
526
527 for (i = 0; i < 0xB7; i++) {
528 if (!(i % 16))
529 printk(KERN_DEBUG "\nCR%xx ", i >> 4);
530 vga_out8(vgaCRIndex, i, par);
531 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
532 }
533
534 printk(KERN_DEBUG "\n\n");
535 }
536 #endif
537
538 /* --------------------------------------------------------------------- */
539
savage_get_default_par(struct savagefb_par * par,struct savage_reg * reg)540 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
541 {
542 unsigned char cr3a, cr53, cr66;
543
544 vga_out16(0x3d4, 0x4838, par);
545 vga_out16(0x3d4, 0xa039, par);
546 vga_out16(0x3c4, 0x0608, par);
547
548 vga_out8(0x3d4, 0x66, par);
549 cr66 = vga_in8(0x3d5, par);
550 vga_out8(0x3d5, cr66 | 0x80, par);
551 vga_out8(0x3d4, 0x3a, par);
552 cr3a = vga_in8(0x3d5, par);
553 vga_out8(0x3d5, cr3a | 0x80, par);
554 vga_out8(0x3d4, 0x53, par);
555 cr53 = vga_in8(0x3d5, par);
556 vga_out8(0x3d5, cr53 & 0x7f, par);
557
558 vga_out8(0x3d4, 0x66, par);
559 vga_out8(0x3d5, cr66, par);
560 vga_out8(0x3d4, 0x3a, par);
561 vga_out8(0x3d5, cr3a, par);
562
563 vga_out8(0x3d4, 0x66, par);
564 vga_out8(0x3d5, cr66, par);
565 vga_out8(0x3d4, 0x3a, par);
566 vga_out8(0x3d5, cr3a, par);
567
568 /* unlock extended seq regs */
569 vga_out8(0x3c4, 0x08, par);
570 reg->SR08 = vga_in8(0x3c5, par);
571 vga_out8(0x3c5, 0x06, par);
572
573 /* now save all the extended regs we need */
574 vga_out8(0x3d4, 0x31, par);
575 reg->CR31 = vga_in8(0x3d5, par);
576 vga_out8(0x3d4, 0x32, par);
577 reg->CR32 = vga_in8(0x3d5, par);
578 vga_out8(0x3d4, 0x34, par);
579 reg->CR34 = vga_in8(0x3d5, par);
580 vga_out8(0x3d4, 0x36, par);
581 reg->CR36 = vga_in8(0x3d5, par);
582 vga_out8(0x3d4, 0x3a, par);
583 reg->CR3A = vga_in8(0x3d5, par);
584 vga_out8(0x3d4, 0x40, par);
585 reg->CR40 = vga_in8(0x3d5, par);
586 vga_out8(0x3d4, 0x42, par);
587 reg->CR42 = vga_in8(0x3d5, par);
588 vga_out8(0x3d4, 0x45, par);
589 reg->CR45 = vga_in8(0x3d5, par);
590 vga_out8(0x3d4, 0x50, par);
591 reg->CR50 = vga_in8(0x3d5, par);
592 vga_out8(0x3d4, 0x51, par);
593 reg->CR51 = vga_in8(0x3d5, par);
594 vga_out8(0x3d4, 0x53, par);
595 reg->CR53 = vga_in8(0x3d5, par);
596 vga_out8(0x3d4, 0x58, par);
597 reg->CR58 = vga_in8(0x3d5, par);
598 vga_out8(0x3d4, 0x60, par);
599 reg->CR60 = vga_in8(0x3d5, par);
600 vga_out8(0x3d4, 0x66, par);
601 reg->CR66 = vga_in8(0x3d5, par);
602 vga_out8(0x3d4, 0x67, par);
603 reg->CR67 = vga_in8(0x3d5, par);
604 vga_out8(0x3d4, 0x68, par);
605 reg->CR68 = vga_in8(0x3d5, par);
606 vga_out8(0x3d4, 0x69, par);
607 reg->CR69 = vga_in8(0x3d5, par);
608 vga_out8(0x3d4, 0x6f, par);
609 reg->CR6F = vga_in8(0x3d5, par);
610
611 vga_out8(0x3d4, 0x33, par);
612 reg->CR33 = vga_in8(0x3d5, par);
613 vga_out8(0x3d4, 0x86, par);
614 reg->CR86 = vga_in8(0x3d5, par);
615 vga_out8(0x3d4, 0x88, par);
616 reg->CR88 = vga_in8(0x3d5, par);
617 vga_out8(0x3d4, 0x90, par);
618 reg->CR90 = vga_in8(0x3d5, par);
619 vga_out8(0x3d4, 0x91, par);
620 reg->CR91 = vga_in8(0x3d5, par);
621 vga_out8(0x3d4, 0xb0, par);
622 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
623
624 /* extended mode timing regs */
625 vga_out8(0x3d4, 0x3b, par);
626 reg->CR3B = vga_in8(0x3d5, par);
627 vga_out8(0x3d4, 0x3c, par);
628 reg->CR3C = vga_in8(0x3d5, par);
629 vga_out8(0x3d4, 0x43, par);
630 reg->CR43 = vga_in8(0x3d5, par);
631 vga_out8(0x3d4, 0x5d, par);
632 reg->CR5D = vga_in8(0x3d5, par);
633 vga_out8(0x3d4, 0x5e, par);
634 reg->CR5E = vga_in8(0x3d5, par);
635 vga_out8(0x3d4, 0x65, par);
636 reg->CR65 = vga_in8(0x3d5, par);
637
638 /* save seq extended regs for DCLK PLL programming */
639 vga_out8(0x3c4, 0x0e, par);
640 reg->SR0E = vga_in8(0x3c5, par);
641 vga_out8(0x3c4, 0x0f, par);
642 reg->SR0F = vga_in8(0x3c5, par);
643 vga_out8(0x3c4, 0x10, par);
644 reg->SR10 = vga_in8(0x3c5, par);
645 vga_out8(0x3c4, 0x11, par);
646 reg->SR11 = vga_in8(0x3c5, par);
647 vga_out8(0x3c4, 0x12, par);
648 reg->SR12 = vga_in8(0x3c5, par);
649 vga_out8(0x3c4, 0x13, par);
650 reg->SR13 = vga_in8(0x3c5, par);
651 vga_out8(0x3c4, 0x29, par);
652 reg->SR29 = vga_in8(0x3c5, par);
653
654 vga_out8(0x3c4, 0x15, par);
655 reg->SR15 = vga_in8(0x3c5, par);
656 vga_out8(0x3c4, 0x30, par);
657 reg->SR30 = vga_in8(0x3c5, par);
658 vga_out8(0x3c4, 0x18, par);
659 reg->SR18 = vga_in8(0x3c5, par);
660
661 /* Save flat panel expansion registers. */
662 if (par->chip == S3_SAVAGE_MX) {
663 int i;
664
665 for (i = 0; i < 8; i++) {
666 vga_out8(0x3c4, 0x54+i, par);
667 reg->SR54[i] = vga_in8(0x3c5, par);
668 }
669 }
670
671 vga_out8(0x3d4, 0x66, par);
672 cr66 = vga_in8(0x3d5, par);
673 vga_out8(0x3d5, cr66 | 0x80, par);
674 vga_out8(0x3d4, 0x3a, par);
675 cr3a = vga_in8(0x3d5, par);
676 vga_out8(0x3d5, cr3a | 0x80, par);
677
678 /* now save MIU regs */
679 if (par->chip != S3_SAVAGE_MX) {
680 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
681 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
682 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
683 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
684 }
685
686 vga_out8(0x3d4, 0x3a, par);
687 vga_out8(0x3d5, cr3a, par);
688 vga_out8(0x3d4, 0x66, par);
689 vga_out8(0x3d5, cr66, par);
690 }
691
savage_set_default_par(struct savagefb_par * par,struct savage_reg * reg)692 static void savage_set_default_par(struct savagefb_par *par,
693 struct savage_reg *reg)
694 {
695 unsigned char cr3a, cr53, cr66;
696
697 vga_out16(0x3d4, 0x4838, par);
698 vga_out16(0x3d4, 0xa039, par);
699 vga_out16(0x3c4, 0x0608, par);
700
701 vga_out8(0x3d4, 0x66, par);
702 cr66 = vga_in8(0x3d5, par);
703 vga_out8(0x3d5, cr66 | 0x80, par);
704 vga_out8(0x3d4, 0x3a, par);
705 cr3a = vga_in8(0x3d5, par);
706 vga_out8(0x3d5, cr3a | 0x80, par);
707 vga_out8(0x3d4, 0x53, par);
708 cr53 = vga_in8(0x3d5, par);
709 vga_out8(0x3d5, cr53 & 0x7f, par);
710
711 vga_out8(0x3d4, 0x66, par);
712 vga_out8(0x3d5, cr66, par);
713 vga_out8(0x3d4, 0x3a, par);
714 vga_out8(0x3d5, cr3a, par);
715
716 vga_out8(0x3d4, 0x66, par);
717 vga_out8(0x3d5, cr66, par);
718 vga_out8(0x3d4, 0x3a, par);
719 vga_out8(0x3d5, cr3a, par);
720
721 /* unlock extended seq regs */
722 vga_out8(0x3c4, 0x08, par);
723 vga_out8(0x3c5, reg->SR08, par);
724 vga_out8(0x3c5, 0x06, par);
725
726 /* now restore all the extended regs we need */
727 vga_out8(0x3d4, 0x31, par);
728 vga_out8(0x3d5, reg->CR31, par);
729 vga_out8(0x3d4, 0x32, par);
730 vga_out8(0x3d5, reg->CR32, par);
731 vga_out8(0x3d4, 0x34, par);
732 vga_out8(0x3d5, reg->CR34, par);
733 vga_out8(0x3d4, 0x36, par);
734 vga_out8(0x3d5,reg->CR36, par);
735 vga_out8(0x3d4, 0x3a, par);
736 vga_out8(0x3d5, reg->CR3A, par);
737 vga_out8(0x3d4, 0x40, par);
738 vga_out8(0x3d5, reg->CR40, par);
739 vga_out8(0x3d4, 0x42, par);
740 vga_out8(0x3d5, reg->CR42, par);
741 vga_out8(0x3d4, 0x45, par);
742 vga_out8(0x3d5, reg->CR45, par);
743 vga_out8(0x3d4, 0x50, par);
744 vga_out8(0x3d5, reg->CR50, par);
745 vga_out8(0x3d4, 0x51, par);
746 vga_out8(0x3d5, reg->CR51, par);
747 vga_out8(0x3d4, 0x53, par);
748 vga_out8(0x3d5, reg->CR53, par);
749 vga_out8(0x3d4, 0x58, par);
750 vga_out8(0x3d5, reg->CR58, par);
751 vga_out8(0x3d4, 0x60, par);
752 vga_out8(0x3d5, reg->CR60, par);
753 vga_out8(0x3d4, 0x66, par);
754 vga_out8(0x3d5, reg->CR66, par);
755 vga_out8(0x3d4, 0x67, par);
756 vga_out8(0x3d5, reg->CR67, par);
757 vga_out8(0x3d4, 0x68, par);
758 vga_out8(0x3d5, reg->CR68, par);
759 vga_out8(0x3d4, 0x69, par);
760 vga_out8(0x3d5, reg->CR69, par);
761 vga_out8(0x3d4, 0x6f, par);
762 vga_out8(0x3d5, reg->CR6F, par);
763
764 vga_out8(0x3d4, 0x33, par);
765 vga_out8(0x3d5, reg->CR33, par);
766 vga_out8(0x3d4, 0x86, par);
767 vga_out8(0x3d5, reg->CR86, par);
768 vga_out8(0x3d4, 0x88, par);
769 vga_out8(0x3d5, reg->CR88, par);
770 vga_out8(0x3d4, 0x90, par);
771 vga_out8(0x3d5, reg->CR90, par);
772 vga_out8(0x3d4, 0x91, par);
773 vga_out8(0x3d5, reg->CR91, par);
774 vga_out8(0x3d4, 0xb0, par);
775 vga_out8(0x3d5, reg->CRB0, par);
776
777 /* extended mode timing regs */
778 vga_out8(0x3d4, 0x3b, par);
779 vga_out8(0x3d5, reg->CR3B, par);
780 vga_out8(0x3d4, 0x3c, par);
781 vga_out8(0x3d5, reg->CR3C, par);
782 vga_out8(0x3d4, 0x43, par);
783 vga_out8(0x3d5, reg->CR43, par);
784 vga_out8(0x3d4, 0x5d, par);
785 vga_out8(0x3d5, reg->CR5D, par);
786 vga_out8(0x3d4, 0x5e, par);
787 vga_out8(0x3d5, reg->CR5E, par);
788 vga_out8(0x3d4, 0x65, par);
789 vga_out8(0x3d5, reg->CR65, par);
790
791 /* save seq extended regs for DCLK PLL programming */
792 vga_out8(0x3c4, 0x0e, par);
793 vga_out8(0x3c5, reg->SR0E, par);
794 vga_out8(0x3c4, 0x0f, par);
795 vga_out8(0x3c5, reg->SR0F, par);
796 vga_out8(0x3c4, 0x10, par);
797 vga_out8(0x3c5, reg->SR10, par);
798 vga_out8(0x3c4, 0x11, par);
799 vga_out8(0x3c5, reg->SR11, par);
800 vga_out8(0x3c4, 0x12, par);
801 vga_out8(0x3c5, reg->SR12, par);
802 vga_out8(0x3c4, 0x13, par);
803 vga_out8(0x3c5, reg->SR13, par);
804 vga_out8(0x3c4, 0x29, par);
805 vga_out8(0x3c5, reg->SR29, par);
806
807 vga_out8(0x3c4, 0x15, par);
808 vga_out8(0x3c5, reg->SR15, par);
809 vga_out8(0x3c4, 0x30, par);
810 vga_out8(0x3c5, reg->SR30, par);
811 vga_out8(0x3c4, 0x18, par);
812 vga_out8(0x3c5, reg->SR18, par);
813
814 /* Save flat panel expansion registers. */
815 if (par->chip == S3_SAVAGE_MX) {
816 int i;
817
818 for (i = 0; i < 8; i++) {
819 vga_out8(0x3c4, 0x54+i, par);
820 vga_out8(0x3c5, reg->SR54[i], par);
821 }
822 }
823
824 vga_out8(0x3d4, 0x66, par);
825 cr66 = vga_in8(0x3d5, par);
826 vga_out8(0x3d5, cr66 | 0x80, par);
827 vga_out8(0x3d4, 0x3a, par);
828 cr3a = vga_in8(0x3d5, par);
829 vga_out8(0x3d5, cr3a | 0x80, par);
830
831 /* now save MIU regs */
832 if (par->chip != S3_SAVAGE_MX) {
833 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
834 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
835 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
836 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
837 }
838
839 vga_out8(0x3d4, 0x3a, par);
840 vga_out8(0x3d5, cr3a, par);
841 vga_out8(0x3d4, 0x66, par);
842 vga_out8(0x3d5, cr66, par);
843 }
844
savage_update_var(struct fb_var_screeninfo * var,const struct fb_videomode * modedb)845 static void savage_update_var(struct fb_var_screeninfo *var,
846 const struct fb_videomode *modedb)
847 {
848 var->xres = var->xres_virtual = modedb->xres;
849 var->yres = modedb->yres;
850 if (var->yres_virtual < var->yres)
851 var->yres_virtual = var->yres;
852 var->xoffset = var->yoffset = 0;
853 var->pixclock = modedb->pixclock;
854 var->left_margin = modedb->left_margin;
855 var->right_margin = modedb->right_margin;
856 var->upper_margin = modedb->upper_margin;
857 var->lower_margin = modedb->lower_margin;
858 var->hsync_len = modedb->hsync_len;
859 var->vsync_len = modedb->vsync_len;
860 var->sync = modedb->sync;
861 var->vmode = modedb->vmode;
862 }
863
savagefb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)864 static int savagefb_check_var(struct fb_var_screeninfo *var,
865 struct fb_info *info)
866 {
867 struct savagefb_par *par = info->par;
868 int memlen, vramlen, mode_valid = 0;
869
870 DBG("savagefb_check_var");
871
872 if (!var->pixclock)
873 return -EINVAL;
874
875 var->transp.offset = 0;
876 var->transp.length = 0;
877 switch (var->bits_per_pixel) {
878 case 8:
879 var->red.offset = var->green.offset =
880 var->blue.offset = 0;
881 var->red.length = var->green.length =
882 var->blue.length = var->bits_per_pixel;
883 break;
884 case 16:
885 var->red.offset = 11;
886 var->red.length = 5;
887 var->green.offset = 5;
888 var->green.length = 6;
889 var->blue.offset = 0;
890 var->blue.length = 5;
891 break;
892 case 32:
893 var->transp.offset = 24;
894 var->transp.length = 8;
895 var->red.offset = 16;
896 var->red.length = 8;
897 var->green.offset = 8;
898 var->green.length = 8;
899 var->blue.offset = 0;
900 var->blue.length = 8;
901 break;
902
903 default:
904 return -EINVAL;
905 }
906
907 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
908 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
909 mode_valid = 1;
910
911 /* calculate modeline if supported by monitor */
912 if (!mode_valid && info->monspecs.gtf) {
913 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
914 mode_valid = 1;
915 }
916
917 if (!mode_valid) {
918 const struct fb_videomode *mode;
919
920 mode = fb_find_best_mode(var, &info->modelist);
921 if (mode) {
922 savage_update_var(var, mode);
923 mode_valid = 1;
924 }
925 }
926
927 if (!mode_valid && info->monspecs.modedb_len)
928 return -EINVAL;
929
930 /* Is the mode larger than the LCD panel? */
931 if (par->SavagePanelWidth &&
932 (var->xres > par->SavagePanelWidth ||
933 var->yres > par->SavagePanelHeight)) {
934 printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
935 "(%dx%d)\n", var->xres, var->yres,
936 par->SavagePanelWidth,
937 par->SavagePanelHeight);
938 return -1;
939 }
940
941 if (var->yres_virtual < var->yres)
942 var->yres_virtual = var->yres;
943 if (var->xres_virtual < var->xres)
944 var->xres_virtual = var->xres;
945
946 vramlen = info->fix.smem_len;
947
948 memlen = var->xres_virtual * var->bits_per_pixel *
949 var->yres_virtual / 8;
950 if (memlen > vramlen) {
951 var->yres_virtual = vramlen * 8 /
952 (var->xres_virtual * var->bits_per_pixel);
953 memlen = var->xres_virtual * var->bits_per_pixel *
954 var->yres_virtual / 8;
955 }
956
957 /* we must round yres/xres down, we already rounded y/xres_virtual up
958 if it was possible. We should return -EINVAL, but I disagree */
959 if (var->yres_virtual < var->yres)
960 var->yres = var->yres_virtual;
961 if (var->xres_virtual < var->xres)
962 var->xres = var->xres_virtual;
963 if (var->xoffset + var->xres > var->xres_virtual)
964 var->xoffset = var->xres_virtual - var->xres;
965 if (var->yoffset + var->yres > var->yres_virtual)
966 var->yoffset = var->yres_virtual - var->yres;
967
968 return 0;
969 }
970
971
savagefb_decode_var(struct fb_var_screeninfo * var,struct savagefb_par * par,struct savage_reg * reg)972 static int savagefb_decode_var(struct fb_var_screeninfo *var,
973 struct savagefb_par *par,
974 struct savage_reg *reg)
975 {
976 struct xtimings timings;
977 int width, dclk, i, j; /*, refresh; */
978 unsigned int m, n, r;
979 unsigned char tmp = 0;
980 unsigned int pixclock = var->pixclock;
981
982 DBG("savagefb_decode_var");
983
984 memset(&timings, 0, sizeof(timings));
985
986 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
987 timings.Clock = 1000000000 / pixclock;
988 if (timings.Clock < 1) timings.Clock = 1;
989 timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
990 timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
991 timings.HDisplay = var->xres;
992 timings.HSyncStart = timings.HDisplay + var->right_margin;
993 timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
994 timings.HTotal = timings.HSyncEnd + var->left_margin;
995 timings.VDisplay = var->yres;
996 timings.VSyncStart = timings.VDisplay + var->lower_margin;
997 timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
998 timings.VTotal = timings.VSyncEnd + var->upper_margin;
999 timings.sync = var->sync;
1000
1001
1002 par->depth = var->bits_per_pixel;
1003 par->vwidth = var->xres_virtual;
1004
1005 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {
1006 timings.HDisplay *= 2;
1007 timings.HSyncStart *= 2;
1008 timings.HSyncEnd *= 2;
1009 timings.HTotal *= 2;
1010 }
1011
1012 /*
1013 * This will allocate the datastructure and initialize all of the
1014 * generic VGA registers.
1015 */
1016 vgaHWInit(var, par, &timings, reg);
1017
1018 /* We need to set CR67 whether or not we use the BIOS. */
1019
1020 dclk = timings.Clock;
1021 reg->CR67 = 0x00;
1022
1023 switch(var->bits_per_pixel) {
1024 case 8:
1025 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1026 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
1027 else
1028 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
1029 break;
1030 case 15:
1031 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1032 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1033 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
1034 else
1035 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
1036 break;
1037 case 16:
1038 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1039 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1040 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
1041 else
1042 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
1043 break;
1044 case 24:
1045 reg->CR67 = 0x70;
1046 break;
1047 case 32:
1048 reg->CR67 = 0xd0;
1049 break;
1050 }
1051
1052 /*
1053 * Either BIOS use is disabled, or we failed to find a suitable
1054 * match. Fall back to traditional register-crunching.
1055 */
1056
1057 vga_out8(0x3d4, 0x3a, par);
1058 tmp = vga_in8(0x3d5, par);
1059 if (1 /*FIXME:psav->pci_burst*/)
1060 reg->CR3A = (tmp & 0x7f) | 0x15;
1061 else
1062 reg->CR3A = tmp | 0x95;
1063
1064 reg->CR53 = 0x00;
1065 reg->CR31 = 0x8c;
1066 reg->CR66 = 0x89;
1067
1068 vga_out8(0x3d4, 0x58, par);
1069 reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1070 reg->CR58 |= 0x13;
1071
1072 reg->SR15 = 0x03 | 0x80;
1073 reg->SR18 = 0x00;
1074 reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
1075
1076 vga_out8(0x3d4, 0x40, par);
1077 reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1078
1079 reg->MMPR0 = 0x010400;
1080 reg->MMPR1 = 0x00;
1081 reg->MMPR2 = 0x0808;
1082 reg->MMPR3 = 0x08080810;
1083
1084 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
1085 /* m = 107; n = 4; r = 2; */
1086
1087 if (par->MCLK <= 0) {
1088 reg->SR10 = 255;
1089 reg->SR11 = 255;
1090 } else {
1091 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1092 ®->SR11, ®->SR10);
1093 /* reg->SR10 = 80; // MCLK == 286000 */
1094 /* reg->SR11 = 125; */
1095 }
1096
1097 reg->SR12 = (r << 6) | (n & 0x3f);
1098 reg->SR13 = m & 0xff;
1099 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
1100
1101 if (var->bits_per_pixel < 24)
1102 reg->MMPR0 -= 0x8000;
1103 else
1104 reg->MMPR0 -= 0x4000;
1105
1106 if (timings.interlaced)
1107 reg->CR42 = 0x20;
1108 else
1109 reg->CR42 = 0x00;
1110
1111 reg->CR34 = 0x10; /* display fifo */
1112
1113 i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
1114 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
1115 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
1116 ((timings.HSyncStart & 0x800) >> 7);
1117
1118 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
1119 i |= 0x08;
1120 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
1121 i |= 0x20;
1122
1123 j = (reg->CRTC[0] + ((i & 0x01) << 8) +
1124 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
1125
1126 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
1127 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
1128 reg->CRTC[0] + ((i & 0x01) << 8))
1129 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
1130 else
1131 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
1132 }
1133
1134 reg->CR3B = j & 0xff;
1135 i |= (j & 0x100) >> 2;
1136 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
1137 reg->CR5D = i;
1138 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
1139 (((timings.VDisplay - 1) & 0x400) >> 9) |
1140 (((timings.VSyncStart) & 0x400) >> 8) |
1141 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
1142 width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
1143 reg->CR91 = reg->CRTC[19] = 0xff & width;
1144 reg->CR51 = (0x300 & width) >> 4;
1145 reg->CR90 = 0x80 | (width >> 8);
1146 reg->MiscOutReg |= 0x0c;
1147
1148 /* Set frame buffer description. */
1149
1150 if (var->bits_per_pixel <= 8)
1151 reg->CR50 = 0;
1152 else if (var->bits_per_pixel <= 16)
1153 reg->CR50 = 0x10;
1154 else
1155 reg->CR50 = 0x30;
1156
1157 if (var->xres_virtual <= 640)
1158 reg->CR50 |= 0x40;
1159 else if (var->xres_virtual == 800)
1160 reg->CR50 |= 0x80;
1161 else if (var->xres_virtual == 1024)
1162 reg->CR50 |= 0x00;
1163 else if (var->xres_virtual == 1152)
1164 reg->CR50 |= 0x01;
1165 else if (var->xres_virtual == 1280)
1166 reg->CR50 |= 0xc0;
1167 else if (var->xres_virtual == 1600)
1168 reg->CR50 |= 0x81;
1169 else
1170 reg->CR50 |= 0xc1; /* Use GBD */
1171
1172 if (par->chip == S3_SAVAGE2000)
1173 reg->CR33 = 0x08;
1174 else
1175 reg->CR33 = 0x20;
1176
1177 reg->CRTC[0x17] = 0xeb;
1178
1179 reg->CR67 |= 1;
1180
1181 vga_out8(0x3d4, 0x36, par);
1182 reg->CR36 = vga_in8(0x3d5, par);
1183 vga_out8(0x3d4, 0x68, par);
1184 reg->CR68 = vga_in8(0x3d5, par);
1185 reg->CR69 = 0;
1186 vga_out8(0x3d4, 0x6f, par);
1187 reg->CR6F = vga_in8(0x3d5, par);
1188 vga_out8(0x3d4, 0x86, par);
1189 reg->CR86 = vga_in8(0x3d5, par);
1190 vga_out8(0x3d4, 0x88, par);
1191 reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1192 vga_out8(0x3d4, 0xb0, par);
1193 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1194
1195 return 0;
1196 }
1197
1198 /* --------------------------------------------------------------------- */
1199
1200 /*
1201 * Set a single color register. Return != 0 for invalid regno.
1202 */
savagefb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)1203 static int savagefb_setcolreg(unsigned regno,
1204 unsigned red,
1205 unsigned green,
1206 unsigned blue,
1207 unsigned transp,
1208 struct fb_info *info)
1209 {
1210 struct savagefb_par *par = info->par;
1211
1212 if (regno >= NR_PALETTE)
1213 return -EINVAL;
1214
1215 par->palette[regno].red = red;
1216 par->palette[regno].green = green;
1217 par->palette[regno].blue = blue;
1218 par->palette[regno].transp = transp;
1219
1220 switch (info->var.bits_per_pixel) {
1221 case 8:
1222 vga_out8(0x3c8, regno, par);
1223
1224 vga_out8(0x3c9, red >> 10, par);
1225 vga_out8(0x3c9, green >> 10, par);
1226 vga_out8(0x3c9, blue >> 10, par);
1227 break;
1228
1229 case 16:
1230 if (regno < 16)
1231 ((u32 *)info->pseudo_palette)[regno] =
1232 ((red & 0xf800) ) |
1233 ((green & 0xfc00) >> 5) |
1234 ((blue & 0xf800) >> 11);
1235 break;
1236
1237 case 24:
1238 if (regno < 16)
1239 ((u32 *)info->pseudo_palette)[regno] =
1240 ((red & 0xff00) << 8) |
1241 ((green & 0xff00) ) |
1242 ((blue & 0xff00) >> 8);
1243 break;
1244 case 32:
1245 if (regno < 16)
1246 ((u32 *)info->pseudo_palette)[regno] =
1247 ((transp & 0xff00) << 16) |
1248 ((red & 0xff00) << 8) |
1249 ((green & 0xff00) ) |
1250 ((blue & 0xff00) >> 8);
1251 break;
1252
1253 default:
1254 return 1;
1255 }
1256
1257 return 0;
1258 }
1259
savagefb_set_par_int(struct savagefb_par * par,struct savage_reg * reg)1260 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)
1261 {
1262 unsigned char tmp, cr3a, cr66, cr67;
1263
1264 DBG("savagefb_set_par_int");
1265
1266 par->SavageWaitIdle(par);
1267
1268 vga_out8(0x3c2, 0x23, par);
1269
1270 vga_out16(0x3d4, 0x4838, par);
1271 vga_out16(0x3d4, 0xa539, par);
1272 vga_out16(0x3c4, 0x0608, par);
1273
1274 vgaHWProtect(par, 1);
1275
1276 /*
1277 * Some Savage/MX and /IX systems go nuts when trying to exit the
1278 * server after WindowMaker has displayed a gradient background. I
1279 * haven't been able to find what causes it, but a non-destructive
1280 * switch to mode 3 here seems to eliminate the issue.
1281 */
1282
1283 VerticalRetraceWait(par);
1284 vga_out8(0x3d4, 0x67, par);
1285 cr67 = vga_in8(0x3d5, par);
1286 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1287
1288 vga_out8(0x3d4, 0x23, par);
1289 vga_out8(0x3d5, 0x00, par);
1290 vga_out8(0x3d4, 0x26, par);
1291 vga_out8(0x3d5, 0x00, par);
1292
1293 /* restore extended regs */
1294 vga_out8(0x3d4, 0x66, par);
1295 vga_out8(0x3d5, reg->CR66, par);
1296 vga_out8(0x3d4, 0x3a, par);
1297 vga_out8(0x3d5, reg->CR3A, par);
1298 vga_out8(0x3d4, 0x31, par);
1299 vga_out8(0x3d5, reg->CR31, par);
1300 vga_out8(0x3d4, 0x32, par);
1301 vga_out8(0x3d5, reg->CR32, par);
1302 vga_out8(0x3d4, 0x58, par);
1303 vga_out8(0x3d5, reg->CR58, par);
1304 vga_out8(0x3d4, 0x53, par);
1305 vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1306
1307 vga_out16(0x3c4, 0x0608, par);
1308
1309 /* Restore DCLK registers. */
1310
1311 vga_out8(0x3c4, 0x0e, par);
1312 vga_out8(0x3c5, reg->SR0E, par);
1313 vga_out8(0x3c4, 0x0f, par);
1314 vga_out8(0x3c5, reg->SR0F, par);
1315 vga_out8(0x3c4, 0x29, par);
1316 vga_out8(0x3c5, reg->SR29, par);
1317 vga_out8(0x3c4, 0x15, par);
1318 vga_out8(0x3c5, reg->SR15, par);
1319
1320 /* Restore flat panel expansion registers. */
1321 if (par->chip == S3_SAVAGE_MX) {
1322 int i;
1323
1324 for (i = 0; i < 8; i++) {
1325 vga_out8(0x3c4, 0x54+i, par);
1326 vga_out8(0x3c5, reg->SR54[i], par);
1327 }
1328 }
1329
1330 vgaHWRestore (par, reg);
1331
1332 /* extended mode timing registers */
1333 vga_out8(0x3d4, 0x53, par);
1334 vga_out8(0x3d5, reg->CR53, par);
1335 vga_out8(0x3d4, 0x5d, par);
1336 vga_out8(0x3d5, reg->CR5D, par);
1337 vga_out8(0x3d4, 0x5e, par);
1338 vga_out8(0x3d5, reg->CR5E, par);
1339 vga_out8(0x3d4, 0x3b, par);
1340 vga_out8(0x3d5, reg->CR3B, par);
1341 vga_out8(0x3d4, 0x3c, par);
1342 vga_out8(0x3d5, reg->CR3C, par);
1343 vga_out8(0x3d4, 0x43, par);
1344 vga_out8(0x3d5, reg->CR43, par);
1345 vga_out8(0x3d4, 0x65, par);
1346 vga_out8(0x3d5, reg->CR65, par);
1347
1348 /* restore the desired video mode with cr67 */
1349 vga_out8(0x3d4, 0x67, par);
1350 /* following part not present in X11 driver */
1351 cr67 = vga_in8(0x3d5, par) & 0xf;
1352 vga_out8(0x3d5, 0x50 | cr67, par);
1353 mdelay(10);
1354 vga_out8(0x3d4, 0x67, par);
1355 /* end of part */
1356 vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1357
1358 /* other mode timing and extended regs */
1359 vga_out8(0x3d4, 0x34, par);
1360 vga_out8(0x3d5, reg->CR34, par);
1361 vga_out8(0x3d4, 0x40, par);
1362 vga_out8(0x3d5, reg->CR40, par);
1363 vga_out8(0x3d4, 0x42, par);
1364 vga_out8(0x3d5, reg->CR42, par);
1365 vga_out8(0x3d4, 0x45, par);
1366 vga_out8(0x3d5, reg->CR45, par);
1367 vga_out8(0x3d4, 0x50, par);
1368 vga_out8(0x3d5, reg->CR50, par);
1369 vga_out8(0x3d4, 0x51, par);
1370 vga_out8(0x3d5, reg->CR51, par);
1371
1372 /* memory timings */
1373 vga_out8(0x3d4, 0x36, par);
1374 vga_out8(0x3d5, reg->CR36, par);
1375 vga_out8(0x3d4, 0x60, par);
1376 vga_out8(0x3d5, reg->CR60, par);
1377 vga_out8(0x3d4, 0x68, par);
1378 vga_out8(0x3d5, reg->CR68, par);
1379 vga_out8(0x3d4, 0x69, par);
1380 vga_out8(0x3d5, reg->CR69, par);
1381 vga_out8(0x3d4, 0x6f, par);
1382 vga_out8(0x3d5, reg->CR6F, par);
1383
1384 vga_out8(0x3d4, 0x33, par);
1385 vga_out8(0x3d5, reg->CR33, par);
1386 vga_out8(0x3d4, 0x86, par);
1387 vga_out8(0x3d5, reg->CR86, par);
1388 vga_out8(0x3d4, 0x88, par);
1389 vga_out8(0x3d5, reg->CR88, par);
1390 vga_out8(0x3d4, 0x90, par);
1391 vga_out8(0x3d5, reg->CR90, par);
1392 vga_out8(0x3d4, 0x91, par);
1393 vga_out8(0x3d5, reg->CR91, par);
1394
1395 if (par->chip == S3_SAVAGE4) {
1396 vga_out8(0x3d4, 0xb0, par);
1397 vga_out8(0x3d5, reg->CRB0, par);
1398 }
1399
1400 vga_out8(0x3d4, 0x32, par);
1401 vga_out8(0x3d5, reg->CR32, par);
1402
1403 /* unlock extended seq regs */
1404 vga_out8(0x3c4, 0x08, par);
1405 vga_out8(0x3c5, 0x06, par);
1406
1407 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1408 * that we should leave the default SR10 and SR11 values there.
1409 */
1410 if (reg->SR10 != 255) {
1411 vga_out8(0x3c4, 0x10, par);
1412 vga_out8(0x3c5, reg->SR10, par);
1413 vga_out8(0x3c4, 0x11, par);
1414 vga_out8(0x3c5, reg->SR11, par);
1415 }
1416
1417 /* restore extended seq regs for dclk */
1418 vga_out8(0x3c4, 0x0e, par);
1419 vga_out8(0x3c5, reg->SR0E, par);
1420 vga_out8(0x3c4, 0x0f, par);
1421 vga_out8(0x3c5, reg->SR0F, par);
1422 vga_out8(0x3c4, 0x12, par);
1423 vga_out8(0x3c5, reg->SR12, par);
1424 vga_out8(0x3c4, 0x13, par);
1425 vga_out8(0x3c5, reg->SR13, par);
1426 vga_out8(0x3c4, 0x29, par);
1427 vga_out8(0x3c5, reg->SR29, par);
1428 vga_out8(0x3c4, 0x18, par);
1429 vga_out8(0x3c5, reg->SR18, par);
1430
1431 /* load new m, n pll values for dclk & mclk */
1432 vga_out8(0x3c4, 0x15, par);
1433 tmp = vga_in8(0x3c5, par) & ~0x21;
1434
1435 vga_out8(0x3c5, tmp | 0x03, par);
1436 vga_out8(0x3c5, tmp | 0x23, par);
1437 vga_out8(0x3c5, tmp | 0x03, par);
1438 vga_out8(0x3c5, reg->SR15, par);
1439 udelay(100);
1440
1441 vga_out8(0x3c4, 0x30, par);
1442 vga_out8(0x3c5, reg->SR30, par);
1443 vga_out8(0x3c4, 0x08, par);
1444 vga_out8(0x3c5, reg->SR08, par);
1445
1446 /* now write out cr67 in full, possibly starting STREAMS */
1447 VerticalRetraceWait(par);
1448 vga_out8(0x3d4, 0x67, par);
1449 vga_out8(0x3d5, reg->CR67, par);
1450
1451 vga_out8(0x3d4, 0x66, par);
1452 cr66 = vga_in8(0x3d5, par);
1453 vga_out8(0x3d5, cr66 | 0x80, par);
1454 vga_out8(0x3d4, 0x3a, par);
1455 cr3a = vga_in8(0x3d5, par);
1456 vga_out8(0x3d5, cr3a | 0x80, par);
1457
1458 if (par->chip != S3_SAVAGE_MX) {
1459 VerticalRetraceWait(par);
1460 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1461 par->SavageWaitIdle(par);
1462 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1463 par->SavageWaitIdle(par);
1464 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1465 par->SavageWaitIdle(par);
1466 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1467 }
1468
1469 vga_out8(0x3d4, 0x66, par);
1470 vga_out8(0x3d5, cr66, par);
1471 vga_out8(0x3d4, 0x3a, par);
1472 vga_out8(0x3d5, cr3a, par);
1473
1474 SavageSetup2DEngine(par);
1475 vgaHWProtect(par, 0);
1476 }
1477
savagefb_update_start(struct savagefb_par * par,int base)1478 static void savagefb_update_start(struct savagefb_par *par, int base)
1479 {
1480 /* program the start address registers */
1481 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1482 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1483 vga_out8(0x3d4, 0x69, par);
1484 vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1485 }
1486
1487
savagefb_set_fix(struct fb_info * info)1488 static void savagefb_set_fix(struct fb_info *info)
1489 {
1490 info->fix.line_length = info->var.xres_virtual *
1491 info->var.bits_per_pixel / 8;
1492
1493 if (info->var.bits_per_pixel == 8) {
1494 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1495 info->fix.xpanstep = 4;
1496 } else {
1497 info->fix.visual = FB_VISUAL_TRUECOLOR;
1498 info->fix.xpanstep = 2;
1499 }
1500
1501 }
1502
savagefb_set_par(struct fb_info * info)1503 static int savagefb_set_par(struct fb_info *info)
1504 {
1505 struct savagefb_par *par = info->par;
1506 struct fb_var_screeninfo *var = &info->var;
1507 int err;
1508
1509 DBG("savagefb_set_par");
1510 err = savagefb_decode_var(var, par, &par->state);
1511 if (err)
1512 return err;
1513
1514 if (par->dacSpeedBpp <= 0) {
1515 if (var->bits_per_pixel > 24)
1516 par->dacSpeedBpp = par->clock[3];
1517 else if (var->bits_per_pixel >= 24)
1518 par->dacSpeedBpp = par->clock[2];
1519 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1520 par->dacSpeedBpp = par->clock[1];
1521 else if (var->bits_per_pixel <= 8)
1522 par->dacSpeedBpp = par->clock[0];
1523 }
1524
1525 /* Set ramdac limits */
1526 par->maxClock = par->dacSpeedBpp;
1527 par->minClock = 10000;
1528
1529 savagefb_set_par_int(par, &par->state);
1530 fb_set_cmap(&info->cmap, info);
1531 savagefb_set_fix(info);
1532 savagefb_set_clip(info);
1533
1534 SavagePrintRegs(par);
1535 return 0;
1536 }
1537
1538 /*
1539 * Pan or Wrap the Display
1540 */
savagefb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)1541 static int savagefb_pan_display(struct fb_var_screeninfo *var,
1542 struct fb_info *info)
1543 {
1544 struct savagefb_par *par = info->par;
1545 int base;
1546
1547 base = (var->yoffset * info->fix.line_length
1548 + (var->xoffset & ~1) * ((info->var.bits_per_pixel+7) / 8)) >> 2;
1549
1550 savagefb_update_start(par, base);
1551 return 0;
1552 }
1553
savagefb_blank(int blank,struct fb_info * info)1554 static int savagefb_blank(int blank, struct fb_info *info)
1555 {
1556 struct savagefb_par *par = info->par;
1557 u8 sr8 = 0, srd = 0;
1558
1559 if (par->display_type == DISP_CRT) {
1560 vga_out8(0x3c4, 0x08, par);
1561 sr8 = vga_in8(0x3c5, par);
1562 sr8 |= 0x06;
1563 vga_out8(0x3c5, sr8, par);
1564 vga_out8(0x3c4, 0x0d, par);
1565 srd = vga_in8(0x3c5, par);
1566 srd &= 0x50;
1567
1568 switch (blank) {
1569 case FB_BLANK_UNBLANK:
1570 case FB_BLANK_NORMAL:
1571 break;
1572 case FB_BLANK_VSYNC_SUSPEND:
1573 srd |= 0x10;
1574 break;
1575 case FB_BLANK_HSYNC_SUSPEND:
1576 srd |= 0x40;
1577 break;
1578 case FB_BLANK_POWERDOWN:
1579 srd |= 0x50;
1580 break;
1581 }
1582
1583 vga_out8(0x3c4, 0x0d, par);
1584 vga_out8(0x3c5, srd, par);
1585 }
1586
1587 if (par->display_type == DISP_LCD ||
1588 par->display_type == DISP_DFP) {
1589 switch(blank) {
1590 case FB_BLANK_UNBLANK:
1591 case FB_BLANK_NORMAL:
1592 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1593 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1594 break;
1595 case FB_BLANK_VSYNC_SUSPEND:
1596 case FB_BLANK_HSYNC_SUSPEND:
1597 case FB_BLANK_POWERDOWN:
1598 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1599 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1600 break;
1601 }
1602 }
1603
1604 return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1605 }
1606
savagefb_open(struct fb_info * info,int user)1607 static int savagefb_open(struct fb_info *info, int user)
1608 {
1609 struct savagefb_par *par = info->par;
1610
1611 mutex_lock(&par->open_lock);
1612
1613 if (!par->open_count) {
1614 memset(&par->vgastate, 0, sizeof(par->vgastate));
1615 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS |
1616 VGA_SAVE_MODE;
1617 par->vgastate.vgabase = par->mmio.vbase + 0x8000;
1618 save_vga(&par->vgastate);
1619 savage_get_default_par(par, &par->initial);
1620 }
1621
1622 par->open_count++;
1623 mutex_unlock(&par->open_lock);
1624 return 0;
1625 }
1626
savagefb_release(struct fb_info * info,int user)1627 static int savagefb_release(struct fb_info *info, int user)
1628 {
1629 struct savagefb_par *par = info->par;
1630
1631 mutex_lock(&par->open_lock);
1632
1633 if (par->open_count == 1) {
1634 savage_set_default_par(par, &par->initial);
1635 restore_vga(&par->vgastate);
1636 }
1637
1638 par->open_count--;
1639 mutex_unlock(&par->open_lock);
1640 return 0;
1641 }
1642
1643 static const struct fb_ops savagefb_ops = {
1644 .owner = THIS_MODULE,
1645 .fb_open = savagefb_open,
1646 .fb_release = savagefb_release,
1647 .fb_check_var = savagefb_check_var,
1648 .fb_set_par = savagefb_set_par,
1649 .fb_setcolreg = savagefb_setcolreg,
1650 .fb_pan_display = savagefb_pan_display,
1651 .fb_blank = savagefb_blank,
1652 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1653 .fb_fillrect = savagefb_fillrect,
1654 .fb_copyarea = savagefb_copyarea,
1655 .fb_imageblit = savagefb_imageblit,
1656 .fb_sync = savagefb_sync,
1657 #else
1658 .fb_fillrect = cfb_fillrect,
1659 .fb_copyarea = cfb_copyarea,
1660 .fb_imageblit = cfb_imageblit,
1661 #endif
1662 };
1663
1664 /* --------------------------------------------------------------------- */
1665
1666 static const struct fb_var_screeninfo savagefb_var800x600x8 = {
1667 .accel_flags = FB_ACCELF_TEXT,
1668 .xres = 800,
1669 .yres = 600,
1670 .xres_virtual = 800,
1671 .yres_virtual = 600,
1672 .bits_per_pixel = 8,
1673 .pixclock = 25000,
1674 .left_margin = 88,
1675 .right_margin = 40,
1676 .upper_margin = 23,
1677 .lower_margin = 1,
1678 .hsync_len = 128,
1679 .vsync_len = 4,
1680 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1681 .vmode = FB_VMODE_NONINTERLACED
1682 };
1683
savage_enable_mmio(struct savagefb_par * par)1684 static void savage_enable_mmio(struct savagefb_par *par)
1685 {
1686 unsigned char val;
1687
1688 DBG("savage_enable_mmio\n");
1689
1690 val = vga_in8(0x3c3, par);
1691 vga_out8(0x3c3, val | 0x01, par);
1692 val = vga_in8(0x3cc, par);
1693 vga_out8(0x3c2, val | 0x01, par);
1694
1695 if (par->chip >= S3_SAVAGE4) {
1696 vga_out8(0x3d4, 0x40, par);
1697 val = vga_in8(0x3d5, par);
1698 vga_out8(0x3d5, val | 1, par);
1699 }
1700 }
1701
1702
savage_disable_mmio(struct savagefb_par * par)1703 static void savage_disable_mmio(struct savagefb_par *par)
1704 {
1705 unsigned char val;
1706
1707 DBG("savage_disable_mmio\n");
1708
1709 if (par->chip >= S3_SAVAGE4) {
1710 vga_out8(0x3d4, 0x40, par);
1711 val = vga_in8(0x3d5, par);
1712 vga_out8(0x3d5, val | 1, par);
1713 }
1714 }
1715
1716
savage_map_mmio(struct fb_info * info)1717 static int savage_map_mmio(struct fb_info *info)
1718 {
1719 struct savagefb_par *par = info->par;
1720 DBG("savage_map_mmio");
1721
1722 if (S3_SAVAGE3D_SERIES(par->chip))
1723 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1724 SAVAGE_NEWMMIO_REGBASE_S3;
1725 else
1726 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1727 SAVAGE_NEWMMIO_REGBASE_S4;
1728
1729 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1730
1731 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1732 if (!par->mmio.vbase) {
1733 printk("savagefb: unable to map memory mapped IO\n");
1734 return -ENOMEM;
1735 } else
1736 printk(KERN_INFO "savagefb: mapped io at %p\n",
1737 par->mmio.vbase);
1738
1739 info->fix.mmio_start = par->mmio.pbase;
1740 info->fix.mmio_len = par->mmio.len;
1741
1742 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1743 par->bci_ptr = 0;
1744
1745 savage_enable_mmio(par);
1746
1747 return 0;
1748 }
1749
savage_unmap_mmio(struct fb_info * info)1750 static void savage_unmap_mmio(struct fb_info *info)
1751 {
1752 struct savagefb_par *par = info->par;
1753 DBG("savage_unmap_mmio");
1754
1755 savage_disable_mmio(par);
1756
1757 if (par->mmio.vbase) {
1758 iounmap(par->mmio.vbase);
1759 par->mmio.vbase = NULL;
1760 }
1761 }
1762
savage_map_video(struct fb_info * info,int video_len)1763 static int savage_map_video(struct fb_info *info, int video_len)
1764 {
1765 struct savagefb_par *par = info->par;
1766 int resource;
1767
1768 DBG("savage_map_video");
1769
1770 if (S3_SAVAGE3D_SERIES(par->chip))
1771 resource = 0;
1772 else
1773 resource = 1;
1774
1775 par->video.pbase = pci_resource_start(par->pcidev, resource);
1776 par->video.len = video_len;
1777 par->video.vbase = ioremap_wc(par->video.pbase, par->video.len);
1778
1779 if (!par->video.vbase) {
1780 printk("savagefb: unable to map screen memory\n");
1781 return -ENOMEM;
1782 } else
1783 printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
1784 "pbase == %x\n", par->video.vbase, par->video.pbase);
1785
1786 info->fix.smem_start = par->video.pbase;
1787 info->fix.smem_len = par->video.len - par->cob_size;
1788 info->screen_base = par->video.vbase;
1789 par->video.wc_cookie = arch_phys_wc_add(par->video.pbase, video_len);
1790
1791 /* Clear framebuffer, it's all white in memory after boot */
1792 memset_io(par->video.vbase, 0, par->video.len);
1793
1794 return 0;
1795 }
1796
savage_unmap_video(struct fb_info * info)1797 static void savage_unmap_video(struct fb_info *info)
1798 {
1799 struct savagefb_par *par = info->par;
1800
1801 DBG("savage_unmap_video");
1802
1803 if (par->video.vbase) {
1804 arch_phys_wc_del(par->video.wc_cookie);
1805 iounmap(par->video.vbase);
1806 par->video.vbase = NULL;
1807 info->screen_base = NULL;
1808 }
1809 }
1810
savage_init_hw(struct savagefb_par * par)1811 static int savage_init_hw(struct savagefb_par *par)
1812 {
1813 unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1814
1815 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1816 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 };
1817 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1818 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1819 int videoRam, videoRambytes, dvi;
1820
1821 DBG("savage_init_hw");
1822
1823 /* unprotect CRTC[0-7] */
1824 vga_out8(0x3d4, 0x11, par);
1825 tmp = vga_in8(0x3d5, par);
1826 vga_out8(0x3d5, tmp & 0x7f, par);
1827
1828 /* unlock extended regs */
1829 vga_out16(0x3d4, 0x4838, par);
1830 vga_out16(0x3d4, 0xa039, par);
1831 vga_out16(0x3c4, 0x0608, par);
1832
1833 vga_out8(0x3d4, 0x40, par);
1834 tmp = vga_in8(0x3d5, par);
1835 vga_out8(0x3d5, tmp & ~0x01, par);
1836
1837 /* unlock sys regs */
1838 vga_out8(0x3d4, 0x38, par);
1839 vga_out8(0x3d5, 0x48, par);
1840
1841 /* Unlock system registers. */
1842 vga_out16(0x3d4, 0x4838, par);
1843
1844 /* Next go on to detect amount of installed ram */
1845
1846 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
1847 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
1848
1849 /* Compute the amount of video memory and offscreen memory. */
1850
1851 switch (par->chip) {
1852 case S3_SAVAGE3D:
1853 videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
1854 break;
1855
1856 case S3_SAVAGE4:
1857 /*
1858 * The Savage4 has one ugly special case to consider. On
1859 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1860 * when it really means 8MB. Why do it the same when you
1861 * can do it different...
1862 */
1863 vga_out8(0x3d4, 0x68, par); /* memory control 1 */
1864 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1865 RamSavage4[1] = 8;
1866 fallthrough;
1867
1868 case S3_SAVAGE2000:
1869 videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
1870 break;
1871
1872 case S3_SAVAGE_MX:
1873 case S3_SUPERSAVAGE:
1874 videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
1875 break;
1876
1877 case S3_PROSAVAGE:
1878 case S3_PROSAVAGEDDR:
1879 case S3_TWISTER:
1880 videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
1881 break;
1882
1883 default:
1884 /* How did we get here? */
1885 videoRam = 0;
1886 break;
1887 }
1888
1889 videoRambytes = videoRam * 1024;
1890
1891 printk(KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
1892
1893 /* reset graphics engine to avoid memory corruption */
1894 vga_out8(0x3d4, 0x66, par);
1895 cr66 = vga_in8(0x3d5, par);
1896 vga_out8(0x3d5, cr66 | 0x02, par);
1897 usleep_range(10000, 11000);
1898
1899 vga_out8(0x3d4, 0x66, par);
1900 vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */
1901 usleep_range(10000, 11000);
1902
1903
1904 /*
1905 * reset memory interface, 3D engine, AGP master, PCI master,
1906 * master engine unit, motion compensation/LPB
1907 */
1908 vga_out8(0x3d4, 0x3f, par);
1909 cr3f = vga_in8(0x3d5, par);
1910 vga_out8(0x3d5, cr3f | 0x08, par);
1911 usleep_range(10000, 11000);
1912
1913 vga_out8(0x3d4, 0x3f, par);
1914 vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */
1915 usleep_range(10000, 11000);
1916
1917 /* Savage ramdac speeds */
1918 par->numClocks = 4;
1919 par->clock[0] = 250000;
1920 par->clock[1] = 250000;
1921 par->clock[2] = 220000;
1922 par->clock[3] = 220000;
1923
1924 /* detect current mclk */
1925 vga_out8(0x3c4, 0x08, par);
1926 sr8 = vga_in8(0x3c5, par);
1927 vga_out8(0x3c5, 0x06, par);
1928 vga_out8(0x3c4, 0x10, par);
1929 n = vga_in8(0x3c5, par);
1930 vga_out8(0x3c4, 0x11, par);
1931 m = vga_in8(0x3c5, par);
1932 vga_out8(0x3c4, 0x08, par);
1933 vga_out8(0x3c5, sr8, par);
1934 m &= 0x7f;
1935 n1 = n & 0x1f;
1936 n2 = (n >> 5) & 0x03;
1937 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1938 printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1939 par->MCLK);
1940
1941 /* check for DVI/flat panel */
1942 dvi = 0;
1943
1944 if (par->chip == S3_SAVAGE4) {
1945 unsigned char sr30 = 0x00;
1946
1947 vga_out8(0x3c4, 0x30, par);
1948 /* clear bit 1 */
1949 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1950 sr30 = vga_in8(0x3c5, par);
1951 if (sr30 & 0x02 /*0x04 */) {
1952 dvi = 1;
1953 printk("savagefb: Digital Flat Panel Detected\n");
1954 }
1955 }
1956
1957 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1958 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
1959 par->display_type = DISP_LCD;
1960 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1961 par->display_type = DISP_DFP;
1962 else
1963 par->display_type = DISP_CRT;
1964
1965 /* Check LCD panel parrmation */
1966
1967 if (par->display_type == DISP_LCD) {
1968 unsigned char cr6b = VGArCR(0x6b, par);
1969
1970 int panelX = (VGArSEQ(0x61, par) +
1971 ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1972 int panelY = (VGArSEQ(0x69, par) +
1973 ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1974
1975 char * sTechnology = "Unknown";
1976
1977 /* OK, I admit it. I don't know how to limit the max dot clock
1978 * for LCD panels of various sizes. I thought I copied the
1979 * formula from the BIOS, but many users have parrmed me of
1980 * my folly.
1981 *
1982 * Instead, I'll abandon any attempt to automatically limit the
1983 * clock, and add an LCDClock option to XF86Config. Some day,
1984 * I should come back to this.
1985 */
1986
1987 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
1988 ActiveCRT = 0x01,
1989 ActiveLCD = 0x02,
1990 ActiveTV = 0x04,
1991 ActiveCRT2 = 0x20,
1992 ActiveDUO = 0x80
1993 };
1994
1995 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
1996 sTechnology = "TFT";
1997 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
1998 sTechnology = "DSTN";
1999 } else {
2000 sTechnology = "STN";
2001 }
2002
2003 printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
2004 panelX, panelY, sTechnology,
2005 cr6b & ActiveLCD ? "and active" : "but not active");
2006
2007 if (cr6b & ActiveLCD) {
2008 /*
2009 * If the LCD is active and panel expansion is enabled,
2010 * we probably want to kill the HW cursor.
2011 */
2012
2013 printk(KERN_INFO "savagefb: Limiting video mode to "
2014 "%dx%d\n", panelX, panelY);
2015
2016 par->SavagePanelWidth = panelX;
2017 par->SavagePanelHeight = panelY;
2018
2019 } else
2020 par->display_type = DISP_CRT;
2021 }
2022
2023 savage_get_default_par(par, &par->state);
2024 par->save = par->state;
2025
2026 if (S3_SAVAGE4_SERIES(par->chip)) {
2027 /*
2028 * The Savage4 and ProSavage have COB coherency bugs which
2029 * render the buffer useless. We disable it.
2030 */
2031 par->cob_index = 2;
2032 par->cob_size = 0x8000 << par->cob_index;
2033 par->cob_offset = videoRambytes;
2034 } else {
2035 /* We use 128kB for the COB on all chips. */
2036
2037 par->cob_index = 7;
2038 par->cob_size = 0x400 << par->cob_index;
2039 par->cob_offset = videoRambytes - par->cob_size;
2040 }
2041
2042 return videoRambytes;
2043 }
2044
savage_init_fb_info(struct fb_info * info,struct pci_dev * dev,const struct pci_device_id * id)2045 static int savage_init_fb_info(struct fb_info *info, struct pci_dev *dev,
2046 const struct pci_device_id *id)
2047 {
2048 struct savagefb_par *par = info->par;
2049 int err = 0;
2050
2051 par->pcidev = dev;
2052
2053 info->fix.type = FB_TYPE_PACKED_PIXELS;
2054 info->fix.type_aux = 0;
2055 info->fix.ypanstep = 1;
2056 info->fix.ywrapstep = 0;
2057 info->fix.accel = id->driver_data;
2058
2059 switch (info->fix.accel) {
2060 case FB_ACCEL_SUPERSAVAGE:
2061 par->chip = S3_SUPERSAVAGE;
2062 snprintf(info->fix.id, 16, "SuperSavage");
2063 break;
2064 case FB_ACCEL_SAVAGE4:
2065 par->chip = S3_SAVAGE4;
2066 snprintf(info->fix.id, 16, "Savage4");
2067 break;
2068 case FB_ACCEL_SAVAGE3D:
2069 par->chip = S3_SAVAGE3D;
2070 snprintf(info->fix.id, 16, "Savage3D");
2071 break;
2072 case FB_ACCEL_SAVAGE3D_MV:
2073 par->chip = S3_SAVAGE3D;
2074 snprintf(info->fix.id, 16, "Savage3D-MV");
2075 break;
2076 case FB_ACCEL_SAVAGE2000:
2077 par->chip = S3_SAVAGE2000;
2078 snprintf(info->fix.id, 16, "Savage2000");
2079 break;
2080 case FB_ACCEL_SAVAGE_MX_MV:
2081 par->chip = S3_SAVAGE_MX;
2082 snprintf(info->fix.id, 16, "Savage/MX-MV");
2083 break;
2084 case FB_ACCEL_SAVAGE_MX:
2085 par->chip = S3_SAVAGE_MX;
2086 snprintf(info->fix.id, 16, "Savage/MX");
2087 break;
2088 case FB_ACCEL_SAVAGE_IX_MV:
2089 par->chip = S3_SAVAGE_MX;
2090 snprintf(info->fix.id, 16, "Savage/IX-MV");
2091 break;
2092 case FB_ACCEL_SAVAGE_IX:
2093 par->chip = S3_SAVAGE_MX;
2094 snprintf(info->fix.id, 16, "Savage/IX");
2095 break;
2096 case FB_ACCEL_PROSAVAGE_PM:
2097 par->chip = S3_PROSAVAGE;
2098 snprintf(info->fix.id, 16, "ProSavagePM");
2099 break;
2100 case FB_ACCEL_PROSAVAGE_KM:
2101 par->chip = S3_PROSAVAGE;
2102 snprintf(info->fix.id, 16, "ProSavageKM");
2103 break;
2104 case FB_ACCEL_S3TWISTER_P:
2105 par->chip = S3_TWISTER;
2106 snprintf(info->fix.id, 16, "TwisterP");
2107 break;
2108 case FB_ACCEL_S3TWISTER_K:
2109 par->chip = S3_TWISTER;
2110 snprintf(info->fix.id, 16, "TwisterK");
2111 break;
2112 case FB_ACCEL_PROSAVAGE_DDR:
2113 par->chip = S3_PROSAVAGEDDR;
2114 snprintf(info->fix.id, 16, "ProSavageDDR");
2115 break;
2116 case FB_ACCEL_PROSAVAGE_DDRK:
2117 par->chip = S3_PROSAVAGEDDR;
2118 snprintf(info->fix.id, 16, "ProSavage8");
2119 break;
2120 }
2121
2122 if (S3_SAVAGE3D_SERIES(par->chip)) {
2123 par->SavageWaitIdle = savage3D_waitidle;
2124 par->SavageWaitFifo = savage3D_waitfifo;
2125 } else if (S3_SAVAGE4_SERIES(par->chip) ||
2126 S3_SUPERSAVAGE == par->chip) {
2127 par->SavageWaitIdle = savage4_waitidle;
2128 par->SavageWaitFifo = savage4_waitfifo;
2129 } else {
2130 par->SavageWaitIdle = savage2000_waitidle;
2131 par->SavageWaitFifo = savage2000_waitfifo;
2132 }
2133
2134 info->var.nonstd = 0;
2135 info->var.activate = FB_ACTIVATE_NOW;
2136 info->var.width = -1;
2137 info->var.height = -1;
2138 info->var.accel_flags = 0;
2139
2140 info->fbops = &savagefb_ops;
2141 info->flags = FBINFO_HWACCEL_YPAN |
2142 FBINFO_HWACCEL_XPAN;
2143
2144 info->pseudo_palette = par->pseudo_palette;
2145
2146 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2147 /* FIFO size + padding for commands */
2148 info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL);
2149
2150 err = -ENOMEM;
2151 if (info->pixmap.addr) {
2152 info->pixmap.size = 8*1024;
2153 info->pixmap.scan_align = 4;
2154 info->pixmap.buf_align = 4;
2155 info->pixmap.access_align = 32;
2156
2157 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
2158 if (!err)
2159 info->flags |= FBINFO_HWACCEL_COPYAREA |
2160 FBINFO_HWACCEL_FILLRECT |
2161 FBINFO_HWACCEL_IMAGEBLIT;
2162 else
2163 kfree(info->pixmap.addr);
2164 }
2165 #endif
2166 return err;
2167 }
2168
2169 /* --------------------------------------------------------------------- */
2170
savagefb_probe(struct pci_dev * dev,const struct pci_device_id * id)2171 static int savagefb_probe(struct pci_dev *dev, const struct pci_device_id *id)
2172 {
2173 struct fb_info *info;
2174 struct savagefb_par *par;
2175 u_int h_sync, v_sync;
2176 unsigned char __maybe_unused *edid;
2177 int err, lpitch;
2178 int video_len;
2179
2180 DBG("savagefb_probe");
2181
2182 err = aperture_remove_conflicting_pci_devices(dev, "savagefb");
2183 if (err)
2184 return err;
2185
2186 info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
2187 if (!info)
2188 return -ENOMEM;
2189 par = info->par;
2190 mutex_init(&par->open_lock);
2191 err = pci_enable_device(dev);
2192 if (err)
2193 goto failed_enable;
2194
2195 if ((err = pci_request_regions(dev, "savagefb"))) {
2196 printk(KERN_ERR "cannot request PCI regions\n");
2197 goto failed_enable;
2198 }
2199
2200 err = -ENOMEM;
2201
2202 if ((err = savage_init_fb_info(info, dev, id)))
2203 goto failed_init;
2204
2205 err = savage_map_mmio(info);
2206 if (err)
2207 goto failed_mmio;
2208
2209 video_len = savage_init_hw(par);
2210 /* FIXME: can't be negative */
2211 if (video_len < 0) {
2212 err = video_len;
2213 goto failed_mmio;
2214 }
2215
2216 err = savage_map_video(info, video_len);
2217 if (err)
2218 goto failed_video;
2219
2220 INIT_LIST_HEAD(&info->modelist);
2221 #if defined(CONFIG_FB_SAVAGE_I2C)
2222 savagefb_create_i2c_busses(info);
2223 savagefb_probe_i2c_connector(info, &edid);
2224 fb_edid_to_monspecs(edid, &info->monspecs);
2225 kfree(edid);
2226 fb_videomode_to_modelist(info->monspecs.modedb,
2227 info->monspecs.modedb_len,
2228 &info->modelist);
2229 #endif
2230 info->var = savagefb_var800x600x8;
2231 /* if a panel was detected, default to a CVT mode instead */
2232 if (par->SavagePanelWidth) {
2233 struct fb_videomode cvt_mode;
2234
2235 memset(&cvt_mode, 0, sizeof(cvt_mode));
2236 cvt_mode.xres = par->SavagePanelWidth;
2237 cvt_mode.yres = par->SavagePanelHeight;
2238 cvt_mode.refresh = 60;
2239 /* FIXME: if we know there is only the panel
2240 * we can enable reduced blanking as well */
2241 if (fb_find_mode_cvt(&cvt_mode, 0, 0))
2242 printk(KERN_WARNING "No CVT mode found for panel\n");
2243 else if (fb_find_mode(&info->var, info, NULL, NULL, 0,
2244 &cvt_mode, 0) != 3)
2245 info->var = savagefb_var800x600x8;
2246 }
2247
2248 if (mode_option) {
2249 fb_find_mode(&info->var, info, mode_option,
2250 info->monspecs.modedb, info->monspecs.modedb_len,
2251 NULL, 8);
2252 } else if (info->monspecs.modedb != NULL) {
2253 const struct fb_videomode *mode;
2254
2255 mode = fb_find_best_display(&info->monspecs, &info->modelist);
2256 savage_update_var(&info->var, mode);
2257 }
2258
2259 /* maximize virtual vertical length */
2260 lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2261 info->var.yres_virtual = info->fix.smem_len/lpitch;
2262
2263 if (info->var.yres_virtual < info->var.yres) {
2264 err = -ENOMEM;
2265 goto failed;
2266 }
2267
2268 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2269 /*
2270 * The clipping coordinates are masked with 0xFFF, so limit our
2271 * virtual resolutions to these sizes.
2272 */
2273 if (info->var.yres_virtual > 0x1000)
2274 info->var.yres_virtual = 0x1000;
2275
2276 if (info->var.xres_virtual > 0x1000)
2277 info->var.xres_virtual = 0x1000;
2278 #endif
2279 err = savagefb_check_var(&info->var, info);
2280 if (err)
2281 goto failed;
2282
2283 savagefb_set_fix(info);
2284
2285 /*
2286 * Calculate the hsync and vsync frequencies. Note that
2287 * we split the 1e12 constant up so that we can preserve
2288 * the precision and fit the results into 32-bit registers.
2289 * (1953125000 * 512 = 1e12)
2290 */
2291 h_sync = 1953125000 / info->var.pixclock;
2292 h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2293 info->var.right_margin +
2294 info->var.hsync_len);
2295 v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2296 info->var.lower_margin + info->var.vsync_len);
2297
2298 printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2299 "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2300 info->fix.smem_len >> 10,
2301 info->var.xres, info->var.yres,
2302 h_sync / 1000, h_sync % 1000, v_sync);
2303
2304
2305 fb_destroy_modedb(info->monspecs.modedb);
2306 info->monspecs.modedb = NULL;
2307
2308 err = register_framebuffer(info);
2309 if (err < 0)
2310 goto failed;
2311
2312 printk(KERN_INFO "fb: S3 %s frame buffer device\n",
2313 info->fix.id);
2314
2315 /*
2316 * Our driver data
2317 */
2318 pci_set_drvdata(dev, info);
2319
2320 return 0;
2321
2322 failed:
2323 #ifdef CONFIG_FB_SAVAGE_I2C
2324 savagefb_delete_i2c_busses(info);
2325 #endif
2326 fb_alloc_cmap(&info->cmap, 0, 0);
2327 savage_unmap_video(info);
2328 failed_video:
2329 savage_unmap_mmio(info);
2330 failed_mmio:
2331 kfree(info->pixmap.addr);
2332 failed_init:
2333 pci_release_regions(dev);
2334 failed_enable:
2335 framebuffer_release(info);
2336
2337 return err;
2338 }
2339
savagefb_remove(struct pci_dev * dev)2340 static void savagefb_remove(struct pci_dev *dev)
2341 {
2342 struct fb_info *info = pci_get_drvdata(dev);
2343
2344 DBG("savagefb_remove");
2345
2346 if (info) {
2347 unregister_framebuffer(info);
2348
2349 #ifdef CONFIG_FB_SAVAGE_I2C
2350 savagefb_delete_i2c_busses(info);
2351 #endif
2352 fb_alloc_cmap(&info->cmap, 0, 0);
2353 savage_unmap_video(info);
2354 savage_unmap_mmio(info);
2355 kfree(info->pixmap.addr);
2356 pci_release_regions(dev);
2357 framebuffer_release(info);
2358 }
2359 }
2360
savagefb_suspend_late(struct device * dev,pm_message_t mesg)2361 static int savagefb_suspend_late(struct device *dev, pm_message_t mesg)
2362 {
2363 struct fb_info *info = dev_get_drvdata(dev);
2364 struct savagefb_par *par = info->par;
2365
2366 DBG("savagefb_suspend");
2367
2368 if (mesg.event == PM_EVENT_PRETHAW)
2369 mesg.event = PM_EVENT_FREEZE;
2370 par->pm_state = mesg.event;
2371 dev->power.power_state = mesg;
2372
2373 /*
2374 * For PM_EVENT_FREEZE, do not power down so the console
2375 * can remain active.
2376 */
2377 if (mesg.event == PM_EVENT_FREEZE)
2378 return 0;
2379
2380 console_lock();
2381 fb_set_suspend(info, 1);
2382
2383 if (info->fbops->fb_sync)
2384 info->fbops->fb_sync(info);
2385
2386 savagefb_blank(FB_BLANK_POWERDOWN, info);
2387 savage_set_default_par(par, &par->save);
2388 savage_disable_mmio(par);
2389 console_unlock();
2390
2391 return 0;
2392 }
2393
savagefb_suspend(struct device * dev)2394 static int __maybe_unused savagefb_suspend(struct device *dev)
2395 {
2396 return savagefb_suspend_late(dev, PMSG_SUSPEND);
2397 }
2398
savagefb_hibernate(struct device * dev)2399 static int __maybe_unused savagefb_hibernate(struct device *dev)
2400 {
2401 return savagefb_suspend_late(dev, PMSG_HIBERNATE);
2402 }
2403
savagefb_freeze(struct device * dev)2404 static int __maybe_unused savagefb_freeze(struct device *dev)
2405 {
2406 return savagefb_suspend_late(dev, PMSG_FREEZE);
2407 }
2408
savagefb_resume(struct device * dev)2409 static int __maybe_unused savagefb_resume(struct device *dev)
2410 {
2411 struct fb_info *info = dev_get_drvdata(dev);
2412 struct savagefb_par *par = info->par;
2413 int cur_state = par->pm_state;
2414
2415 DBG("savage_resume");
2416
2417 par->pm_state = PM_EVENT_ON;
2418
2419 /*
2420 * The adapter was not powered down coming back from a
2421 * PM_EVENT_FREEZE.
2422 */
2423 if (cur_state == PM_EVENT_FREEZE)
2424 return 0;
2425
2426 console_lock();
2427
2428 savage_enable_mmio(par);
2429 savage_init_hw(par);
2430 savagefb_set_par(info);
2431 fb_set_suspend(info, 0);
2432 savagefb_blank(FB_BLANK_UNBLANK, info);
2433 console_unlock();
2434
2435 return 0;
2436 }
2437
2438 static const struct dev_pm_ops savagefb_pm_ops = {
2439 #ifdef CONFIG_PM_SLEEP
2440 .suspend = savagefb_suspend,
2441 .resume = savagefb_resume,
2442 .freeze = savagefb_freeze,
2443 .thaw = savagefb_resume,
2444 .poweroff = savagefb_hibernate,
2445 .restore = savagefb_resume,
2446 #endif
2447 };
2448
2449 static const struct pci_device_id savagefb_devices[] = {
2450 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2452
2453 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2455
2456 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2458
2459 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2461
2462 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2464
2465 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2467
2468 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2470
2471 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2472 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2473
2474 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2475 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2476
2477 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2478 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2479
2480 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2481 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2482
2483 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2485
2486 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2487 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2488
2489 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2491
2492 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2494
2495 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2497
2498 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2500
2501 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2502 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2503
2504 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2505 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2506
2507 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2509
2510 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2511 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2512
2513 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2514 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2515
2516 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2517 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2518
2519 {0, 0, 0, 0, 0, 0, 0}
2520 };
2521
2522 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2523
2524 static struct pci_driver savagefb_driver = {
2525 .name = "savagefb",
2526 .id_table = savagefb_devices,
2527 .probe = savagefb_probe,
2528 .driver.pm = &savagefb_pm_ops,
2529 .remove = savagefb_remove,
2530 };
2531
2532 /* **************************** exit-time only **************************** */
2533
savage_done(void)2534 static void __exit savage_done(void)
2535 {
2536 DBG("savage_done");
2537 pci_unregister_driver(&savagefb_driver);
2538 }
2539
2540
2541 /* ************************* init in-kernel code ************************** */
2542
savagefb_setup(char * options)2543 static int __init savagefb_setup(char *options)
2544 {
2545 #ifndef MODULE
2546 char *this_opt;
2547
2548 if (!options || !*options)
2549 return 0;
2550
2551 while ((this_opt = strsep(&options, ",")) != NULL) {
2552 mode_option = this_opt;
2553 }
2554 #endif /* !MODULE */
2555 return 0;
2556 }
2557
savagefb_init(void)2558 static int __init savagefb_init(void)
2559 {
2560 char *option;
2561
2562 DBG("savagefb_init");
2563
2564 if (fb_modesetting_disabled("savagefb"))
2565 return -ENODEV;
2566
2567 if (fb_get_options("savagefb", &option))
2568 return -ENODEV;
2569
2570 savagefb_setup(option);
2571 return pci_register_driver(&savagefb_driver);
2572
2573 }
2574
2575 module_init(savagefb_init);
2576 module_exit(savage_done);
2577
2578 module_param(mode_option, charp, 0);
2579 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
2580