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Searched refs:nvkm_mask (Results 1 – 25 of 132) sorted by relevance

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/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgt215.c45 nvkm_mask(device, 0x61c448 + soff, 0x80000002, 0x80000002); in gt215_sor_hda_eld()
58 nvkm_mask(device, 0x61c448 + ior->id * 0x800, mask, data); in gt215_sor_hda_hpd()
75 nvkm_mask(device, 0x61c1e0 + soff, mask, data); in gt215_sor_dp_audio()
104 nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010000); in gt215_sor_hdmi_infoframe_vsi()
115 nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010001); in gt215_sor_hdmi_infoframe_vsi()
127 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_sor_hdmi_infoframe_avi()
137 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000001); in gt215_sor_hdmi_infoframe_avi()
151 nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000); in gt215_sor_hdmi_ctrl()
152 nvkm_mask(device, 0x61c53c + soff, 0x00000001, 0x00000000); in gt215_sor_hdmi_ctrl()
153 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_sor_hdmi_ctrl()
[all …]
Dg84.c39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
74 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001); in g84_sor_hdmi_infoframe_avi()
89 nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000); in g84_sor_hdmi_ctrl()
90 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_ctrl()
95 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_ctrl()
99 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001); in g84_sor_hdmi_ctrl()
102 nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ in g84_sor_hdmi_ctrl()
103 nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ in g84_sor_hdmi_ctrl()
[all …]
Dg94.c39 nvkm_mask(device, 0x61c128 + loff, 0x0000003f, watermark); in g94_sor_dp_watermark()
49 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, TU << 2); in g94_sor_dp_activesym()
50 nvkm_mask(device, 0x61c128 + loff, 0x010f7f00, VTUa << 24 | VTUf << 16 | VTUi << 8); in g94_sor_dp_activesym()
59 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h); in g94_sor_dp_audio_sym()
60 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v); in g94_sor_dp_audio_sym()
98 nvkm_mask(device, 0x61c10c + loff, 0x0f001000, data); in g94_sor_dp_pattern()
112 nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask); in g94_sor_dp_power()
113 nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000); in g94_sor_dp_power()
135 nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor); in g94_sor_dp_links()
136 nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl); in g94_sor_dp_links()
[all …]
Dgf119.c42 nvkm_mask(device, 0x616548 + hoff, 0x00000070, head << 4); in gf119_sor_hda_device_entry()
56 nvkm_mask(device, 0x10ec10 + soff, 0x80000002, 0x80000002); in gf119_sor_hda_eld()
74 nvkm_mask(device, 0x10ec10 + soff, mask, data); in gf119_sor_hda_hpd()
90 nvkm_mask(device, 0x616610 + hoff, 0x0800003f, 0x08000000 | watermark); in gf119_sor_dp_watermark()
99 nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, h); in gf119_sor_dp_audio_sym()
100 nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, v); in gf119_sor_dp_audio_sym()
111 nvkm_mask(device, 0x616618 + hoff, mask, data); in gf119_sor_dp_audio()
124 nvkm_mask(device, 0x616588 + hoff, 0x00003f3f, (slot_nr << 8) | slot); in gf119_sor_dp_vcpi()
125 nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) | pbn); in gf119_sor_dp_vcpi()
167 nvkm_mask(device, 0x61c110 + soff, 0x1f1f1f1f, data); in gf119_sor_dp_pattern()
[all …]
Dgk104.c42 nvkm_mask(device, 0x690100 + hoff, 0x00010001, 0x00000000); in gk104_sor_hdmi_infoframe_vsi()
50 nvkm_mask(device, 0x690100 + hoff, 0x00000001, 0x00000001); in gk104_sor_hdmi_infoframe_vsi()
63 nvkm_mask(device, 0x690000 + hoff, 0x00000001, 0x00000000); in gk104_sor_hdmi_infoframe_avi()
73 nvkm_mask(device, 0x690000 + hoff, 0x00000001, 0x00000001); in gk104_sor_hdmi_infoframe_avi()
87 nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000); in gk104_sor_hdmi_ctrl()
88 nvkm_mask(device, 0x690100 + hdmi, 0x00000001, 0x00000000); in gk104_sor_hdmi_ctrl()
89 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000); in gk104_sor_hdmi_ctrl()
90 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000); in gk104_sor_hdmi_ctrl()
95 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000); in gk104_sor_hdmi_ctrl()
97 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000001); in gk104_sor_hdmi_ctrl()
[all …]
Dtu102.c38 nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn); in tu102_sor_dp_vcpi()
39 nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot); in tu102_sor_dp_vcpi()
58 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); in tu102_sor_dp_links()
62 nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000); in tu102_sor_dp_links()
63 nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001); in tu102_sor_dp_links()
65 nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl); in tu102_sor_dp_links()
115 nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000); in tu102_disp_init()
130 nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i); in tu102_disp_init()
151 nvkm_mask(device, 0x640004, 1 << i, 1 << i); in tu102_disp_init()
154 nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp); in tu102_disp_init()
[all …]
Dgv100.c43 nvkm_mask(device, 0x616528 + hoff, 0x00000070, head << 4); in gv100_sor_hda_device_entry()
59 nvkm_mask(device, 0x616550 + hoff, 0x0c00003f, 0x08000000 | watermark); in gv100_sor_dp_watermark()
68 nvkm_mask(device, 0x616568 + hoff, 0x0000ffff, h); in gv100_sor_dp_audio_sym()
69 nvkm_mask(device, 0x61656c + hoff, 0x00ffffff, v); in gv100_sor_dp_audio_sym()
80 nvkm_mask(device, 0x616560 + hoff, mask, data); in gv100_sor_dp_audio()
108 nvkm_mask(device, 0x6f0100 + hoff, 0x00010001, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
120 nvkm_mask(device, 0x6f0100 + hoff, 0x00000001, 0x00000001); in gv100_sor_hdmi_infoframe_vsi()
132 nvkm_mask(device, 0x6f0000 + hoff, 0x00000001, 0x00000000); in gv100_sor_hdmi_infoframe_avi()
142 nvkm_mask(device, 0x6f0000 + hoff, 0x00000001, 0x00000001); in gv100_sor_hdmi_infoframe_avi()
156 nvkm_mask(device, 0x6165c0 + hoff, 0x40000000, 0x00000000); in gv100_sor_hdmi_ctrl()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgk110.c58 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gk110_pmu_pgob()
60 nvkm_mask(device, 0x000200, 0x08000000, 0x08000000); in gk110_pmu_pgob()
63 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002); in gk110_pmu_pgob()
64 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001); in gk110_pmu_pgob()
65 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000); in gk110_pmu_pgob()
67 nvkm_mask(device, 0x0206b4, 0x00000000, 0x00000000); in gk110_pmu_pgob()
76 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000); in gk110_pmu_pgob()
77 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001); in gk110_pmu_pgob()
78 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000); in gk110_pmu_pgob()
80 nvkm_mask(device, 0x000200, 0x08000000, 0x00000000); in gk110_pmu_pgob()
[all …]
Dgk104.c64 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gk104_pmu_pgob()
66 nvkm_mask(device, 0x000200, 0x08000000, 0x08000000); in gk104_pmu_pgob()
69 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002); in gk104_pmu_pgob()
70 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001); in gk104_pmu_pgob()
71 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000); in gk104_pmu_pgob()
73 nvkm_mask(device, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000); in gk104_pmu_pgob()
76 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000); in gk104_pmu_pgob()
77 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001); in gk104_pmu_pgob()
78 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000); in gk104_pmu_pgob()
80 nvkm_mask(device, 0x000200, 0x08000000, 0x00000000); in gk104_pmu_pgob()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv05.c78 nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); in nv05_devinit_meminit()
89 nvkm_mask(device, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); in nv05_devinit_meminit()
92 nvkm_mask(device, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); in nv05_devinit_meminit()
94 nvkm_mask(device, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); in nv05_devinit_meminit()
95 nvkm_mask(device, NV04_PFB_CFG1, 0, 1); in nv05_devinit_meminit()
102 nvkm_mask(device, NV04_PFB_BOOT_0, in nv05_devinit_meminit()
111 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
116 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
120 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
Dnv04.c53 nvkm_mask(device, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); in nv04_devinit_meminit()
55 nvkm_mask(device, NV04_PFB_BOOT_0, ~0, in nv04_devinit_meminit()
66 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
69 nvkm_mask(device, NV04_PFB_DEBUG_0, in nv04_devinit_meminit()
76 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
82 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
89 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
93 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
97 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, in nv04_devinit_meminit()
101 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv04_devinit_meminit()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgt215.c313 nvkm_mask(device, 0x020060, 0x00070000, 0x00000000); in gt215_clk_pre()
314 nvkm_mask(device, 0x002504, 0x00000001, 0x00000001); in gt215_clk_pre()
350 nvkm_mask(device, 0x002504, 0x00000001, 0x00000000); in gt215_clk_post()
351 nvkm_mask(device, 0x020060, 0x00070000, 0x00040000); in gt215_clk_post()
358 nvkm_mask(device, src, 0x00000100, 0x00000000); in disable_clk_src()
359 nvkm_mask(device, src, 0x00000001, 0x00000000); in disable_clk_src()
377 nvkm_mask(device, src1, 0x00000101, 0x00000101); in prog_pll()
378 nvkm_mask(device, ctrl, 0x00000008, 0x00000008); in prog_pll()
382 nvkm_mask(device, src0, 0x003f3141, 0x00000101 | info->clk); in prog_pll()
384 nvkm_mask(device, ctrl, 0x00000015, 0x00000015); in prog_pll()
[all …]
Dgm20b.c177 nvkm_mask(device, GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_MASK, in gm20b_pllg_write_mnp()
284 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, in gm20b_pllg_slide()
290 nvkm_mask(device, GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_NEW_MASK, in gm20b_pllg_slide()
298 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, in gm20b_pllg_slide()
309 nvkm_mask(device, GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_MASK, in gm20b_pllg_slide()
313 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, in gm20b_pllg_slide()
326 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); in gm20b_pllg_enable()
333 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_SYNC_MODE, in gm20b_pllg_enable()
338 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), in gm20b_pllg_enable()
350 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); in gm20b_pllg_disable()
[all …]
Dgk20a.c225 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
236 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
247 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
261 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); in gk20a_pllg_enable()
277 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), in gk20a_pllg_enable()
289 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); in gk20a_pllg_disable()
291 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); in gk20a_pllg_disable()
306 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, in gk20a_pllg_program_mnp()
309 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, in gk20a_pllg_program_mnp()
324 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, in gk20a_pllg_program_mnp()
[all …]
Dgk104.c362 nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv); in gk104_clk_prog_0()
371 nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); in gk104_clk_prog_1_0()
382 nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000); in gk104_clk_prog_1_1()
391 nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000); in gk104_clk_prog_2()
392 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000); in gk104_clk_prog_2()
395 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); in gk104_clk_prog_2()
398 nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); in gk104_clk_prog_2()
403 nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); in gk104_clk_prog_2()
406 nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004); in gk104_clk_prog_2()
416 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
Dgk104.c92 nvkm_mask(device, 0x12004c, 0x0000003f, 0x00000002); in gk104_privring_intr()
103 nvkm_mask(device, 0x122318, 0x0003ffff, 0x00001000); in gk104_privring_init()
104 nvkm_mask(device, 0x12231c, 0x0003ffff, 0x00000200); in gk104_privring_init()
105 nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); in gk104_privring_init()
106 nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); in gk104_privring_init()
107 nvkm_mask(device, 0x1223b0, 0x0003ffff, 0x00000fff); in gk104_privring_init()
108 nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000200); in gk104_privring_init()
109 nvkm_mask(device, 0x122358, 0x0003ffff, 0x00002880); in gk104_privring_init()
/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgk110.c342 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); in gk110_gr_init_419eb4()
343 nvkm_mask(device, 0x419eb4, 0x00002000, 0x00002000); in gk110_gr_init_419eb4()
344 nvkm_mask(device, 0x419eb4, 0x00004000, 0x00004000); in gk110_gr_init_419eb4()
345 nvkm_mask(device, 0x419eb4, 0x00008000, 0x00008000); in gk110_gr_init_419eb4()
346 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00000000); in gk110_gr_init_419eb4()
347 nvkm_mask(device, 0x419eb4, 0x00002000, 0x00000000); in gk110_gr_init_419eb4()
348 nvkm_mask(device, 0x419eb4, 0x00004000, 0x00000000); in gk110_gr_init_419eb4()
349 nvkm_mask(device, 0x419eb4, 0x00008000, 0x00000000); in gk110_gr_init_419eb4()
Dctxgv100.c156 nvkm_mask(device, 0x400088, 0x00060000, on ? 0x00060000 : 0x00000000); in gv100_grctx_generate_r400088()
175 nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010); in gv100_grctx_generate_unkn()
176 nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004); in gv100_grctx_generate_unkn()
177 nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000); in gv100_grctx_generate_unkn()
178 nvkm_mask(device, 0x405800, 0x08000000, 0x08000000); in gv100_grctx_generate_unkn()
179 nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); in gv100_grctx_generate_unkn()
187 nvkm_mask(device, 0x40988c, mask, data); in gv100_grctx_unkn88c()
189 nvkm_mask(device, 0x41a88c, mask, data); in gv100_grctx_unkn88c()
191 nvkm_mask(device, 0x408a14, mask, data); in gv100_grctx_unkn88c()
Dctxgk104.c858 nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); in gk104_grctx_generate_r418800()
859 nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000); in gk104_grctx_generate_r418800()
897 nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001); in gk104_grctx_generate_unkn()
898 nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010); in gk104_grctx_generate_unkn()
899 nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004); in gk104_grctx_generate_unkn()
900 nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000); in gk104_grctx_generate_unkn()
901 nvkm_mask(device, 0x405800, 0x08000000, 0x08000000); in gk104_grctx_generate_unkn()
902 nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); in gk104_grctx_generate_unkn()
911 nvkm_mask(device, 0x419f78, 0x00000009, 0x00000000); in gk104_grctx_generate_r419f78()
Dctxgf108.c770 nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001); in gf108_grctx_generate_unkn()
771 nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010); in gf108_grctx_generate_unkn()
772 nvkm_mask(device, 0x419814, 0x00000004, 0x00000004); in gf108_grctx_generate_unkn()
773 nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000); in gf108_grctx_generate_unkn()
774 nvkm_mask(device, 0x405800, 0x08000000, 0x08000000); in gf108_grctx_generate_unkn()
775 nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); in gf108_grctx_generate_unkn()
Dgp100.c46 nvkm_mask(device, 0x418100 + ((znum / 4) * 4), in gp100_gr_zbc_clear_color()
60 nvkm_mask(device, 0x41814c + ((znum / 4) * 4), in gp100_gr_zbc_clear_depth()
83 nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000); in gp100_gr_init_419c9c()
84 nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000); in gp100_gr_init_419c9c()
99 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ in gp100_gr_init_rop_active_fbps()
100 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ in gp100_gr_init_rop_active_fbps()
/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dpadg94.c37 nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000001); in g94_i2c_pad_mode()
40 nvkm_mask(device, 0x00e500 + base, 0x0000c003, 0x0000c001); in g94_i2c_pad_mode()
41 nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000000); in g94_i2c_pad_mode()
44 nvkm_mask(device, 0x00e500 + base, 0x0000c003, 0x00000002); in g94_i2c_pad_mode()
45 nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000000); in g94_i2c_pad_mode()
Dpadgm200.c37 nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000001); in gm200_i2c_pad_mode()
40 nvkm_mask(device, 0x00d970 + base, 0x0000c003, 0x0000c001); in gm200_i2c_pad_mode()
41 nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000000); in gm200_i2c_pad_mode()
44 nvkm_mask(device, 0x00d970 + base, 0x0000c003, 0x00000002); in gm200_i2c_pad_mode()
45 nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000000); in gm200_i2c_pad_mode()
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv40.c119 nvkm_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ in nv40_ram_prog()
123 nvkm_mask(device, 0x00c040, 0x0000c000, 0x00000000); in nv40_ram_prog()
130 nvkm_mask(device, 0x004044, 0xc0771100, ram->ctrl); in nv40_ram_prog()
131 nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl); in nv40_ram_prog()
138 nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl); in nv40_ram_prog()
142 nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl); in nv40_ram_prog()
147 nvkm_mask(device, 0x00c040, 0x0000c000, 0x0000c000); in nv40_ram_prog()
151 nvkm_mask(device, 0x100210, 0x80000000, 0x80000000); in nv40_ram_prog()
/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dgf119.c62 nvkm_mask(device, 0x00d610 + (line * 0x04), 0x000000c0, data); in gf119_fan_pwm_ctrl()
100 nvkm_mask(device, 0x0200d8, 0x1fff, divs); /* keep the high bits */ in gf119_fan_pwm_set()
127 nvkm_mask(device, 0x00e720, 0x00000003, 0x00000002); in gf119_therm_init()
129 nvkm_mask(device, 0x00d79c, 0x000000ff, therm->fan->tach.line); in gf119_therm_init()
131 nvkm_mask(device, 0x00e720, 0x00000001, 0x00000001); in gf119_therm_init()
133 nvkm_mask(device, 0x00e720, 0x00000002, 0x00000000); in gf119_therm_init()

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