| /drivers/dma/ |
| D | xgene-dma.c | 216 struct xgene_dma *pdma; member
272 struct xgene_dma *pdma; member
344 static bool is_pq_enabled(struct xgene_dma *pdma) in is_pq_enabled() argument
348 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW); in is_pq_enabled()
1014 struct xgene_dma *pdma = (struct xgene_dma *)id; in xgene_dma_err_isr() local
1018 val = ioread32(pdma->csr_dma + XGENE_DMA_INT); in xgene_dma_err_isr()
1021 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT); in xgene_dma_err_isr()
1026 dev_err(pdma->dev, in xgene_dma_err_isr()
1036 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE); in xgene_dma_wr_ring_state()
1039 iowrite32(ring->state[i], ring->pdma->csr_ring + in xgene_dma_wr_ring_state()
[all …]
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| D | Makefile | 68 obj-$(CONFIG_SF_PDMA) += sf-pdma/
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| D | Kconfig | 751 source "drivers/dma/sf-pdma/Kconfig"
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| /drivers/dma/sf-pdma/ |
| D | sf-pdma.c | 90 dev_err(chan->pdma->dma_dev.dev, in sf_pdma_prep_dma_memcpy()
257 dev_err(chan->pdma->dma_dev.dev, "NULL desc.\n"); in sf_pdma_xfer_desc()
398 static int sf_pdma_irq_init(struct platform_device *pdev, struct sf_pdma *pdma) in sf_pdma_irq_init() argument
403 for (i = 0; i < pdma->n_chans; i++) { in sf_pdma_irq_init()
404 chan = &pdma->chans[i]; in sf_pdma_irq_init()
448 static void sf_pdma_setup_chans(struct sf_pdma *pdma) in sf_pdma_setup_chans() argument
453 INIT_LIST_HEAD(&pdma->dma_dev.channels); in sf_pdma_setup_chans()
455 for (i = 0; i < pdma->n_chans; i++) { in sf_pdma_setup_chans()
456 chan = &pdma->chans[i]; in sf_pdma_setup_chans()
477 chan->pdma = pdma; in sf_pdma_setup_chans()
[all …]
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| D | sf-pdma.h | 56 #define SF_PDMA_REG_BASE(ch) (pdma->membase + (PDMA_CHAN_OFFSET * (ch)))
95 struct sf_pdma *pdma; member
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| D | Makefile | 1 obj-$(CONFIG_SF_PDMA) += sf-pdma.o
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| /drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| D | nv50.c | 34 struct nvkm_dma **pdma) in nv50_dma_new() argument
36 return nvkm_dma_new_(&nv50_dma, device, type, inst, pdma); in nv50_dma_new()
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| D | gf100.c | 34 struct nvkm_dma **pdma) in gf100_dma_new() argument
36 return nvkm_dma_new_(&gf100_dma, device, type, inst, pdma); in gf100_dma_new()
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| D | gf119.c | 34 struct nvkm_dma **pdma) in gf119_dma_new() argument
36 return nvkm_dma_new_(&gf119_dma, device, type, inst, pdma); in gf119_dma_new()
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| D | nv04.c | 34 struct nvkm_dma **pdma) in nv04_dma_new() argument
36 return nvkm_dma_new_(&nv04_dma, device, type, inst, pdma); in nv04_dma_new()
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| D | gv100.c | 32 struct nvkm_dma **pdma) in gv100_dma_new() argument
34 return nvkm_dma_new_(&gv100_dma, device, type, inst, pdma); in gv100_dma_new()
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| D | base.c | 107 enum nvkm_subdev_type type, int inst, struct nvkm_dma **pdma) in nvkm_dma_new_() argument
111 if (!(dma = *pdma = kzalloc(sizeof(*dma), GFP_KERNEL))) in nvkm_dma_new_()
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| /drivers/net/ethernet/mediatek/ |
| D | mtk_eth_soc.c | 48 .pdma = {
96 .pdma = {
112 .pdma = {
160 .pdma = {
915 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_disable()
916 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_disable()
926 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_enable()
927 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_enable()
2421 reg_map->pdma.irq_status); in mtk_napi_rx()
2428 mtk_r32(eth, reg_map->pdma.irq_status), in mtk_napi_rx()
[all …]
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| D | mtk_eth_soc.h | 1109 } pdma; member
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_ppgtt.c | 88 write_dma_entry(struct drm_i915_gem_object * const pdma, in write_dma_entry() argument
92 u64 * const vaddr = __px_vaddr(pdma); in write_dma_entry()
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