| /drivers/mfd/ |
| D | sm501.c | 116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
[all …]
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| /drivers/gpu/drm/hisilicon/hibmc/ |
| D | hibmc_drm_de.c | 284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
300 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
316 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
323 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
196 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
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| /drivers/media/i2c/ |
| D | ov7251.c | 109 const struct ov7251_pll2_cfg *pll2; member
218 .pll2 = &ov7251_pll2_cfg_19_2_mhz,
226 .pll2 = &ov7251_pll2_cfg_24_mhz,
840 configs->pll2->pre_div); in ov7251_pll_configure()
845 configs->pll2->mult); in ov7251_pll_configure()
850 configs->pll2->div); in ov7251_pll_configure()
855 configs->pll2->sys_div); in ov7251_pll_configure()
860 configs->pll2->adc_div); in ov7251_pll_configure()
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| /drivers/gpu/drm/tegra/ |
| D | sor.c | 367 unsigned int pll2; member
1451 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1461 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1464 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2282 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2284 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2297 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2303 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
[all …]
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| /drivers/clk/mxs/ |
| D | clk-imx28.c | 133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
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| /drivers/clk/sunxi/ |
| D | Makefile | 12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 207 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| D | intel_dpll_mgr.c | 1958 PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2); in bxt_ddi_pll_enable()
2073 hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2074 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
2213 dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff); in bxt_ddi_set_dpll_hw_state()
2245 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2); in bxt_ddi_pll_get_freq()
2339 hw_state->pll2, in bxt_dump_hw_state()
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| D | intel_display.c | 5331 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); in intel_pipe_config_compare()
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| /drivers/clk/qcom/ |
| D | mmcc-msm8960.c | 44 static struct clk_pll pll2 = { variable
103 { .hw = &pll2.clkr.hw },
116 { .hw = &pll2.clkr.hw },
130 { .hw = &pll2.clkr.hw },
2801 [PLL2] = &pll2.clkr,
2977 [PLL2] = &pll2.clkr,
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