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Searched refs:sor (Results 1 – 25 of 31) sorted by relevance

12

/drivers/gpu/drm/tegra/
Dsor.c399 int (*probe)(struct tegra_sor *sor);
400 void (*audio_enable)(struct tegra_sor *sor);
401 void (*audio_disable)(struct tegra_sor *sor);
484 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) in tegra_sor_readl() argument
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
500 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) in tegra_sor_set_parent_clock() argument
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DMakefile21 sor.o \
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dg94.c34 g94_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) in g94_sor_dp_watermark() argument
36 struct nvkm_device *device = sor->disp->engine.subdev.device; in g94_sor_dp_watermark()
37 const u32 loff = nv50_sor_link(sor); in g94_sor_dp_watermark()
43 g94_sor_dp_activesym(struct nvkm_ior *sor, int head, in g94_sor_dp_activesym() argument
46 struct nvkm_device *device = sor->disp->engine.subdev.device; in g94_sor_dp_activesym()
47 const u32 loff = nv50_sor_link(sor); in g94_sor_dp_activesym()
54 g94_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) in g94_sor_dp_audio_sym() argument
56 struct nvkm_device *device = sor->disp->engine.subdev.device; in g94_sor_dp_audio_sym()
57 const u32 soff = nv50_ior_base(sor); in g94_sor_dp_audio_sym()
64 g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in g94_sor_dp_drive() argument
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Dga102.c32 ga102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) in ga102_sor_dp_links() argument
34 struct nvkm_device *device = sor->disp->engine.subdev.device; in ga102_sor_dp_links()
35 const u32 soff = nv50_ior_base(sor); in ga102_sor_dp_links()
36 const u32 loff = nv50_sor_link(sor); in ga102_sor_dp_links()
40 switch (sor->dp.bw) { in ga102_sor_dp_links()
54 dpctrl |= ((1 << sor->dp.nr) - 1) << 16; in ga102_sor_dp_links()
55 if (sor->dp.mst) in ga102_sor_dp_links()
57 if (sor->dp.ef) in ga102_sor_dp_links()
85 ga102_sor_clock(struct nvkm_ior *sor) in ga102_sor_clock() argument
87 struct nvkm_device *device = sor->disp->engine.subdev.device; in ga102_sor_clock()
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Dgm200.c34 gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gm200_sor_dp_drive() argument
36 struct nvkm_device *device = sor->disp->engine.subdev.device; in gm200_sor_dp_drive()
37 const u32 loff = nv50_sor_link(sor); in gm200_sor_dp_drive()
38 const u32 shift = sor->func->dp->lanes[ln] * 8; in gm200_sor_dp_drive()
95 const u32 sor = ior ? ior->id + 1 : 0; in gm200_sor_route_set() local
99 nvkm_mask(device, 0x612308 + moff, 0x0000001f, link << 4 | sor); in gm200_sor_route_set()
104 nvkm_mask(device, 0x612388 + moff, 0x0000001f, link << 4 | sor); in gm200_sor_route_set()
112 int lnk[2], sor[2], m, s; in gm200_sor_route_get() local
118 sor[s] = (data & 0x0000000f); in gm200_sor_route_get()
119 if (!sor[s]) in gm200_sor_route_get()
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Dtu102.c33 tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn, u16 aligned) in tu102_sor_dp_vcpi() argument
35 struct nvkm_device *device = sor->disp->engine.subdev.device; in tu102_sor_dp_vcpi()
43 tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) in tu102_sor_dp_links() argument
45 struct nvkm_device *device = sor->disp->engine.subdev.device; in tu102_sor_dp_links()
46 const u32 soff = nv50_ior_base(sor); in tu102_sor_dp_links()
47 const u32 loff = nv50_sor_link(sor); in tu102_sor_dp_links()
51 clksor |= sor->dp.bw << 18; in tu102_sor_dp_links()
52 dpctrl |= ((1 << sor->dp.nr) - 1) << 16; in tu102_sor_dp_links()
53 if (sor->dp.mst) in tu102_sor_dp_links()
55 if (sor->dp.ef) in tu102_sor_dp_links()
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Dgf119.c85 gf119_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) in gf119_sor_dp_watermark() argument
87 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_watermark()
94 gf119_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) in gf119_sor_dp_audio_sym() argument
96 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_audio_sym()
104 gf119_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) in gf119_sor_dp_audio() argument
106 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_audio()
119 gf119_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn, u16 aligned) in gf119_sor_dp_vcpi() argument
121 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_vcpi()
129 gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gf119_sor_dp_drive() argument
131 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_drive()
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Dgm107.c32 gm107_sor_dp_pattern(struct nvkm_ior *sor, int pattern) in gm107_sor_dp_pattern() argument
34 struct nvkm_device *device = sor->disp->engine.subdev.device; in gm107_sor_dp_pattern()
35 const u32 soff = nv50_ior_base(sor); in gm107_sor_dp_pattern()
49 if (sor->asy.link & 1) in gm107_sor_dp_pattern()
95 .sor = { .cnt = gf119_sor_cnt, .new = gm107_sor_new },
Dnv50.c160 nv50_sor_clock(struct nvkm_ior *sor) in nv50_sor_clock() argument
162 struct nvkm_device *device = sor->disp->engine.subdev.device; in nv50_sor_clock()
163 const int div = sor->asy.link == 3; in nv50_sor_clock()
164 const u32 soff = nv50_ior_base(sor); in nv50_sor_clock()
179 nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu, bool data, bool vsync, bool hsync) in nv50_sor_power() argument
181 struct nvkm_device *device = sor->disp->engine.subdev.device; in nv50_sor_power()
182 const u32 soff = nv50_ior_base(sor); in nv50_sor_power()
198 nv50_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) in nv50_sor_state() argument
200 struct nvkm_device *device = sor->disp->engine.subdev.device; in nv50_sor_state()
201 const u32 coff = sor->id * 8 + (state == &sor->arm) * 4; in nv50_sor_state()
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Dgt215.c68 gt215_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) in gt215_sor_dp_audio() argument
70 struct nvkm_device *device = sor->disp->engine.subdev.device; in gt215_sor_dp_audio()
71 const u32 soff = nv50_ior_base(sor); in gt215_sor_dp_audio()
211 .sor = { .cnt = g94_sor_cnt, .new = gt215_sor_new },
Dgv100.c54 gv100_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) in gv100_sor_dp_watermark() argument
56 struct nvkm_device *device = sor->disp->engine.subdev.device; in gv100_sor_dp_watermark()
63 gv100_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) in gv100_sor_dp_audio_sym() argument
65 struct nvkm_device *device = sor->disp->engine.subdev.device; in gv100_sor_dp_audio_sym()
73 gv100_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) in gv100_sor_dp_audio() argument
75 struct nvkm_device *device = sor->disp->engine.subdev.device; in gv100_sor_dp_audio()
184 gv100_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) in gv100_sor_state() argument
186 struct nvkm_device *device = sor->disp->engine.subdev.device; in gv100_sor_state()
187 const u32 coff = (state == &sor->arm) * 0x8000 + sor->id * 0x20; in gv100_sor_state()
1147 for (i = 0; i < disp->sor.nr; i++) { in gv100_disp_init()
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Dgk110.c42 .sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
Dmcp77.c54 .sor = { .cnt = g94_sor_cnt, .new = mcp77_sor_new },
Dgt200.c91 .sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new },
Dgp100.c67 .sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new },
Dmcp89.c68 .sor = { .cnt = g94_sor_cnt, .new = mcp89_sor_new },
Dpriv.h31 } wndw, head, dac, sor, pior; member
/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
Ddcb.h38 struct sor_conf sor; member
47 struct sor_conf sor; member
52 struct sor_conf sor; member
/drivers/gpu/drm/nouveau/dispnv50/
Dcore827d.c34 .sor = &sor507d,
Dcore917d.c37 .sor = &sor907d,
Dcore907d.c71 .sor = &sor907d,
Dcorec57d.c70 .sor = &sorc37d,
Dcore.h39 } *dac, *pior, *sor; member
/drivers/gpu/drm/nouveau/include/nvkm/engine/
Ddisp.h35 } wndw, head, dac, sor; member
/drivers/gpu/drm/nouveau/
Dnouveau_bios.c1448 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1449 link = entry->lvdsconf.sor.link; in parse_dcb20_entry()
1474 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1504 link = entry->dpconf.sor.link; in parse_dcb20_entry()
1508 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1510 link = entry->tmdsconf.sor.link; in parse_dcb20_entry()

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