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Searched refs:wm (Results 1 – 25 of 61) sorted by relevance

123

/drivers/input/touchscreen/
Dwm97xx-core.c84 int wm97xx_reg_read(struct wm97xx *wm, u16 reg) in wm97xx_reg_read() argument
86 if (wm->ac97) in wm97xx_reg_read()
87 return wm->ac97->bus->ops->read(wm->ac97, reg); in wm97xx_reg_read()
93 void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val) in wm97xx_reg_write() argument
97 wm->dig[(reg - AC97_WM9713_DIG1) >> 1] = val; in wm97xx_reg_write()
101 wm->gpio[(reg - AC97_GPIO_CFG) >> 1] = val; in wm97xx_reg_write()
105 wm->misc = val; in wm97xx_reg_write()
107 if (wm->ac97) in wm97xx_reg_write()
108 wm->ac97->bus->ops->write(wm->ac97, reg, val); in wm97xx_reg_write()
120 int wm97xx_read_aux_adc(struct wm97xx *wm, u16 adcsel) in wm97xx_read_aux_adc() argument
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Dwm9713.c151 static void wm9713_phy_init(struct wm97xx *wm) in wm9713_phy_init() argument
163 dev_info(wm->dev, "setting pen detect pull-up to %d Ohms\n", in wm9713_phy_init()
170 dev_info(wm->dev, "setting 5-wire touchscreen mode."); in wm9713_phy_init()
173 dev_warn(wm->dev, in wm9713_phy_init()
183 dev_info(wm->dev, in wm9713_phy_init()
186 dev_info(wm->dev, in wm9713_phy_init()
193 dev_info(wm->dev, "supplied delay out of range."); in wm9713_phy_init()
195 dev_info(wm->dev, "setting adc sample delay to %d u Secs.", in wm9713_phy_init()
206 wm->misc = wm97xx_reg_read(wm, 0x5a); in wm9713_phy_init()
208 wm97xx_reg_write(wm, AC97_WM9713_DIG1, dig1); in wm9713_phy_init()
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Dwm9712.c151 static void wm9712_phy_init(struct wm97xx *wm) in wm9712_phy_init() argument
160 dev_dbg(wm->dev, "setting pen detect pull-up to %d Ohms\n", in wm9712_phy_init()
167 dev_dbg(wm->dev, "setting 5-wire touchscreen mode.\n"); in wm9712_phy_init()
170 dev_warn(wm->dev, "pressure measurement is not " in wm9712_phy_init()
179 dev_dbg(wm->dev, in wm9712_phy_init()
182 dev_dbg(wm->dev, in wm9712_phy_init()
189 dev_dbg(wm->dev, "supplied delay out of range.\n"); in wm9712_phy_init()
194 dev_dbg(wm->dev, "setting adc sample delay to %d u Secs.\n", in wm9712_phy_init()
202 reg = wm97xx_reg_read(wm, AC97_MISC_AFE); in wm9712_phy_init()
203 wm97xx_reg_write(wm, AC97_MISC_AFE, reg | WM97XX_GPIO_4); in wm9712_phy_init()
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Dwm9705.c133 static void wm9705_phy_init(struct wm97xx *wm) in wm9705_phy_init() argument
141 wm97xx_reg_write(wm, AC97_AUX, 0x8000); in wm9705_phy_init()
142 wm97xx_reg_write(wm, AC97_VIDEO, 0x8000); in wm9705_phy_init()
147 dev_dbg(wm->dev, in wm9705_phy_init()
150 dev_dbg(wm->dev, in wm9705_phy_init()
158 dev_dbg(wm->dev, "supplied delay out of range."); in wm9705_phy_init()
164 dev_dbg(wm->dev, "setting adc sample delay to %d u Secs.", in wm9705_phy_init()
169 dev_dbg(wm->dev, "setting pdd to Vmid/%d", 1 - (pdd & 0x000f)); in wm9705_phy_init()
174 wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); in wm9705_phy_init()
175 wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); in wm9705_phy_init()
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Dmainstone-wm97xx.c100 static void wm97xx_acc_pen_up(struct wm97xx *wm) in wm97xx_acc_pen_up() argument
115 static int wm97xx_acc_pen_down(struct wm97xx *wm) in wm97xx_acc_pen_down() argument
146 dev_dbg(wm->dev, "Raw coordinates: x=%x, y=%x, p=%x\n", in wm97xx_acc_pen_down()
157 input_report_abs(wm->input_dev, ABS_X, x & 0xfff); in wm97xx_acc_pen_down()
158 input_report_abs(wm->input_dev, ABS_Y, y & 0xfff); in wm97xx_acc_pen_down()
159 input_report_abs(wm->input_dev, ABS_PRESSURE, p & 0xfff); in wm97xx_acc_pen_down()
160 input_report_key(wm->input_dev, BTN_TOUCH, (p != 0)); in wm97xx_acc_pen_down()
161 input_sync(wm->input_dev); in wm97xx_acc_pen_down()
168 static int wm97xx_acc_startup(struct wm97xx *wm) in wm97xx_acc_startup() argument
173 if (wm->ac97 == NULL) in wm97xx_acc_startup()
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/drivers/gpu/drm/i915/display/
Di9xx_wm.c232 mutex_lock(&dev_priv->display.wm.wm_mutex); in intel_set_memory_cxsr()
235 dev_priv->display.wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
237 dev_priv->display.wm.g4x.cxsr = enable; in intel_set_memory_cxsr()
238 mutex_unlock(&dev_priv->display.wm.wm_mutex); in intel_set_memory_cxsr()
266 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
546 const struct intel_watermark_params *wm, in intel_calculate_wm() argument
560 entries = DIV_ROUND_UP(entries, wm->cacheline_size) + in intel_calculate_wm()
561 wm->guard_size; in intel_calculate_wm()
568 if (wm_size > wm->max_wm) in intel_calculate_wm()
569 wm_size = wm->max_wm; in intel_calculate_wm()
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Dskl_watermark.c355 const struct skl_plane_wm *wm = in skl_crtc_can_enable_sagv() local
356 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
360 if (!wm->wm[0].enable) in skl_crtc_can_enable_sagv()
364 for (level = i915->display.wm.num_levels - 1; in skl_crtc_can_enable_sagv()
365 !wm->wm[level].enable; --level) in skl_crtc_can_enable_sagv()
377 const struct skl_plane_wm *wm = in skl_crtc_can_enable_sagv() local
378 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
384 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv) in skl_crtc_can_enable_sagv()
400 const struct skl_plane_wm *wm = in tgl_crtc_can_enable_sagv() local
401 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
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Dintel_wm.c47 if (i915->display.funcs.wm->update_wm) in intel_update_watermarks()
48 i915->display.funcs.wm->update_wm(i915); in intel_update_watermarks()
56 if (i915->display.funcs.wm->compute_pipe_wm) in intel_compute_pipe_wm()
57 return i915->display.funcs.wm->compute_pipe_wm(state, crtc); in intel_compute_pipe_wm()
67 if (!i915->display.funcs.wm->compute_intermediate_wm) in intel_compute_intermediate_wm()
70 if (drm_WARN_ON(&i915->drm, !i915->display.funcs.wm->compute_pipe_wm)) in intel_compute_intermediate_wm()
73 return i915->display.funcs.wm->compute_intermediate_wm(state, crtc); in intel_compute_intermediate_wm()
81 if (i915->display.funcs.wm->initial_watermarks) { in intel_initial_watermarks()
82 i915->display.funcs.wm->initial_watermarks(state, crtc); in intel_initial_watermarks()
94 if (i915->display.funcs.wm->atomic_update_watermarks) in intel_atomic_update_watermarks()
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Dintel_display_trace.h189 TP_PROTO(struct intel_crtc *crtc, const struct g4x_wm_values *wm),
190 TP_ARGS(crtc, wm),
216 __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY];
217 __entry->sprite = wm->pipe[crtc->pipe].plane[PLANE_SPRITE0];
218 __entry->cursor = wm->pipe[crtc->pipe].plane[PLANE_CURSOR];
219 __entry->sr_plane = wm->sr.plane;
220 __entry->sr_cursor = wm->sr.cursor;
221 __entry->sr_fbc = wm->sr.fbc;
222 __entry->hpll_plane = wm->hpll.plane;
223 __entry->hpll_cursor = wm->hpll.cursor;
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/drivers/media/platform/qcom/camss/
Dcamss-vfe-gen1.h21 void (*bus_connect_wm_to_rdi)(struct vfe_device *vfe, u8 wm, enum vfe_line_id id);
22 void (*bus_disconnect_wm_from_rdi)(struct vfe_device *vfe, u8 wm, enum vfe_line_id id);
24 void (*bus_reload_wm)(struct vfe_device *vfe, u8 wm);
27 void (*enable_irq_wm_line)(struct vfe_device *vfe, u8 wm, enum vfe_line_id line_id,
36 void (*set_cgc_override)(struct vfe_device *vfe, u8 wm, u8 enable);
47 void (*wm_frame_based)(struct vfe_device *vfe, u8 wm, u8 enable);
48 void (*wm_line_based)(struct vfe_device *vfe, u32 wm, struct v4l2_pix_format_mplane *pix,
50 void (*wm_set_ub_cfg)(struct vfe_device *vfe, u8 wm, u16 offset, u16 depth);
51 void (*wm_set_subsample)(struct vfe_device *vfe, u8 wm);
52 void (*wm_set_framedrop_period)(struct vfe_device *vfe, u8 wm, u8 per);
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Dcamss-vfe-480.c117 static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) in vfe_wm_start() argument
122 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ in vfe_wm_start()
130 vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); in vfe_wm_start()
131 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); in vfe_wm_start()
133 vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); in vfe_wm_start()
135 vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); in vfe_wm_start()
136 writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); in vfe_wm_start()
139 writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); in vfe_wm_start()
140 writel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); in vfe_wm_start()
141 writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); in vfe_wm_start()
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Dcamss-vfe-4-1.c270 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_enable() argument
273 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), in vfe_wm_enable()
276 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), in vfe_wm_enable()
280 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_frame_based() argument
283 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), in vfe_wm_frame_based()
286 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), in vfe_wm_frame_based()
303 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, in vfe_wm_line_based() argument
320 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); in vfe_wm_line_based()
329 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); in vfe_wm_line_based()
332 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); in vfe_wm_line_based()
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Dcamss-vfe-4-8.c304 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_frame_based() argument
307 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), in vfe_wm_frame_based()
310 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), in vfe_wm_frame_based()
369 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, in vfe_wm_line_based() argument
386 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); in vfe_wm_line_based()
395 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); in vfe_wm_line_based()
398 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); in vfe_wm_line_based()
400 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); in vfe_wm_line_based()
404 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) in vfe_wm_set_framedrop_period() argument
409 VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); in vfe_wm_set_framedrop_period()
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Dcamss-vfe-4-7.c321 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_enable() argument
324 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), in vfe_wm_enable()
327 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), in vfe_wm_enable()
331 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_frame_based() argument
334 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), in vfe_wm_frame_based()
337 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), in vfe_wm_frame_based()
396 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, in vfe_wm_line_based() argument
413 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); in vfe_wm_line_based()
422 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); in vfe_wm_line_based()
425 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); in vfe_wm_line_based()
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Dcamss-vfe-170.c222 static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) in vfe_wm_start() argument
244 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); in vfe_wm_start()
247 writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_WIDTH_CFG(wm)); in vfe_wm_start()
250 writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_HEIGHT_CFG(wm)); in vfe_wm_start()
253 writel_relaxed(val, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); // XXX 1 for PLAIN8? in vfe_wm_start()
257 writel_relaxed(val, vfe->base + VFE_BUS_WM_STRIDE(wm)); in vfe_wm_start()
262 writel_relaxed(val, vfe->base + VFE_BUS_WM_CFG(wm)); in vfe_wm_start()
265 static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) in vfe_wm_stop() argument
268 writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm)); in vfe_wm_stop()
271 static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, in vfe_wm_update() argument
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/drivers/video/fbdev/
Di740fb.c220 u32 wm; in i740_calc_fifo() local
225 wm = 0x18120000; in i740_calc_fifo()
227 wm = 0x16110000; in i740_calc_fifo()
229 wm = 0x120E0000; in i740_calc_fifo()
231 wm = 0x100D0000; in i740_calc_fifo()
237 wm = 0x2C1D0000; in i740_calc_fifo()
239 wm = 0x2C180000; in i740_calc_fifo()
241 wm = 0x24160000; in i740_calc_fifo()
243 wm = 0x18120000; in i740_calc_fifo()
245 wm = 0x16110000; in i740_calc_fifo()
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/drivers/gpu/drm/radeon/
Drs690.c274 struct rs690_watermark *wm, in rs690_crtc_bandwidth_compute() argument
286 wm->lb_request_fifo_depth = 4; in rs690_crtc_bandwidth_compute()
306 wm->num_line_pair.full = dfixed_const(2); in rs690_crtc_bandwidth_compute()
308 wm->num_line_pair.full = dfixed_const(1); in rs690_crtc_bandwidth_compute()
313 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); in rs690_crtc_bandwidth_compute()
316 wm->lb_request_fifo_depth = 4; in rs690_crtc_bandwidth_compute()
318 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); in rs690_crtc_bandwidth_compute()
343 wm->consumption_rate.full = dfixed_div(a, consumption_time); in rs690_crtc_bandwidth_compute()
361 wm->active_time.full = dfixed_mul(line_time, b); in rs690_crtc_bandwidth_compute()
362 wm->active_time.full = dfixed_div(wm->active_time, a); in rs690_crtc_bandwidth_compute()
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Drv515.c925 struct rv515_watermark *wm, in rv515_crtc_bandwidth_compute() argument
937 wm->lb_request_fifo_depth = 4; in rv515_crtc_bandwidth_compute()
954 wm->num_line_pair.full = dfixed_const(2); in rv515_crtc_bandwidth_compute()
956 wm->num_line_pair.full = dfixed_const(1); in rv515_crtc_bandwidth_compute()
961 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); in rv515_crtc_bandwidth_compute()
964 wm->lb_request_fifo_depth = 4; in rv515_crtc_bandwidth_compute()
966 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); in rv515_crtc_bandwidth_compute()
991 wm->consumption_rate.full = dfixed_div(a, consumption_time); in rv515_crtc_bandwidth_compute()
1009 wm->active_time.full = dfixed_mul(line_time, b); in rv515_crtc_bandwidth_compute()
1010 wm->active_time.full = dfixed_div(wm->active_time, a); in rv515_crtc_bandwidth_compute()
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Devergreen.c1949 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) in evergreen_dram_bandwidth() argument
1957 yclk.full = dfixed_const(wm->yclk); in evergreen_dram_bandwidth()
1959 dram_channels.full = dfixed_const(wm->dram_channels * 4); in evergreen_dram_bandwidth()
1969 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) in evergreen_dram_bandwidth_for_display() argument
1977 yclk.full = dfixed_const(wm->yclk); in evergreen_dram_bandwidth_for_display()
1979 dram_channels.full = dfixed_const(wm->dram_channels * 4); in evergreen_dram_bandwidth_for_display()
1989 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) in evergreen_data_return_bandwidth() argument
1997 sclk.full = dfixed_const(wm->sclk); in evergreen_data_return_bandwidth()
2009 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) in evergreen_dmif_request_bandwidth() argument
2017 disp_clk.full = dfixed_const(wm->disp_clk); in evergreen_dmif_request_bandwidth()
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Dsi.c2068 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm) in dce6_dram_bandwidth() argument
2076 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth()
2078 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth()
2088 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm) in dce6_dram_bandwidth_for_display() argument
2096 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth_for_display()
2098 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth_for_display()
2108 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm) in dce6_data_return_bandwidth() argument
2116 sclk.full = dfixed_const(wm->sclk); in dce6_data_return_bandwidth()
2128 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm) in dce6_get_dmif_bytes_per_request() argument
2133 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm) in dce6_dmif_request_bandwidth() argument
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/drivers/parport/
Dparport_gsc.h119 const unsigned char wm = (PARPORT_CONTROL_STROBE | in parport_gsc_write_control() local
131 __parport_gsc_frob_control (p, wm, d & wm); in parport_gsc_write_control()
148 const unsigned char wm = (PARPORT_CONTROL_STROBE | in parport_gsc_frob_control() local
165 mask &= wm; in parport_gsc_frob_control()
166 val &= wm; in parport_gsc_frob_control()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c656 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm) in dce_v8_0_dram_bandwidth() argument
664 yclk.full = dfixed_const(wm->yclk); in dce_v8_0_dram_bandwidth()
666 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v8_0_dram_bandwidth()
685 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm) in dce_v8_0_dram_bandwidth_for_display() argument
693 yclk.full = dfixed_const(wm->yclk); in dce_v8_0_dram_bandwidth_for_display()
695 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v8_0_dram_bandwidth_for_display()
714 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm) in dce_v8_0_data_return_bandwidth() argument
722 sclk.full = dfixed_const(wm->sclk); in dce_v8_0_data_return_bandwidth()
743 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm) in dce_v8_0_dmif_request_bandwidth() argument
751 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v8_0_dmif_request_bandwidth()
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Ddce_v6_0.c521 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) in dce_v6_0_dram_bandwidth() argument
529 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth()
531 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth()
550 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) in dce_v6_0_dram_bandwidth_for_display() argument
558 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth_for_display()
560 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth_for_display()
579 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) in dce_v6_0_data_return_bandwidth() argument
587 sclk.full = dfixed_const(wm->sclk); in dce_v6_0_data_return_bandwidth()
608 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) in dce_v6_0_dmif_request_bandwidth() argument
616 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v6_0_dmif_request_bandwidth()
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Ddce_v10_0.c717 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) in dce_v10_0_dram_bandwidth() argument
725 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth()
727 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth()
746 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) in dce_v10_0_dram_bandwidth_for_display() argument
754 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth_for_display()
756 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth_for_display()
775 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) in dce_v10_0_data_return_bandwidth() argument
783 sclk.full = dfixed_const(wm->sclk); in dce_v10_0_data_return_bandwidth()
804 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) in dce_v10_0_dmif_request_bandwidth() argument
812 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v10_0_dmif_request_bandwidth()
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Ddce_v11_0.c749 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) in dce_v11_0_dram_bandwidth() argument
757 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth()
759 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth()
778 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) in dce_v11_0_dram_bandwidth_for_display() argument
786 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth_for_display()
788 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth_for_display()
807 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) in dce_v11_0_data_return_bandwidth() argument
815 sclk.full = dfixed_const(wm->sclk); in dce_v11_0_data_return_bandwidth()
836 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) in dce_v11_0_dmif_request_bandwidth() argument
844 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v11_0_dmif_request_bandwidth()
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