1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * camss-vfe-480.c
4 *
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v480 (SM8250)
6 *
7 * Copyright (C) 2020-2021 Linaro Ltd.
8 * Copyright (C) 2021 Jonathan Marek
9 */
10
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14
15 #include "camss.h"
16 #include "camss-vfe.h"
17
18 /* VFE 2/3 are lite and have a different register layout */
19 #define IS_LITE (vfe->id >= 2 ? 1 : 0)
20
21 #define VFE_HW_VERSION (0x00)
22
23 #define VFE_GLOBAL_RESET_CMD (IS_LITE ? 0x0c : 0x1c)
24 #define GLOBAL_RESET_HW_AND_REG (IS_LITE ? BIT(1) : BIT(0))
25
26 #define VFE_REG_UPDATE_CMD (IS_LITE ? 0x20 : 0x34)
reg_update_rdi(struct vfe_device * vfe,int n)27 static inline int reg_update_rdi(struct vfe_device *vfe, int n)
28 {
29 return IS_LITE ? BIT(n) : BIT(1 + (n));
30 }
31
32 #define REG_UPDATE_RDI reg_update_rdi
33 #define VFE_IRQ_CMD (IS_LITE ? 0x24 : 0x38)
34 #define IRQ_CMD_GLOBAL_CLEAR BIT(0)
35
36 #define VFE_IRQ_MASK(n) ((IS_LITE ? 0x28 : 0x3c) + (n) * 4)
37 #define IRQ_MASK_0_RESET_ACK (IS_LITE ? BIT(17) : BIT(0))
38 #define IRQ_MASK_0_BUS_TOP_IRQ (IS_LITE ? BIT(4) : BIT(7))
39 #define VFE_IRQ_CLEAR(n) ((IS_LITE ? 0x34 : 0x48) + (n) * 4)
40 #define VFE_IRQ_STATUS(n) ((IS_LITE ? 0x40 : 0x54) + (n) * 4)
41
42 #define BUS_REG_BASE (IS_LITE ? 0x1a00 : 0xaa00)
43
44 #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
45 #define WM_CGC_OVERRIDE_ALL (0x3FFFFFF)
46
47 #define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xdc)
48
49 #define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4)
bus_irq_mask_0_rdi_rup(struct vfe_device * vfe,int n)50 static inline int bus_irq_mask_0_rdi_rup(struct vfe_device *vfe, int n)
51 {
52 return IS_LITE ? BIT(n) : BIT(3 + (n));
53 }
54
55 #define BUS_IRQ_MASK_0_RDI_RUP bus_irq_mask_0_rdi_rup
bus_irq_mask_0_comp_done(struct vfe_device * vfe,int n)56 static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n)
57 {
58 return IS_LITE ? BIT(4 + (n)) : BIT(6 + (n));
59 }
60
61 #define BUS_IRQ_MASK_0_COMP_DONE bus_irq_mask_0_comp_done
62 #define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4)
63 #define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4)
64 #define VFE_BUS_IRQ_CLEAR_GLOBAL (BUS_REG_BASE + 0x30)
65
66 #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100)
67 #define WM_CFG_EN (0)
68 #define WM_CFG_MODE (16)
69 #define MODE_QCOM_PLAIN (0)
70 #define MODE_MIPI_RAW (1)
71 #define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100)
72 #define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100)
73 #define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100)
74 #define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
75 #define VFE_BUS_WM_IMAGE_CFG_1(n) (BUS_REG_BASE + 0x210 + (n) * 0x100)
76 #define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100)
77 #define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100)
78 #define VFE_BUS_WM_HEADER_ADDR(n) (BUS_REG_BASE + 0x220 + (n) * 0x100)
79 #define VFE_BUS_WM_HEADER_INCR(n) (BUS_REG_BASE + 0x224 + (n) * 0x100)
80 #define VFE_BUS_WM_HEADER_CFG(n) (BUS_REG_BASE + 0x228 + (n) * 0x100)
81
82 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100)
83 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100)
84 #define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100)
85 #define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100)
86
87 #define VFE_BUS_WM_SYSTEM_CACHE_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100)
88 #define VFE_BUS_WM_BURST_LIMIT(n) (BUS_REG_BASE + 0x264 + (n) * 0x100)
89
90 /* for titan 480, each bus client is hardcoded to a specific path
91 * and each bus client is part of a hardcoded "comp group"
92 */
93 #define RDI_WM(n) ((IS_LITE ? 0 : 23) + (n))
94 #define RDI_COMP_GROUP(n) ((IS_LITE ? 0 : 11) + (n))
95
96 #define MAX_VFE_OUTPUT_LINES 4
97
vfe_hw_version(struct vfe_device * vfe)98 static u32 vfe_hw_version(struct vfe_device *vfe)
99 {
100 u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION);
101
102 u32 gen = (hw_version >> 28) & 0xF;
103 u32 rev = (hw_version >> 16) & 0xFFF;
104 u32 step = hw_version & 0xFFFF;
105
106 dev_dbg(vfe->camss->dev, "VFE HW Version = %u.%u.%u\n", gen, rev, step);
107
108 return hw_version;
109 }
110
vfe_global_reset(struct vfe_device * vfe)111 static void vfe_global_reset(struct vfe_device *vfe)
112 {
113 writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0));
114 writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD);
115 }
116
vfe_wm_start(struct vfe_device * vfe,u8 wm,struct vfe_line * line)117 static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
118 {
119 struct v4l2_pix_format_mplane *pix =
120 &line->video_out.active_fmt.fmt.pix_mp;
121
122 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
123
124 /* no clock gating at bus input */
125 writel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
126
127 writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
128
129 writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height,
130 vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
131 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));
132 writel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH,
133 vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
134 writel_relaxed(pix->plane_fmt[0].bytesperline,
135 vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
136 writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
137
138 /* no dropped frames, one irq per frame */
139 writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
140 writel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
141 writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
142 writel_relaxed(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
143
144 writel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE,
145 vfe->base + VFE_BUS_WM_CFG(wm));
146 }
147
vfe_wm_stop(struct vfe_device * vfe,u8 wm)148 static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
149 {
150 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
151 writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));
152 }
153
vfe_wm_update(struct vfe_device * vfe,u8 wm,u32 addr,struct vfe_line * line)154 static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
155 struct vfe_line *line)
156 {
157 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
158 writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
159 }
160
vfe_reg_update(struct vfe_device * vfe,enum vfe_line_id line_id)161 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
162 {
163 vfe->reg_update |= REG_UPDATE_RDI(vfe, line_id);
164 writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD);
165 }
166
vfe_reg_update_clear(struct vfe_device * vfe,enum vfe_line_id line_id)167 static inline void vfe_reg_update_clear(struct vfe_device *vfe,
168 enum vfe_line_id line_id)
169 {
170 vfe->reg_update &= ~REG_UPDATE_RDI(vfe, line_id);
171 }
172
vfe_enable_irq_common(struct vfe_device * vfe)173 static void vfe_enable_irq_common(struct vfe_device *vfe)
174 {
175 /* enable reset ack IRQ and top BUS status IRQ */
176 writel_relaxed(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ,
177 vfe->base + VFE_IRQ_MASK(0));
178 }
179
vfe_enable_lines_irq(struct vfe_device * vfe)180 static void vfe_enable_lines_irq(struct vfe_device *vfe)
181 {
182 int i;
183 u32 bus_irq_mask = 0;
184
185 for (i = 0; i < MAX_VFE_OUTPUT_LINES; i++) {
186 /* Enable IRQ for newly added lines, but also keep already running lines's IRQ */
187 if (vfe->line[i].output.state == VFE_OUTPUT_RESERVED ||
188 vfe->line[i].output.state == VFE_OUTPUT_ON) {
189 bus_irq_mask |= BUS_IRQ_MASK_0_RDI_RUP(vfe, i)
190 | BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i));
191 }
192 }
193
194 writel_relaxed(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0));
195 }
196
197 static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id);
198 static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm);
199
200 /*
201 * vfe_isr - VFE module interrupt handler
202 * @irq: Interrupt line
203 * @dev: VFE device
204 *
205 * Return IRQ_HANDLED on success
206 */
vfe_isr(int irq,void * dev)207 static irqreturn_t vfe_isr(int irq, void *dev)
208 {
209 struct vfe_device *vfe = dev;
210 u32 status;
211 int i;
212
213 status = readl_relaxed(vfe->base + VFE_IRQ_STATUS(0));
214 writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0));
215 writel_relaxed(IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
216
217 if (status & IRQ_MASK_0_RESET_ACK)
218 vfe_isr_reset_ack(vfe);
219
220 if (status & IRQ_MASK_0_BUS_TOP_IRQ) {
221 u32 status = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(0));
222
223 writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0));
224 writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL);
225
226 /* Loop through all WMs IRQs */
227 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) {
228 if (status & BUS_IRQ_MASK_0_RDI_RUP(vfe, i))
229 vfe_isr_reg_update(vfe, i);
230
231 if (status & BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i)))
232 vfe_isr_wm_done(vfe, i);
233 }
234 }
235
236 return IRQ_HANDLED;
237 }
238
239 /*
240 * vfe_halt - Trigger halt on VFE module and wait to complete
241 * @vfe: VFE device
242 *
243 * Return 0 on success or a negative error code otherwise
244 */
vfe_halt(struct vfe_device * vfe)245 static int vfe_halt(struct vfe_device *vfe)
246 {
247 /* rely on vfe_disable_output() to stop the VFE */
248 return 0;
249 }
250
vfe_get_output(struct vfe_line * line)251 static int vfe_get_output(struct vfe_line *line)
252 {
253 struct vfe_device *vfe = to_vfe(line);
254 struct vfe_output *output;
255 unsigned long flags;
256
257 spin_lock_irqsave(&vfe->output_lock, flags);
258
259 output = &line->output;
260 if (output->state > VFE_OUTPUT_RESERVED) {
261 dev_err(vfe->camss->dev, "Output is running\n");
262 goto error;
263 }
264
265 output->wm_num = 1;
266
267 /* Correspondence between VFE line number and WM number.
268 * line 0 -> RDI 0, line 1 -> RDI1, line 2 -> RDI2, line 3 -> PIX/RDI3
269 * Note this 1:1 mapping will not work for PIX streams.
270 */
271 output->wm_idx[0] = line->id;
272 vfe->wm_output_map[line->id] = line->id;
273
274 output->drop_update_idx = 0;
275
276 spin_unlock_irqrestore(&vfe->output_lock, flags);
277
278 return 0;
279
280 error:
281 spin_unlock_irqrestore(&vfe->output_lock, flags);
282 output->state = VFE_OUTPUT_OFF;
283
284 return -EINVAL;
285 }
286
vfe_enable_output(struct vfe_line * line)287 static int vfe_enable_output(struct vfe_line *line)
288 {
289 struct vfe_device *vfe = to_vfe(line);
290 struct vfe_output *output = &line->output;
291 unsigned long flags;
292 unsigned int i;
293
294 spin_lock_irqsave(&vfe->output_lock, flags);
295
296 vfe_reg_update_clear(vfe, line->id);
297
298 if (output->state > VFE_OUTPUT_RESERVED) {
299 dev_err(vfe->camss->dev, "Output is not in reserved state %d\n",
300 output->state);
301 spin_unlock_irqrestore(&vfe->output_lock, flags);
302 return -EINVAL;
303 }
304
305 WARN_ON(output->gen2.active_num);
306
307 output->state = VFE_OUTPUT_ON;
308
309 output->sequence = 0;
310 output->wait_reg_update = 0;
311 reinit_completion(&output->reg_update);
312
313 vfe_wm_start(vfe, output->wm_idx[0], line);
314
315 for (i = 0; i < 2; i++) {
316 output->buf[i] = vfe_buf_get_pending(output);
317 if (!output->buf[i])
318 break;
319 output->gen2.active_num++;
320 vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line);
321 }
322
323 vfe_reg_update(vfe, line->id);
324
325 spin_unlock_irqrestore(&vfe->output_lock, flags);
326
327 return 0;
328 }
329
vfe_disable_output(struct vfe_line * line)330 static void vfe_disable_output(struct vfe_line *line)
331 {
332 struct vfe_device *vfe = to_vfe(line);
333 struct vfe_output *output = &line->output;
334 unsigned long flags;
335 unsigned int i;
336
337 spin_lock_irqsave(&vfe->output_lock, flags);
338 for (i = 0; i < output->wm_num; i++)
339 vfe_wm_stop(vfe, output->wm_idx[i]);
340 output->gen2.active_num = 0;
341 spin_unlock_irqrestore(&vfe->output_lock, flags);
342
343 vfe_reset(vfe);
344 }
345
346 /*
347 * vfe_enable - Enable streaming on VFE line
348 * @line: VFE line
349 *
350 * Return 0 on success or a negative error code otherwise
351 */
vfe_enable(struct vfe_line * line)352 static int vfe_enable(struct vfe_line *line)
353 {
354 struct vfe_device *vfe = to_vfe(line);
355 int ret;
356
357 mutex_lock(&vfe->stream_lock);
358
359 if (!vfe->stream_count)
360 vfe_enable_irq_common(vfe);
361
362 vfe->stream_count++;
363
364 vfe_enable_lines_irq(vfe);
365
366 mutex_unlock(&vfe->stream_lock);
367
368 ret = vfe_get_output(line);
369 if (ret < 0)
370 goto error_get_output;
371
372 ret = vfe_enable_output(line);
373 if (ret < 0)
374 goto error_enable_output;
375
376 vfe->was_streaming = 1;
377
378 return 0;
379
380 error_enable_output:
381 vfe_put_output(line);
382
383 error_get_output:
384 mutex_lock(&vfe->stream_lock);
385
386 vfe->stream_count--;
387
388 mutex_unlock(&vfe->stream_lock);
389
390 return ret;
391 }
392
393 /*
394 * vfe_disable - Disable streaming on VFE line
395 * @line: VFE line
396 *
397 * Return 0 on success or a negative error code otherwise
398 */
vfe_disable(struct vfe_line * line)399 static int vfe_disable(struct vfe_line *line)
400 {
401 struct vfe_device *vfe = to_vfe(line);
402
403 vfe_disable_output(line);
404
405 vfe_put_output(line);
406
407 mutex_lock(&vfe->stream_lock);
408
409 vfe->stream_count--;
410
411 mutex_unlock(&vfe->stream_lock);
412
413 return 0;
414 }
415
416 /*
417 * vfe_isr_reg_update - Process reg update interrupt
418 * @vfe: VFE Device
419 * @line_id: VFE line
420 */
vfe_isr_reg_update(struct vfe_device * vfe,enum vfe_line_id line_id)421 static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
422 {
423 struct vfe_output *output;
424 unsigned long flags;
425
426 spin_lock_irqsave(&vfe->output_lock, flags);
427 vfe_reg_update_clear(vfe, line_id);
428
429 output = &vfe->line[line_id].output;
430
431 if (output->wait_reg_update) {
432 output->wait_reg_update = 0;
433 complete(&output->reg_update);
434 }
435
436 spin_unlock_irqrestore(&vfe->output_lock, flags);
437 }
438
439 /*
440 * vfe_isr_wm_done - Process write master done interrupt
441 * @vfe: VFE Device
442 * @wm: Write master id
443 */
vfe_isr_wm_done(struct vfe_device * vfe,u8 wm)444 static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm)
445 {
446 struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]];
447 struct camss_buffer *ready_buf;
448 struct vfe_output *output;
449 unsigned long flags;
450 u32 index;
451 u64 ts = ktime_get_ns();
452
453 spin_lock_irqsave(&vfe->output_lock, flags);
454
455 if (vfe->wm_output_map[wm] == VFE_LINE_NONE) {
456 dev_err_ratelimited(vfe->camss->dev,
457 "Received wm done for unmapped index\n");
458 goto out_unlock;
459 }
460 output = &vfe->line[vfe->wm_output_map[wm]].output;
461
462 ready_buf = output->buf[0];
463 if (!ready_buf) {
464 dev_err_ratelimited(vfe->camss->dev,
465 "Missing ready buf %d!\n", output->state);
466 goto out_unlock;
467 }
468
469 ready_buf->vb.vb2_buf.timestamp = ts;
470 ready_buf->vb.sequence = output->sequence++;
471
472 index = 0;
473 output->buf[0] = output->buf[1];
474 if (output->buf[0])
475 index = 1;
476
477 output->buf[index] = vfe_buf_get_pending(output);
478
479 if (output->buf[index])
480 vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line);
481 else
482 output->gen2.active_num--;
483
484 spin_unlock_irqrestore(&vfe->output_lock, flags);
485
486 vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
487
488 return;
489
490 out_unlock:
491 spin_unlock_irqrestore(&vfe->output_lock, flags);
492 }
493
494 /*
495 * vfe_pm_domain_off - Disable power domains specific to this VFE.
496 * @vfe: VFE Device
497 */
vfe_pm_domain_off(struct vfe_device * vfe)498 static void vfe_pm_domain_off(struct vfe_device *vfe)
499 {
500 struct camss *camss = vfe->camss;
501
502 if (vfe->id >= camss->vfe_num)
503 return;
504
505 device_link_del(camss->genpd_link[vfe->id]);
506 }
507
508 /*
509 * vfe_pm_domain_on - Enable power domains specific to this VFE.
510 * @vfe: VFE Device
511 */
vfe_pm_domain_on(struct vfe_device * vfe)512 static int vfe_pm_domain_on(struct vfe_device *vfe)
513 {
514 struct camss *camss = vfe->camss;
515 enum vfe_line_id id = vfe->id;
516
517 if (id >= camss->vfe_num)
518 return 0;
519
520 camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id],
521 DL_FLAG_STATELESS |
522 DL_FLAG_PM_RUNTIME |
523 DL_FLAG_RPM_ACTIVE);
524 if (!camss->genpd_link[id])
525 return -EINVAL;
526
527 return 0;
528 }
529
530 /*
531 * vfe_queue_buffer - Add empty buffer
532 * @vid: Video device structure
533 * @buf: Buffer to be enqueued
534 *
535 * Add an empty buffer - depending on the current number of buffers it will be
536 * put in pending buffer queue or directly given to the hardware to be filled.
537 *
538 * Return 0 on success or a negative error code otherwise
539 */
vfe_queue_buffer(struct camss_video * vid,struct camss_buffer * buf)540 static int vfe_queue_buffer(struct camss_video *vid,
541 struct camss_buffer *buf)
542 {
543 struct vfe_line *line = container_of(vid, struct vfe_line, video_out);
544 struct vfe_device *vfe = to_vfe(line);
545 struct vfe_output *output;
546 unsigned long flags;
547
548 output = &line->output;
549
550 spin_lock_irqsave(&vfe->output_lock, flags);
551
552 if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) {
553 output->buf[output->gen2.active_num++] = buf;
554 vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line);
555 } else {
556 vfe_buf_add_pending(output, buf);
557 }
558
559 spin_unlock_irqrestore(&vfe->output_lock, flags);
560
561 return 0;
562 }
563
564 static const struct camss_video_ops vfe_video_ops_480 = {
565 .queue_buffer = vfe_queue_buffer,
566 .flush_buffers = vfe_flush_buffers,
567 };
568
vfe_subdev_init(struct device * dev,struct vfe_device * vfe)569 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
570 {
571 vfe->video_ops = vfe_video_ops_480;
572 vfe->line_num = MAX_VFE_OUTPUT_LINES;
573 }
574
575 const struct vfe_hw_ops vfe_ops_480 = {
576 .global_reset = vfe_global_reset,
577 .hw_version = vfe_hw_version,
578 .isr = vfe_isr,
579 .pm_domain_off = vfe_pm_domain_off,
580 .pm_domain_on = vfe_pm_domain_on,
581 .subdev_init = vfe_subdev_init,
582 .vfe_disable = vfe_disable,
583 .vfe_enable = vfe_enable,
584 .vfe_halt = vfe_halt,
585 };
586