1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Record and handle CPU attributes.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7 #include <asm/arch_timer.h>
8 #include <asm/cache.h>
9 #include <asm/cpu.h>
10 #include <asm/cputype.h>
11 #include <asm/cpufeature.h>
12 #include <asm/fpsimd.h>
13
14 #include <linux/bitops.h>
15 #include <linux/bug.h>
16 #include <linux/compat.h>
17 #include <linux/elf.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/personality.h>
21 #include <linux/preempt.h>
22 #include <linux/printk.h>
23 #include <linux/seq_file.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/delay.h>
27
28 #include <trace/hooks/cpuinfo.h>
29
30 /*
31 * In case the boot CPU is hotpluggable, we record its initial state and
32 * current state separately. Certain system registers may contain different
33 * values depending on configuration at or after reset.
34 */
35 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
36 static struct cpuinfo_arm64 boot_cpu_data;
37
icache_policy_str(int l1ip)38 static inline const char *icache_policy_str(int l1ip)
39 {
40 switch (l1ip) {
41 case CTR_EL0_L1Ip_VPIPT:
42 return "VPIPT";
43 case CTR_EL0_L1Ip_VIPT:
44 return "VIPT";
45 case CTR_EL0_L1Ip_PIPT:
46 return "PIPT";
47 default:
48 return "RESERVED/UNKNOWN";
49 }
50 }
51
52 unsigned long __icache_flags;
53
54 static const char *const hwcap_str[] = {
55 [KERNEL_HWCAP_FP] = "fp",
56 [KERNEL_HWCAP_ASIMD] = "asimd",
57 [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
58 [KERNEL_HWCAP_AES] = "aes",
59 [KERNEL_HWCAP_PMULL] = "pmull",
60 [KERNEL_HWCAP_SHA1] = "sha1",
61 [KERNEL_HWCAP_SHA2] = "sha2",
62 [KERNEL_HWCAP_CRC32] = "crc32",
63 [KERNEL_HWCAP_ATOMICS] = "atomics",
64 [KERNEL_HWCAP_FPHP] = "fphp",
65 [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
66 [KERNEL_HWCAP_CPUID] = "cpuid",
67 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
68 [KERNEL_HWCAP_JSCVT] = "jscvt",
69 [KERNEL_HWCAP_FCMA] = "fcma",
70 [KERNEL_HWCAP_LRCPC] = "lrcpc",
71 [KERNEL_HWCAP_DCPOP] = "dcpop",
72 [KERNEL_HWCAP_SHA3] = "sha3",
73 [KERNEL_HWCAP_SM3] = "sm3",
74 [KERNEL_HWCAP_SM4] = "sm4",
75 [KERNEL_HWCAP_ASIMDDP] = "asimddp",
76 [KERNEL_HWCAP_SHA512] = "sha512",
77 [KERNEL_HWCAP_SVE] = "sve",
78 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
79 [KERNEL_HWCAP_DIT] = "dit",
80 [KERNEL_HWCAP_USCAT] = "uscat",
81 [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
82 [KERNEL_HWCAP_FLAGM] = "flagm",
83 [KERNEL_HWCAP_SSBS] = "ssbs",
84 [KERNEL_HWCAP_SB] = "sb",
85 [KERNEL_HWCAP_PACA] = "paca",
86 [KERNEL_HWCAP_PACG] = "pacg",
87 [KERNEL_HWCAP_DCPODP] = "dcpodp",
88 [KERNEL_HWCAP_SVE2] = "sve2",
89 [KERNEL_HWCAP_SVEAES] = "sveaes",
90 [KERNEL_HWCAP_SVEPMULL] = "svepmull",
91 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
92 [KERNEL_HWCAP_SVESHA3] = "svesha3",
93 [KERNEL_HWCAP_SVESM4] = "svesm4",
94 [KERNEL_HWCAP_FLAGM2] = "flagm2",
95 [KERNEL_HWCAP_FRINT] = "frint",
96 [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
97 [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
98 [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
99 [KERNEL_HWCAP_SVEBF16] = "svebf16",
100 [KERNEL_HWCAP_I8MM] = "i8mm",
101 [KERNEL_HWCAP_BF16] = "bf16",
102 [KERNEL_HWCAP_DGH] = "dgh",
103 [KERNEL_HWCAP_RNG] = "rng",
104 [KERNEL_HWCAP_BTI] = "bti",
105 [KERNEL_HWCAP_MTE] = "mte",
106 [KERNEL_HWCAP_ECV] = "ecv",
107 [KERNEL_HWCAP_AFP] = "afp",
108 [KERNEL_HWCAP_RPRES] = "rpres",
109 [KERNEL_HWCAP_MTE3] = "mte3",
110 [KERNEL_HWCAP_SME] = "sme",
111 [KERNEL_HWCAP_SME_I16I64] = "smei16i64",
112 [KERNEL_HWCAP_SME_F64F64] = "smef64f64",
113 [KERNEL_HWCAP_SME_I8I32] = "smei8i32",
114 [KERNEL_HWCAP_SME_F16F32] = "smef16f32",
115 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32",
116 [KERNEL_HWCAP_SME_F32F32] = "smef32f32",
117 [KERNEL_HWCAP_SME_FA64] = "smefa64",
118 [KERNEL_HWCAP_WFXT] = "wfxt",
119 [KERNEL_HWCAP_EBF16] = "ebf16",
120 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
121 [KERNEL_HWCAP_CSSC] = "cssc",
122 [KERNEL_HWCAP_RPRFM] = "rprfm",
123 [KERNEL_HWCAP_SVE2P1] = "sve2p1",
124 [KERNEL_HWCAP_SME2] = "sme2",
125 [KERNEL_HWCAP_SME2P1] = "sme2p1",
126 [KERNEL_HWCAP_SME_I16I32] = "smei16i32",
127 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32",
128 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16",
129 [KERNEL_HWCAP_SME_F16F16] = "smef16f16",
130 [KERNEL_HWCAP_MOPS] = "mops",
131 [KERNEL_HWCAP_HBC] = "hbc",
132 };
133
134 #ifdef CONFIG_COMPAT
135 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
136 static const char *const compat_hwcap_str[] = {
137 [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
138 [COMPAT_KERNEL_HWCAP(HALF)] = "half",
139 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
140 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
141 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
142 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
143 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
144 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
145 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
146 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
147 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
148 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
149 [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
150 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
151 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
152 [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
153 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
154 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
155 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
156 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
157 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
158 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
159 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp",
160 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
161 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
162 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
163 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",
164 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm",
165 };
166
167 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
168 static const char *const compat_hwcap2_str[] = {
169 [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
170 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
171 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
172 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
173 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
174 [COMPAT_KERNEL_HWCAP2(SB)] = "sb",
175 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs",
176 };
177 #endif /* CONFIG_COMPAT */
178
c_show(struct seq_file * m,void * v)179 static int c_show(struct seq_file *m, void *v)
180 {
181 int i, j;
182 bool compat = personality(current->personality) == PER_LINUX32;
183
184 for_each_online_cpu(i) {
185 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
186 u32 midr = cpuinfo->reg_midr;
187
188 /*
189 * glibc reads /proc/cpuinfo to determine the number of
190 * online processors, looking for lines beginning with
191 * "processor". Give glibc what it expects.
192 */
193 seq_printf(m, "processor\t: %d\n", i);
194 if (compat)
195 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
196 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
197
198 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
199 loops_per_jiffy / (500000UL/HZ),
200 loops_per_jiffy / (5000UL/HZ) % 100);
201
202 /*
203 * Dump out the common processor features in a single line.
204 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
205 * rather than attempting to parse this, but there's a body of
206 * software which does already (at least for 32-bit).
207 */
208 seq_puts(m, "Features\t:");
209 if (compat) {
210 #ifdef CONFIG_COMPAT
211 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
212 if (compat_elf_hwcap & (1 << j)) {
213 /*
214 * Warn once if any feature should not
215 * have been present on arm64 platform.
216 */
217 if (WARN_ON_ONCE(!compat_hwcap_str[j]))
218 continue;
219
220 seq_printf(m, " %s", compat_hwcap_str[j]);
221 }
222 }
223
224 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
225 if (compat_elf_hwcap2 & (1 << j))
226 seq_printf(m, " %s", compat_hwcap2_str[j]);
227 #endif /* CONFIG_COMPAT */
228 } else {
229 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
230 if (cpu_have_feature(j))
231 seq_printf(m, " %s", hwcap_str[j]);
232 }
233 seq_puts(m, "\n");
234
235 seq_printf(m, "CPU implementer\t: 0x%02x\n",
236 MIDR_IMPLEMENTOR(midr));
237 seq_printf(m, "CPU architecture: 8\n");
238 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
239 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
240 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
241 }
242
243 trace_android_rvh_cpuinfo_c_show(m);
244
245 return 0;
246 }
247
c_start(struct seq_file * m,loff_t * pos)248 static void *c_start(struct seq_file *m, loff_t *pos)
249 {
250 return *pos < 1 ? (void *)1 : NULL;
251 }
252
c_next(struct seq_file * m,void * v,loff_t * pos)253 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
254 {
255 ++*pos;
256 return NULL;
257 }
258
c_stop(struct seq_file * m,void * v)259 static void c_stop(struct seq_file *m, void *v)
260 {
261 }
262
263 const struct seq_operations cpuinfo_op = {
264 .start = c_start,
265 .next = c_next,
266 .stop = c_stop,
267 .show = c_show
268 };
269
270
271 static struct kobj_type cpuregs_kobj_type = {
272 .sysfs_ops = &kobj_sysfs_ops,
273 };
274
275 /*
276 * The ARM ARM uses the phrase "32-bit register" to describe a register
277 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
278 * no statement is made as to whether the upper 32 bits will or will not
279 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
280 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
281 *
282 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
283 * registers, we expose them both as 64 bit values to cater for possible
284 * future expansion without an ABI break.
285 */
286 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
287 #define CPUREGS_ATTR_RO(_name, _field) \
288 static ssize_t _name##_show(struct kobject *kobj, \
289 struct kobj_attribute *attr, char *buf) \
290 { \
291 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
292 \
293 if (info->reg_midr) \
294 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
295 else \
296 return 0; \
297 } \
298 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
299
300 CPUREGS_ATTR_RO(midr_el1, midr);
301 CPUREGS_ATTR_RO(revidr_el1, revidr);
302 CPUREGS_ATTR_RO(smidr_el1, smidr);
303
304 static struct attribute *cpuregs_id_attrs[] = {
305 &cpuregs_attr_midr_el1.attr,
306 &cpuregs_attr_revidr_el1.attr,
307 NULL
308 };
309
310 static const struct attribute_group cpuregs_attr_group = {
311 .attrs = cpuregs_id_attrs,
312 .name = "identification"
313 };
314
315 static struct attribute *sme_cpuregs_id_attrs[] = {
316 &cpuregs_attr_smidr_el1.attr,
317 NULL
318 };
319
320 static const struct attribute_group sme_cpuregs_attr_group = {
321 .attrs = sme_cpuregs_id_attrs,
322 .name = "identification"
323 };
324
cpuid_cpu_online(unsigned int cpu)325 static int cpuid_cpu_online(unsigned int cpu)
326 {
327 int rc;
328 struct device *dev;
329 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
330
331 dev = get_cpu_device(cpu);
332 if (!dev) {
333 rc = -ENODEV;
334 goto out;
335 }
336 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
337 if (rc)
338 goto out;
339 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
340 if (rc)
341 kobject_del(&info->kobj);
342 if (system_supports_sme())
343 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);
344 out:
345 return rc;
346 }
347
cpuid_cpu_offline(unsigned int cpu)348 static int cpuid_cpu_offline(unsigned int cpu)
349 {
350 struct device *dev;
351 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
352
353 dev = get_cpu_device(cpu);
354 if (!dev)
355 return -ENODEV;
356 if (info->kobj.parent) {
357 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
358 kobject_del(&info->kobj);
359 }
360
361 return 0;
362 }
363
cpuinfo_regs_init(void)364 static int __init cpuinfo_regs_init(void)
365 {
366 int cpu, ret;
367
368 for_each_possible_cpu(cpu) {
369 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
370
371 kobject_init(&info->kobj, &cpuregs_kobj_type);
372 }
373
374 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
375 cpuid_cpu_online, cpuid_cpu_offline);
376 if (ret < 0) {
377 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
378 return ret;
379 }
380 return 0;
381 }
382 device_initcall(cpuinfo_regs_init);
383
cpuinfo_detect_icache_policy(struct cpuinfo_arm64 * info)384 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
385 {
386 unsigned int cpu = smp_processor_id();
387 u32 l1ip = CTR_L1IP(info->reg_ctr);
388
389 switch (l1ip) {
390 case CTR_EL0_L1Ip_PIPT:
391 break;
392 case CTR_EL0_L1Ip_VPIPT:
393 set_bit(ICACHEF_VPIPT, &__icache_flags);
394 break;
395 case CTR_EL0_L1Ip_VIPT:
396 default:
397 /* Assume aliasing */
398 set_bit(ICACHEF_ALIASING, &__icache_flags);
399 break;
400 }
401
402 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
403 }
404
__cpuinfo_store_cpu_32bit(struct cpuinfo_32bit * info)405 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
406 {
407 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
408 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
409 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
410 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
411 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
412 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
413 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
414 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
415 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
416 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
417 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
418 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
419 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
420 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
421 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
422 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
423 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
424 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
425
426 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
427 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
428 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
429 }
430
__cpuinfo_store_cpu(struct cpuinfo_arm64 * info)431 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
432 {
433 info->reg_cntfrq = arch_timer_get_cntfrq();
434 /*
435 * Use the effective value of the CTR_EL0 than the raw value
436 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
437 * with the CLIDR_EL1 fields to avoid triggering false warnings
438 * when there is a mismatch across the CPUs. Keep track of the
439 * effective value of the CTR_EL0 in our internal records for
440 * accurate sanity check and feature enablement.
441 */
442 info->reg_ctr = read_cpuid_effective_cachetype();
443 info->reg_dczid = read_cpuid(DCZID_EL0);
444 info->reg_midr = read_cpuid_id();
445 info->reg_revidr = read_cpuid(REVIDR_EL1);
446
447 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
448 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
449 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
450 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
451 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
452 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
453 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
454 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
455 info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1);
456 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
457 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
458 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
459 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
460
461 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
462 info->reg_gmid = read_cpuid(GMID_EL1);
463
464 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
465 __cpuinfo_store_cpu_32bit(&info->aarch32);
466
467 cpuinfo_detect_icache_policy(info);
468 }
469
cpuinfo_store_cpu(void)470 void cpuinfo_store_cpu(void)
471 {
472 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
473 __cpuinfo_store_cpu(info);
474 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
475 }
476
cpuinfo_store_boot_cpu(void)477 void __init cpuinfo_store_boot_cpu(void)
478 {
479 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
480 __cpuinfo_store_cpu(info);
481
482 boot_cpu_data = *info;
483 init_cpu_features(&boot_cpu_data);
484 }
485