1 /*
2 * arch/arm64/kernel/topology.c
3 *
4 * Copyright (C) 2011,2013,2014 Linaro Limited.
5 *
6 * Based on the arm32 version written by Vincent Guittot in turn based on
7 * arch/sh/kernel/topology.c
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14 #include <linux/acpi.h>
15 #include <linux/arch_topology.h>
16 #include <linux/cacheinfo.h>
17 #include <linux/cpufreq.h>
18 #include <linux/init.h>
19 #include <linux/percpu.h>
20
21 #include <asm/cpu.h>
22 #include <asm/cputype.h>
23 #include <asm/topology.h>
24
25 #include <trace/hooks/topology.h>
26
27 #ifdef CONFIG_ACPI
acpi_cpu_is_threaded(int cpu)28 static bool __init acpi_cpu_is_threaded(int cpu)
29 {
30 int is_threaded = acpi_pptt_cpu_is_thread(cpu);
31
32 /*
33 * if the PPTT doesn't have thread information, assume a homogeneous
34 * machine and return the current CPU's thread state.
35 */
36 if (is_threaded < 0)
37 is_threaded = read_cpuid_mpidr() & MPIDR_MT_BITMASK;
38
39 return !!is_threaded;
40 }
41
42 /*
43 * Propagate the topology information of the processor_topology_node tree to the
44 * cpu_topology array.
45 */
parse_acpi_topology(void)46 int __init parse_acpi_topology(void)
47 {
48 int cpu, topology_id;
49
50 if (acpi_disabled)
51 return 0;
52
53 for_each_possible_cpu(cpu) {
54 topology_id = find_acpi_cpu_topology(cpu, 0);
55 if (topology_id < 0)
56 return topology_id;
57
58 if (acpi_cpu_is_threaded(cpu)) {
59 cpu_topology[cpu].thread_id = topology_id;
60 topology_id = find_acpi_cpu_topology(cpu, 1);
61 cpu_topology[cpu].core_id = topology_id;
62 } else {
63 cpu_topology[cpu].thread_id = -1;
64 cpu_topology[cpu].core_id = topology_id;
65 }
66 topology_id = find_acpi_cpu_topology_cluster(cpu);
67 cpu_topology[cpu].cluster_id = topology_id;
68 topology_id = find_acpi_cpu_topology_package(cpu);
69 cpu_topology[cpu].package_id = topology_id;
70 }
71
72 return 0;
73 }
74 #endif
75
76 #ifdef CONFIG_ARM64_AMU_EXTN
77 #define read_corecnt() read_sysreg_s(SYS_AMEVCNTR0_CORE_EL0)
78 #define read_constcnt() read_sysreg_s(SYS_AMEVCNTR0_CONST_EL0)
79 #else
80 #define read_corecnt() (0UL)
81 #define read_constcnt() (0UL)
82 #endif
83
84 #undef pr_fmt
85 #define pr_fmt(fmt) "AMU: " fmt
86
87 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale);
88 static DEFINE_PER_CPU(u64, arch_const_cycles_prev);
89 static DEFINE_PER_CPU(u64, arch_core_cycles_prev);
90 static cpumask_var_t amu_fie_cpus;
91
update_freq_counters_refs(void)92 void update_freq_counters_refs(void)
93 {
94 this_cpu_write(arch_core_cycles_prev, read_corecnt());
95 this_cpu_write(arch_const_cycles_prev, read_constcnt());
96 }
97
freq_counters_valid(int cpu)98 static inline bool freq_counters_valid(int cpu)
99 {
100 if ((cpu >= nr_cpu_ids) || !cpumask_test_cpu(cpu, cpu_present_mask))
101 return false;
102
103 if (!cpu_has_amu_feat(cpu)) {
104 pr_debug("CPU%d: counters are not supported.\n", cpu);
105 return false;
106 }
107
108 if (unlikely(!per_cpu(arch_const_cycles_prev, cpu) ||
109 !per_cpu(arch_core_cycles_prev, cpu))) {
110 pr_debug("CPU%d: cycle counters are not enabled.\n", cpu);
111 return false;
112 }
113
114 return true;
115 }
116
freq_inv_set_max_ratio(int cpu,u64 max_rate,u64 ref_rate)117 static int freq_inv_set_max_ratio(int cpu, u64 max_rate, u64 ref_rate)
118 {
119 u64 ratio;
120
121 if (unlikely(!max_rate || !ref_rate)) {
122 pr_debug("CPU%d: invalid maximum or reference frequency.\n",
123 cpu);
124 return -EINVAL;
125 }
126
127 /*
128 * Pre-compute the fixed ratio between the frequency of the constant
129 * reference counter and the maximum frequency of the CPU.
130 *
131 * ref_rate
132 * arch_max_freq_scale = ---------- * SCHED_CAPACITY_SCALE²
133 * max_rate
134 *
135 * We use a factor of 2 * SCHED_CAPACITY_SHIFT -> SCHED_CAPACITY_SCALE²
136 * in order to ensure a good resolution for arch_max_freq_scale for
137 * very low reference frequencies (down to the KHz range which should
138 * be unlikely).
139 */
140 ratio = ref_rate << (2 * SCHED_CAPACITY_SHIFT);
141 ratio = div64_u64(ratio, max_rate);
142 if (!ratio) {
143 WARN_ONCE(1, "Reference frequency too low.\n");
144 return -EINVAL;
145 }
146
147 per_cpu(arch_max_freq_scale, cpu) = (unsigned long)ratio;
148
149 return 0;
150 }
151
amu_scale_freq_tick(void)152 static void amu_scale_freq_tick(void)
153 {
154 u64 prev_core_cnt, prev_const_cnt;
155 u64 core_cnt, const_cnt, scale;
156 bool use_amu_fie = true;
157
158 trace_android_vh_use_amu_fie(&use_amu_fie);
159 if(!use_amu_fie)
160 return;
161
162 prev_const_cnt = this_cpu_read(arch_const_cycles_prev);
163 prev_core_cnt = this_cpu_read(arch_core_cycles_prev);
164
165 update_freq_counters_refs();
166
167 const_cnt = this_cpu_read(arch_const_cycles_prev);
168 core_cnt = this_cpu_read(arch_core_cycles_prev);
169
170 if (unlikely(core_cnt <= prev_core_cnt ||
171 const_cnt <= prev_const_cnt))
172 return;
173
174 /*
175 * /\core arch_max_freq_scale
176 * scale = ------- * --------------------
177 * /\const SCHED_CAPACITY_SCALE
178 *
179 * See validate_cpu_freq_invariance_counters() for details on
180 * arch_max_freq_scale and the use of SCHED_CAPACITY_SHIFT.
181 */
182 scale = core_cnt - prev_core_cnt;
183 scale *= this_cpu_read(arch_max_freq_scale);
184 scale = div64_u64(scale >> SCHED_CAPACITY_SHIFT,
185 const_cnt - prev_const_cnt);
186
187 scale = min_t(unsigned long, scale, SCHED_CAPACITY_SCALE);
188 this_cpu_write(arch_freq_scale, (unsigned long)scale);
189 }
190
191 static struct scale_freq_data amu_sfd = {
192 .source = SCALE_FREQ_SOURCE_ARCH,
193 .set_freq_scale = amu_scale_freq_tick,
194 };
195
amu_fie_setup(const struct cpumask * cpus)196 static void amu_fie_setup(const struct cpumask *cpus)
197 {
198 int cpu;
199
200 /* We are already set since the last insmod of cpufreq driver */
201 if (unlikely(cpumask_subset(cpus, amu_fie_cpus)))
202 return;
203
204 for_each_cpu(cpu, cpus) {
205 if (!freq_counters_valid(cpu) ||
206 freq_inv_set_max_ratio(cpu,
207 cpufreq_get_hw_max_freq(cpu) * 1000ULL,
208 arch_timer_get_rate()))
209 return;
210 }
211
212 cpumask_or(amu_fie_cpus, amu_fie_cpus, cpus);
213
214 topology_set_scale_freq_source(&amu_sfd, amu_fie_cpus);
215
216 pr_debug("CPUs[%*pbl]: counters will be used for FIE.",
217 cpumask_pr_args(cpus));
218 }
219
init_amu_fie_callback(struct notifier_block * nb,unsigned long val,void * data)220 static int init_amu_fie_callback(struct notifier_block *nb, unsigned long val,
221 void *data)
222 {
223 struct cpufreq_policy *policy = data;
224
225 if (val == CPUFREQ_CREATE_POLICY)
226 amu_fie_setup(policy->related_cpus);
227
228 /*
229 * We don't need to handle CPUFREQ_REMOVE_POLICY event as the AMU
230 * counters don't have any dependency on cpufreq driver once we have
231 * initialized AMU support and enabled invariance. The AMU counters will
232 * keep on working just fine in the absence of the cpufreq driver, and
233 * for the CPUs for which there are no counters available, the last set
234 * value of arch_freq_scale will remain valid as that is the frequency
235 * those CPUs are running at.
236 */
237
238 return 0;
239 }
240
241 static struct notifier_block init_amu_fie_notifier = {
242 .notifier_call = init_amu_fie_callback,
243 };
244
init_amu_fie(void)245 static int __init init_amu_fie(void)
246 {
247 int ret;
248
249 if (!zalloc_cpumask_var(&amu_fie_cpus, GFP_KERNEL))
250 return -ENOMEM;
251
252 ret = cpufreq_register_notifier(&init_amu_fie_notifier,
253 CPUFREQ_POLICY_NOTIFIER);
254 if (ret)
255 free_cpumask_var(amu_fie_cpus);
256
257 return ret;
258 }
259 core_initcall(init_amu_fie);
260
261 #ifdef CONFIG_ACPI_CPPC_LIB
262 #include <acpi/cppc_acpi.h>
263
cpu_read_corecnt(void * val)264 static void cpu_read_corecnt(void *val)
265 {
266 /*
267 * A value of 0 can be returned if the current CPU does not support AMUs
268 * or if the counter is disabled for this CPU. A return value of 0 at
269 * counter read is properly handled as an error case by the users of the
270 * counter.
271 */
272 *(u64 *)val = read_corecnt();
273 }
274
cpu_read_constcnt(void * val)275 static void cpu_read_constcnt(void *val)
276 {
277 /*
278 * Return 0 if the current CPU is affected by erratum 2457168. A value
279 * of 0 is also returned if the current CPU does not support AMUs or if
280 * the counter is disabled. A return value of 0 at counter read is
281 * properly handled as an error case by the users of the counter.
282 */
283 *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ?
284 0UL : read_constcnt();
285 }
286
287 static inline
counters_read_on_cpu(int cpu,smp_call_func_t func,u64 * val)288 int counters_read_on_cpu(int cpu, smp_call_func_t func, u64 *val)
289 {
290 /*
291 * Abort call on counterless CPU or when interrupts are
292 * disabled - can lead to deadlock in smp sync call.
293 */
294 if (!cpu_has_amu_feat(cpu))
295 return -EOPNOTSUPP;
296
297 if (WARN_ON_ONCE(irqs_disabled()))
298 return -EPERM;
299
300 smp_call_function_single(cpu, func, val, 1);
301
302 return 0;
303 }
304
305 /*
306 * Refer to drivers/acpi/cppc_acpi.c for the description of the functions
307 * below.
308 */
cpc_ffh_supported(void)309 bool cpc_ffh_supported(void)
310 {
311 int cpu = get_cpu_with_amu_feat();
312
313 /*
314 * FFH is considered supported if there is at least one present CPU that
315 * supports AMUs. Using FFH to read core and reference counters for CPUs
316 * that do not support AMUs, have counters disabled or that are affected
317 * by errata, will result in a return value of 0.
318 *
319 * This is done to allow any enabled and valid counters to be read
320 * through FFH, knowing that potentially returning 0 as counter value is
321 * properly handled by the users of these counters.
322 */
323 if ((cpu >= nr_cpu_ids) || !cpumask_test_cpu(cpu, cpu_present_mask))
324 return false;
325
326 return true;
327 }
328
cpc_read_ffh(int cpu,struct cpc_reg * reg,u64 * val)329 int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
330 {
331 int ret = -EOPNOTSUPP;
332
333 switch ((u64)reg->address) {
334 case 0x0:
335 ret = counters_read_on_cpu(cpu, cpu_read_corecnt, val);
336 break;
337 case 0x1:
338 ret = counters_read_on_cpu(cpu, cpu_read_constcnt, val);
339 break;
340 }
341
342 if (!ret) {
343 *val &= GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
344 reg->bit_offset);
345 *val >>= reg->bit_offset;
346 }
347
348 return ret;
349 }
350
cpc_write_ffh(int cpunum,struct cpc_reg * reg,u64 val)351 int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
352 {
353 return -EOPNOTSUPP;
354 }
355 #endif /* CONFIG_ACPI_CPPC_LIB */
356