1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 ARM Ltd.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #include <linux/kvm_host.h>
8 #include <linux/random.h>
9 #include <linux/memblock.h>
10 #include <asm/alternative.h>
11 #include <asm/debug-monitors.h>
12 #include <asm/insn.h>
13 #include <asm/kvm_mmu.h>
14 #include <asm/memory.h>
15 #include <asm/patching.h>
16
17 /*
18 * The LSB of the HYP VA tag
19 */
20 static u8 tag_lsb;
21 /*
22 * The HYP VA tag value with the region bit
23 */
24 static u64 tag_val;
25 static u64 va_mask;
26
27 /*
28 * Compute HYP VA by using the same computation as kern_hyp_va().
29 */
__early_kern_hyp_va(u64 addr)30 static u64 __early_kern_hyp_va(u64 addr)
31 {
32 addr &= va_mask;
33 addr |= tag_val << tag_lsb;
34 return addr;
35 }
36
37 /*
38 * Store a hyp VA <-> PA offset into a EL2-owned variable.
39 */
init_hyp_physvirt_offset(void)40 static void init_hyp_physvirt_offset(void)
41 {
42 u64 kern_va, hyp_va;
43
44 /* Compute the offset from the hyp VA and PA of a random symbol. */
45 kern_va = (u64)lm_alias(__hyp_text_start);
46 hyp_va = __early_kern_hyp_va(kern_va);
47 hyp_physvirt_offset = (s64)__pa(kern_va) - (s64)hyp_va;
48 }
49
50 /*
51 * We want to generate a hyp VA with the following format (with V ==
52 * vabits_actual):
53 *
54 * 63 ... V | V-1 | V-2 .. tag_lsb | tag_lsb - 1 .. 0
55 * ---------------------------------------------------------
56 * | 0000000 | hyp_va_msb | random tag | kern linear VA |
57 * |--------- tag_val -----------|----- va_mask ---|
58 *
59 * which does not conflict with the idmap regions.
60 */
kvm_compute_layout(void)61 __init void kvm_compute_layout(void)
62 {
63 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
64 u64 hyp_va_msb;
65
66 /* Where is my RAM region? */
67 hyp_va_msb = idmap_addr & BIT(vabits_actual - 1);
68 hyp_va_msb ^= BIT(vabits_actual - 1);
69
70 tag_lsb = fls64((u64)phys_to_virt(memblock_start_of_DRAM()) ^
71 (u64)(high_memory - 1));
72
73 va_mask = GENMASK_ULL(tag_lsb - 1, 0);
74 tag_val = hyp_va_msb;
75
76 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && tag_lsb != (vabits_actual - 1)) {
77 /* We have some free bits to insert a random tag. */
78 tag_val |= get_random_long() & GENMASK_ULL(vabits_actual - 2, tag_lsb);
79 }
80 tag_val >>= tag_lsb;
81
82 init_hyp_physvirt_offset();
83 }
84
85 /*
86 * The .hyp.reloc ELF section contains a list of kimg positions that
87 * contains kimg VAs but will be accessed only in hyp execution context.
88 * Convert them to hyp VAs. See gen-hyprel.c for more details.
89 */
kvm_apply_hyp_relocations(void)90 __init void kvm_apply_hyp_relocations(void)
91 {
92 int32_t *rel;
93 int32_t *begin = (int32_t *)__hyp_reloc_begin;
94 int32_t *end = (int32_t *)__hyp_reloc_end;
95
96 for (rel = begin; rel < end; ++rel) {
97 uintptr_t *ptr, kimg_va;
98
99 /*
100 * Each entry contains a 32-bit relative offset from itself
101 * to a kimg VA position.
102 */
103 ptr = (uintptr_t *)lm_alias((char *)rel + *rel);
104
105 /* Read the kimg VA value at the relocation address. */
106 kimg_va = *ptr;
107
108 /* Convert to hyp VA and store back to the relocation address. */
109 *ptr = __early_kern_hyp_va((uintptr_t)lm_alias(kimg_va));
110 }
111 }
112
kvm_apply_hyp_module_relocations(void * mod_start,void * hyp_va,kvm_nvhe_reloc_t * begin,kvm_nvhe_reloc_t * end)113 void kvm_apply_hyp_module_relocations(void *mod_start, void *hyp_va,
114 kvm_nvhe_reloc_t *begin,
115 kvm_nvhe_reloc_t *end)
116 {
117 kvm_nvhe_reloc_t *rel;
118
119 for (rel = begin; rel < end; ++rel) {
120 u32 **ptr, *va;
121
122 /*
123 * Each entry contains a 32-bit relative offset from itself
124 * to a VA position in the module area.
125 */
126 ptr = (u32 **)((char *)rel + *rel);
127
128 /* Read the module VA value at the relocation address. */
129 va = *ptr;
130
131 /* Convert the module VA of the reloc to a hyp VA */
132 WARN_ON(aarch64_insn_write_literal_u64(ptr,
133 (u64)(((void *)va - mod_start) + hyp_va)));
134 }
135 }
136
compute_instruction(int n,u32 rd,u32 rn)137 static u32 compute_instruction(int n, u32 rd, u32 rn)
138 {
139 u32 insn = AARCH64_BREAK_FAULT;
140
141 switch (n) {
142 case 0:
143 insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND,
144 AARCH64_INSN_VARIANT_64BIT,
145 rn, rd, va_mask);
146 break;
147
148 case 1:
149 /* ROR is a variant of EXTR with Rm = Rn */
150 insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
151 rn, rn, rd,
152 tag_lsb);
153 break;
154
155 case 2:
156 insn = aarch64_insn_gen_add_sub_imm(rd, rn,
157 tag_val & GENMASK(11, 0),
158 AARCH64_INSN_VARIANT_64BIT,
159 AARCH64_INSN_ADSB_ADD);
160 break;
161
162 case 3:
163 insn = aarch64_insn_gen_add_sub_imm(rd, rn,
164 tag_val & GENMASK(23, 12),
165 AARCH64_INSN_VARIANT_64BIT,
166 AARCH64_INSN_ADSB_ADD);
167 break;
168
169 case 4:
170 /* ROR is a variant of EXTR with Rm = Rn */
171 insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
172 rn, rn, rd, 64 - tag_lsb);
173 break;
174 }
175
176 return insn;
177 }
178
kvm_update_va_mask(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)179 void __init kvm_update_va_mask(struct alt_instr *alt,
180 __le32 *origptr, __le32 *updptr, int nr_inst)
181 {
182 int i;
183
184 BUG_ON(nr_inst != 5);
185
186 for (i = 0; i < nr_inst; i++) {
187 u32 rd, rn, insn, oinsn;
188
189 /*
190 * VHE doesn't need any address translation, let's NOP
191 * everything.
192 *
193 * Alternatively, if the tag is zero (because the layout
194 * dictates it and we don't have any spare bits in the
195 * address), NOP everything after masking the kernel VA.
196 */
197 if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN) || (!tag_val && i > 0)) {
198 updptr[i] = cpu_to_le32(aarch64_insn_gen_nop());
199 continue;
200 }
201
202 oinsn = le32_to_cpu(origptr[i]);
203 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
204 rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
205
206 insn = compute_instruction(i, rd, rn);
207 BUG_ON(insn == AARCH64_BREAK_FAULT);
208
209 updptr[i] = cpu_to_le32(insn);
210 }
211 }
212
kvm_patch_vector_branch(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)213 void kvm_patch_vector_branch(struct alt_instr *alt,
214 __le32 *origptr, __le32 *updptr, int nr_inst)
215 {
216 u64 addr;
217 u32 insn;
218
219 BUG_ON(nr_inst != 4);
220
221 if (!cpus_have_cap(ARM64_SPECTRE_V3A) ||
222 WARN_ON_ONCE(cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)))
223 return;
224
225 /*
226 * Compute HYP VA by using the same computation as kern_hyp_va()
227 */
228 addr = __early_kern_hyp_va((u64)kvm_ksym_ref(__kvm_hyp_vector));
229
230 /* Use PC[10:7] to branch to the same vector in KVM */
231 addr |= ((u64)origptr & GENMASK_ULL(10, 7));
232
233 /*
234 * Branch over the preamble in order to avoid the initial store on
235 * the stack (which we already perform in the hardening vectors).
236 */
237 addr += KVM_VECTOR_PREAMBLE;
238
239 /* movz x0, #(addr & 0xffff) */
240 insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
241 (u16)addr,
242 0,
243 AARCH64_INSN_VARIANT_64BIT,
244 AARCH64_INSN_MOVEWIDE_ZERO);
245 *updptr++ = cpu_to_le32(insn);
246
247 /* movk x0, #((addr >> 16) & 0xffff), lsl #16 */
248 insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
249 (u16)(addr >> 16),
250 16,
251 AARCH64_INSN_VARIANT_64BIT,
252 AARCH64_INSN_MOVEWIDE_KEEP);
253 *updptr++ = cpu_to_le32(insn);
254
255 /* movk x0, #((addr >> 32) & 0xffff), lsl #32 */
256 insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
257 (u16)(addr >> 32),
258 32,
259 AARCH64_INSN_VARIANT_64BIT,
260 AARCH64_INSN_MOVEWIDE_KEEP);
261 *updptr++ = cpu_to_le32(insn);
262
263 /* br x0 */
264 insn = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_0,
265 AARCH64_INSN_BRANCH_NOLINK);
266 *updptr++ = cpu_to_le32(insn);
267 }
268
generate_mov_q(u64 val,__le32 * origptr,__le32 * updptr,int nr_inst)269 static void generate_mov_q(u64 val, __le32 *origptr, __le32 *updptr, int nr_inst)
270 {
271 u32 insn, oinsn, rd;
272
273 BUG_ON(nr_inst != 4);
274
275 /* Compute target register */
276 oinsn = le32_to_cpu(*origptr);
277 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
278
279 /* movz rd, #(val & 0xffff) */
280 insn = aarch64_insn_gen_movewide(rd,
281 (u16)val,
282 0,
283 AARCH64_INSN_VARIANT_64BIT,
284 AARCH64_INSN_MOVEWIDE_ZERO);
285 *updptr++ = cpu_to_le32(insn);
286
287 /* movk rd, #((val >> 16) & 0xffff), lsl #16 */
288 insn = aarch64_insn_gen_movewide(rd,
289 (u16)(val >> 16),
290 16,
291 AARCH64_INSN_VARIANT_64BIT,
292 AARCH64_INSN_MOVEWIDE_KEEP);
293 *updptr++ = cpu_to_le32(insn);
294
295 /* movk rd, #((val >> 32) & 0xffff), lsl #32 */
296 insn = aarch64_insn_gen_movewide(rd,
297 (u16)(val >> 32),
298 32,
299 AARCH64_INSN_VARIANT_64BIT,
300 AARCH64_INSN_MOVEWIDE_KEEP);
301 *updptr++ = cpu_to_le32(insn);
302
303 /* movk rd, #((val >> 48) & 0xffff), lsl #48 */
304 insn = aarch64_insn_gen_movewide(rd,
305 (u16)(val >> 48),
306 48,
307 AARCH64_INSN_VARIANT_64BIT,
308 AARCH64_INSN_MOVEWIDE_KEEP);
309 *updptr++ = cpu_to_le32(insn);
310 }
311
kvm_get_kimage_voffset(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)312 void kvm_get_kimage_voffset(struct alt_instr *alt,
313 __le32 *origptr, __le32 *updptr, int nr_inst)
314 {
315 generate_mov_q(kimage_voffset, origptr, updptr, nr_inst);
316 }
317
kvm_compute_final_ctr_el0(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)318 void kvm_compute_final_ctr_el0(struct alt_instr *alt,
319 __le32 *origptr, __le32 *updptr, int nr_inst)
320 {
321 generate_mov_q(read_sanitised_ftr_reg(SYS_CTR_EL0),
322 origptr, updptr, nr_inst);
323 }
324