1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Apple DART (Device Address Resolution Table) IOMMU driver
4 *
5 * Copyright (C) 2021 The Asahi Linux Contributors
6 *
7 * Based on arm/arm-smmu/arm-ssmu.c and arm/arm-smmu-v3/arm-smmu-v3.c
8 * Copyright (C) 2013 ARM Limited
9 * Copyright (C) 2015 ARM Limited
10 * and on exynos-iommu.c
11 * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
12 */
13
14 #include <linux/atomic.h>
15 #include <linux/bitfield.h>
16 #include <linux/clk.h>
17 #include <linux/dev_printk.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/io-pgtable.h>
22 #include <linux/iommu.h>
23 #include <linux/iopoll.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_address.h>
27 #include <linux/of_iommu.h>
28 #include <linux/of_platform.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/swab.h>
33 #include <linux/types.h>
34
35 #include "dma-iommu.h"
36
37 #define DART_MAX_STREAMS 256
38 #define DART_MAX_TTBR 4
39 #define MAX_DARTS_PER_DEVICE 2
40
41 /* Common registers */
42
43 #define DART_PARAMS1 0x00
44 #define DART_PARAMS1_PAGE_SHIFT GENMASK(27, 24)
45
46 #define DART_PARAMS2 0x04
47 #define DART_PARAMS2_BYPASS_SUPPORT BIT(0)
48
49 /* T8020/T6000 registers */
50
51 #define DART_T8020_STREAM_COMMAND 0x20
52 #define DART_T8020_STREAM_COMMAND_BUSY BIT(2)
53 #define DART_T8020_STREAM_COMMAND_INVALIDATE BIT(20)
54
55 #define DART_T8020_STREAM_SELECT 0x34
56
57 #define DART_T8020_ERROR 0x40
58 #define DART_T8020_ERROR_STREAM GENMASK(27, 24)
59 #define DART_T8020_ERROR_CODE GENMASK(11, 0)
60 #define DART_T8020_ERROR_FLAG BIT(31)
61
62 #define DART_T8020_ERROR_READ_FAULT BIT(4)
63 #define DART_T8020_ERROR_WRITE_FAULT BIT(3)
64 #define DART_T8020_ERROR_NO_PTE BIT(2)
65 #define DART_T8020_ERROR_NO_PMD BIT(1)
66 #define DART_T8020_ERROR_NO_TTBR BIT(0)
67
68 #define DART_T8020_CONFIG 0x60
69 #define DART_T8020_CONFIG_LOCK BIT(15)
70
71 #define DART_STREAM_COMMAND_BUSY_TIMEOUT 100
72
73 #define DART_T8020_ERROR_ADDR_HI 0x54
74 #define DART_T8020_ERROR_ADDR_LO 0x50
75
76 #define DART_T8020_STREAMS_ENABLE 0xfc
77
78 #define DART_T8020_TCR 0x100
79 #define DART_T8020_TCR_TRANSLATE_ENABLE BIT(7)
80 #define DART_T8020_TCR_BYPASS_DART BIT(8)
81 #define DART_T8020_TCR_BYPASS_DAPF BIT(12)
82
83 #define DART_T8020_TTBR 0x200
84 #define DART_T8020_TTBR_VALID BIT(31)
85 #define DART_T8020_TTBR_ADDR_FIELD_SHIFT 0
86 #define DART_T8020_TTBR_SHIFT 12
87
88 /* T8110 registers */
89
90 #define DART_T8110_PARAMS3 0x08
91 #define DART_T8110_PARAMS3_PA_WIDTH GENMASK(29, 24)
92 #define DART_T8110_PARAMS3_VA_WIDTH GENMASK(21, 16)
93 #define DART_T8110_PARAMS3_VER_MAJ GENMASK(15, 8)
94 #define DART_T8110_PARAMS3_VER_MIN GENMASK(7, 0)
95
96 #define DART_T8110_PARAMS4 0x0c
97 #define DART_T8110_PARAMS4_NUM_CLIENTS GENMASK(24, 16)
98 #define DART_T8110_PARAMS4_NUM_SIDS GENMASK(8, 0)
99
100 #define DART_T8110_TLB_CMD 0x80
101 #define DART_T8110_TLB_CMD_BUSY BIT(31)
102 #define DART_T8110_TLB_CMD_OP GENMASK(10, 8)
103 #define DART_T8110_TLB_CMD_OP_FLUSH_ALL 0
104 #define DART_T8110_TLB_CMD_OP_FLUSH_SID 1
105 #define DART_T8110_TLB_CMD_STREAM GENMASK(7, 0)
106
107 #define DART_T8110_ERROR 0x100
108 #define DART_T8110_ERROR_STREAM GENMASK(27, 20)
109 #define DART_T8110_ERROR_CODE GENMASK(14, 0)
110 #define DART_T8110_ERROR_FLAG BIT(31)
111
112 #define DART_T8110_ERROR_MASK 0x104
113
114 #define DART_T8110_ERROR_READ_FAULT BIT(5)
115 #define DART_T8110_ERROR_WRITE_FAULT BIT(4)
116 #define DART_T8110_ERROR_NO_PTE BIT(3)
117 #define DART_T8110_ERROR_NO_PMD BIT(2)
118 #define DART_T8110_ERROR_NO_PGD BIT(1)
119 #define DART_T8110_ERROR_NO_TTBR BIT(0)
120
121 #define DART_T8110_ERROR_ADDR_LO 0x170
122 #define DART_T8110_ERROR_ADDR_HI 0x174
123
124 #define DART_T8110_PROTECT 0x200
125 #define DART_T8110_UNPROTECT 0x204
126 #define DART_T8110_PROTECT_LOCK 0x208
127 #define DART_T8110_PROTECT_TTBR_TCR BIT(0)
128
129 #define DART_T8110_ENABLE_STREAMS 0xc00
130 #define DART_T8110_DISABLE_STREAMS 0xc20
131
132 #define DART_T8110_TCR 0x1000
133 #define DART_T8110_TCR_REMAP GENMASK(11, 8)
134 #define DART_T8110_TCR_REMAP_EN BIT(7)
135 #define DART_T8110_TCR_BYPASS_DAPF BIT(2)
136 #define DART_T8110_TCR_BYPASS_DART BIT(1)
137 #define DART_T8110_TCR_TRANSLATE_ENABLE BIT(0)
138
139 #define DART_T8110_TTBR 0x1400
140 #define DART_T8110_TTBR_VALID BIT(0)
141 #define DART_T8110_TTBR_ADDR_FIELD_SHIFT 2
142 #define DART_T8110_TTBR_SHIFT 14
143
144 #define DART_TCR(dart, sid) ((dart)->hw->tcr + ((sid) << 2))
145
146 #define DART_TTBR(dart, sid, idx) ((dart)->hw->ttbr + \
147 (((dart)->hw->ttbr_count * (sid)) << 2) + \
148 ((idx) << 2))
149
150 struct apple_dart_stream_map;
151
152 enum dart_type {
153 DART_T8020,
154 DART_T6000,
155 DART_T8110,
156 };
157
158 struct apple_dart_hw {
159 enum dart_type type;
160 irqreturn_t (*irq_handler)(int irq, void *dev);
161 int (*invalidate_tlb)(struct apple_dart_stream_map *stream_map);
162
163 u32 oas;
164 enum io_pgtable_fmt fmt;
165
166 int max_sid_count;
167
168 u64 lock;
169 u64 lock_bit;
170
171 u64 error;
172
173 u64 enable_streams;
174
175 u64 tcr;
176 u64 tcr_enabled;
177 u64 tcr_disabled;
178 u64 tcr_bypass;
179
180 u64 ttbr;
181 u64 ttbr_valid;
182 u64 ttbr_addr_field_shift;
183 u64 ttbr_shift;
184 int ttbr_count;
185 };
186
187 /*
188 * Private structure associated with each DART device.
189 *
190 * @dev: device struct
191 * @hw: SoC-specific hardware data
192 * @regs: mapped MMIO region
193 * @irq: interrupt number, can be shared with other DARTs
194 * @clks: clocks associated with this DART
195 * @num_clks: number of @clks
196 * @lock: lock for hardware operations involving this dart
197 * @pgsize: pagesize supported by this DART
198 * @supports_bypass: indicates if this DART supports bypass mode
199 * @force_bypass: force bypass mode due to pagesize mismatch?
200 * @sid2group: maps stream ids to iommu_groups
201 * @iommu: iommu core device
202 */
203 struct apple_dart {
204 struct device *dev;
205 const struct apple_dart_hw *hw;
206
207 void __iomem *regs;
208
209 int irq;
210 struct clk_bulk_data *clks;
211 int num_clks;
212
213 spinlock_t lock;
214
215 u32 ias;
216 u32 oas;
217 u32 pgsize;
218 u32 num_streams;
219 u32 supports_bypass : 1;
220 u32 force_bypass : 1;
221
222 struct iommu_group *sid2group[DART_MAX_STREAMS];
223 struct iommu_device iommu;
224
225 u32 save_tcr[DART_MAX_STREAMS];
226 u32 save_ttbr[DART_MAX_STREAMS][DART_MAX_TTBR];
227 };
228
229 /*
230 * Convenience struct to identify streams.
231 *
232 * The normal variant is used inside apple_dart_master_cfg which isn't written
233 * to concurrently.
234 * The atomic variant is used inside apple_dart_domain where we have to guard
235 * against races from potential parallel calls to attach/detach_device.
236 * Note that even inside the atomic variant the apple_dart pointer is not
237 * protected: This pointer is initialized once under the domain init mutex
238 * and never changed again afterwards. Devices with different dart pointers
239 * cannot be attached to the same domain.
240 *
241 * @dart dart pointer
242 * @sid stream id bitmap
243 */
244 struct apple_dart_stream_map {
245 struct apple_dart *dart;
246 DECLARE_BITMAP(sidmap, DART_MAX_STREAMS);
247 };
248 struct apple_dart_atomic_stream_map {
249 struct apple_dart *dart;
250 atomic_long_t sidmap[BITS_TO_LONGS(DART_MAX_STREAMS)];
251 };
252
253 /*
254 * This structure is attached to each iommu domain handled by a DART.
255 *
256 * @pgtbl_ops: pagetable ops allocated by io-pgtable
257 * @finalized: true if the domain has been completely initialized
258 * @init_lock: protects domain initialization
259 * @stream_maps: streams attached to this domain (valid for DMA/UNMANAGED only)
260 * @domain: core iommu domain pointer
261 */
262 struct apple_dart_domain {
263 struct io_pgtable_ops *pgtbl_ops;
264
265 bool finalized;
266 struct mutex init_lock;
267 struct apple_dart_atomic_stream_map stream_maps[MAX_DARTS_PER_DEVICE];
268
269 struct iommu_domain domain;
270 };
271
272 /*
273 * This structure is attached to devices with dev_iommu_priv_set() on of_xlate
274 * and contains a list of streams bound to this device.
275 * So far the worst case seen is a single device with two streams
276 * from different darts, such that this simple static array is enough.
277 *
278 * @streams: streams for this device
279 */
280 struct apple_dart_master_cfg {
281 struct apple_dart_stream_map stream_maps[MAX_DARTS_PER_DEVICE];
282 };
283
284 /*
285 * Helper macro to iterate over apple_dart_master_cfg.stream_maps and
286 * apple_dart_domain.stream_maps
287 *
288 * @i int used as loop variable
289 * @base pointer to base struct (apple_dart_master_cfg or apple_dart_domain)
290 * @stream pointer to the apple_dart_streams struct for each loop iteration
291 */
292 #define for_each_stream_map(i, base, stream_map) \
293 for (i = 0, stream_map = &(base)->stream_maps[0]; \
294 i < MAX_DARTS_PER_DEVICE && stream_map->dart; \
295 stream_map = &(base)->stream_maps[++i])
296
297 static struct platform_driver apple_dart_driver;
298 static const struct iommu_ops apple_dart_iommu_ops;
299
to_dart_domain(struct iommu_domain * dom)300 static struct apple_dart_domain *to_dart_domain(struct iommu_domain *dom)
301 {
302 return container_of(dom, struct apple_dart_domain, domain);
303 }
304
305 static void
apple_dart_hw_enable_translation(struct apple_dart_stream_map * stream_map)306 apple_dart_hw_enable_translation(struct apple_dart_stream_map *stream_map)
307 {
308 struct apple_dart *dart = stream_map->dart;
309 int sid;
310
311 for_each_set_bit(sid, stream_map->sidmap, dart->num_streams)
312 writel(dart->hw->tcr_enabled, dart->regs + DART_TCR(dart, sid));
313 }
314
apple_dart_hw_disable_dma(struct apple_dart_stream_map * stream_map)315 static void apple_dart_hw_disable_dma(struct apple_dart_stream_map *stream_map)
316 {
317 struct apple_dart *dart = stream_map->dart;
318 int sid;
319
320 for_each_set_bit(sid, stream_map->sidmap, dart->num_streams)
321 writel(dart->hw->tcr_disabled, dart->regs + DART_TCR(dart, sid));
322 }
323
324 static void
apple_dart_hw_enable_bypass(struct apple_dart_stream_map * stream_map)325 apple_dart_hw_enable_bypass(struct apple_dart_stream_map *stream_map)
326 {
327 struct apple_dart *dart = stream_map->dart;
328 int sid;
329
330 WARN_ON(!stream_map->dart->supports_bypass);
331 for_each_set_bit(sid, stream_map->sidmap, dart->num_streams)
332 writel(dart->hw->tcr_bypass,
333 dart->regs + DART_TCR(dart, sid));
334 }
335
apple_dart_hw_set_ttbr(struct apple_dart_stream_map * stream_map,u8 idx,phys_addr_t paddr)336 static void apple_dart_hw_set_ttbr(struct apple_dart_stream_map *stream_map,
337 u8 idx, phys_addr_t paddr)
338 {
339 struct apple_dart *dart = stream_map->dart;
340 int sid;
341
342 WARN_ON(paddr & ((1 << dart->hw->ttbr_shift) - 1));
343 for_each_set_bit(sid, stream_map->sidmap, dart->num_streams)
344 writel(dart->hw->ttbr_valid |
345 (paddr >> dart->hw->ttbr_shift) << dart->hw->ttbr_addr_field_shift,
346 dart->regs + DART_TTBR(dart, sid, idx));
347 }
348
apple_dart_hw_clear_ttbr(struct apple_dart_stream_map * stream_map,u8 idx)349 static void apple_dart_hw_clear_ttbr(struct apple_dart_stream_map *stream_map,
350 u8 idx)
351 {
352 struct apple_dart *dart = stream_map->dart;
353 int sid;
354
355 for_each_set_bit(sid, stream_map->sidmap, dart->num_streams)
356 writel(0, dart->regs + DART_TTBR(dart, sid, idx));
357 }
358
359 static void
apple_dart_hw_clear_all_ttbrs(struct apple_dart_stream_map * stream_map)360 apple_dart_hw_clear_all_ttbrs(struct apple_dart_stream_map *stream_map)
361 {
362 int i;
363
364 for (i = 0; i < stream_map->dart->hw->ttbr_count; ++i)
365 apple_dart_hw_clear_ttbr(stream_map, i);
366 }
367
368 static int
apple_dart_t8020_hw_stream_command(struct apple_dart_stream_map * stream_map,u32 command)369 apple_dart_t8020_hw_stream_command(struct apple_dart_stream_map *stream_map,
370 u32 command)
371 {
372 unsigned long flags;
373 int ret;
374 u32 command_reg;
375
376 spin_lock_irqsave(&stream_map->dart->lock, flags);
377
378 writel(stream_map->sidmap[0], stream_map->dart->regs + DART_T8020_STREAM_SELECT);
379 writel(command, stream_map->dart->regs + DART_T8020_STREAM_COMMAND);
380
381 ret = readl_poll_timeout_atomic(
382 stream_map->dart->regs + DART_T8020_STREAM_COMMAND, command_reg,
383 !(command_reg & DART_T8020_STREAM_COMMAND_BUSY), 1,
384 DART_STREAM_COMMAND_BUSY_TIMEOUT);
385
386 spin_unlock_irqrestore(&stream_map->dart->lock, flags);
387
388 if (ret) {
389 dev_err(stream_map->dart->dev,
390 "busy bit did not clear after command %x for streams %lx\n",
391 command, stream_map->sidmap[0]);
392 return ret;
393 }
394
395 return 0;
396 }
397
398 static int
apple_dart_t8110_hw_tlb_command(struct apple_dart_stream_map * stream_map,u32 command)399 apple_dart_t8110_hw_tlb_command(struct apple_dart_stream_map *stream_map,
400 u32 command)
401 {
402 struct apple_dart *dart = stream_map->dart;
403 unsigned long flags;
404 int ret = 0;
405 int sid;
406
407 spin_lock_irqsave(&dart->lock, flags);
408
409 for_each_set_bit(sid, stream_map->sidmap, dart->num_streams) {
410 u32 val = FIELD_PREP(DART_T8110_TLB_CMD_OP, command) |
411 FIELD_PREP(DART_T8110_TLB_CMD_STREAM, sid);
412 writel(val, dart->regs + DART_T8110_TLB_CMD);
413
414 ret = readl_poll_timeout_atomic(
415 dart->regs + DART_T8110_TLB_CMD, val,
416 !(val & DART_T8110_TLB_CMD_BUSY), 1,
417 DART_STREAM_COMMAND_BUSY_TIMEOUT);
418
419 if (ret)
420 break;
421
422 }
423
424 spin_unlock_irqrestore(&dart->lock, flags);
425
426 if (ret) {
427 dev_err(stream_map->dart->dev,
428 "busy bit did not clear after command %x for stream %d\n",
429 command, sid);
430 return ret;
431 }
432
433 return 0;
434 }
435
436 static int
apple_dart_t8020_hw_invalidate_tlb(struct apple_dart_stream_map * stream_map)437 apple_dart_t8020_hw_invalidate_tlb(struct apple_dart_stream_map *stream_map)
438 {
439 return apple_dart_t8020_hw_stream_command(
440 stream_map, DART_T8020_STREAM_COMMAND_INVALIDATE);
441 }
442
443 static int
apple_dart_t8110_hw_invalidate_tlb(struct apple_dart_stream_map * stream_map)444 apple_dart_t8110_hw_invalidate_tlb(struct apple_dart_stream_map *stream_map)
445 {
446 return apple_dart_t8110_hw_tlb_command(
447 stream_map, DART_T8110_TLB_CMD_OP_FLUSH_SID);
448 }
449
apple_dart_hw_reset(struct apple_dart * dart)450 static int apple_dart_hw_reset(struct apple_dart *dart)
451 {
452 u32 config;
453 struct apple_dart_stream_map stream_map;
454 int i;
455
456 config = readl(dart->regs + dart->hw->lock);
457 if (config & dart->hw->lock_bit) {
458 dev_err(dart->dev, "DART is locked down until reboot: %08x\n",
459 config);
460 return -EINVAL;
461 }
462
463 stream_map.dart = dart;
464 bitmap_zero(stream_map.sidmap, DART_MAX_STREAMS);
465 bitmap_set(stream_map.sidmap, 0, dart->num_streams);
466 apple_dart_hw_disable_dma(&stream_map);
467 apple_dart_hw_clear_all_ttbrs(&stream_map);
468
469 /* enable all streams globally since TCR is used to control isolation */
470 for (i = 0; i < BITS_TO_U32(dart->num_streams); i++)
471 writel(U32_MAX, dart->regs + dart->hw->enable_streams + 4 * i);
472
473 /* clear any pending errors before the interrupt is unmasked */
474 writel(readl(dart->regs + dart->hw->error), dart->regs + dart->hw->error);
475
476 if (dart->hw->type == DART_T8110)
477 writel(0, dart->regs + DART_T8110_ERROR_MASK);
478
479 return dart->hw->invalidate_tlb(&stream_map);
480 }
481
apple_dart_domain_flush_tlb(struct apple_dart_domain * domain)482 static void apple_dart_domain_flush_tlb(struct apple_dart_domain *domain)
483 {
484 int i, j;
485 struct apple_dart_atomic_stream_map *domain_stream_map;
486 struct apple_dart_stream_map stream_map;
487
488 for_each_stream_map(i, domain, domain_stream_map) {
489 stream_map.dart = domain_stream_map->dart;
490
491 for (j = 0; j < BITS_TO_LONGS(stream_map.dart->num_streams); j++)
492 stream_map.sidmap[j] = atomic_long_read(&domain_stream_map->sidmap[j]);
493
494 stream_map.dart->hw->invalidate_tlb(&stream_map);
495 }
496 }
497
apple_dart_flush_iotlb_all(struct iommu_domain * domain)498 static void apple_dart_flush_iotlb_all(struct iommu_domain *domain)
499 {
500 apple_dart_domain_flush_tlb(to_dart_domain(domain));
501 }
502
apple_dart_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)503 static void apple_dart_iotlb_sync(struct iommu_domain *domain,
504 struct iommu_iotlb_gather *gather)
505 {
506 apple_dart_domain_flush_tlb(to_dart_domain(domain));
507 }
508
apple_dart_iotlb_sync_map(struct iommu_domain * domain,unsigned long iova,size_t size)509 static void apple_dart_iotlb_sync_map(struct iommu_domain *domain,
510 unsigned long iova, size_t size)
511 {
512 apple_dart_domain_flush_tlb(to_dart_domain(domain));
513 }
514
apple_dart_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)515 static phys_addr_t apple_dart_iova_to_phys(struct iommu_domain *domain,
516 dma_addr_t iova)
517 {
518 struct apple_dart_domain *dart_domain = to_dart_domain(domain);
519 struct io_pgtable_ops *ops = dart_domain->pgtbl_ops;
520
521 if (!ops)
522 return 0;
523
524 return ops->iova_to_phys(ops, iova);
525 }
526
apple_dart_map_pages(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int prot,gfp_t gfp,size_t * mapped)527 static int apple_dart_map_pages(struct iommu_domain *domain, unsigned long iova,
528 phys_addr_t paddr, size_t pgsize,
529 size_t pgcount, int prot, gfp_t gfp,
530 size_t *mapped)
531 {
532 struct apple_dart_domain *dart_domain = to_dart_domain(domain);
533 struct io_pgtable_ops *ops = dart_domain->pgtbl_ops;
534
535 if (!ops)
536 return -ENODEV;
537
538 return ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, gfp,
539 mapped);
540 }
541
apple_dart_unmap_pages(struct iommu_domain * domain,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)542 static size_t apple_dart_unmap_pages(struct iommu_domain *domain,
543 unsigned long iova, size_t pgsize,
544 size_t pgcount,
545 struct iommu_iotlb_gather *gather)
546 {
547 struct apple_dart_domain *dart_domain = to_dart_domain(domain);
548 struct io_pgtable_ops *ops = dart_domain->pgtbl_ops;
549
550 return ops->unmap_pages(ops, iova, pgsize, pgcount, gather);
551 }
552
553 static void
apple_dart_setup_translation(struct apple_dart_domain * domain,struct apple_dart_stream_map * stream_map)554 apple_dart_setup_translation(struct apple_dart_domain *domain,
555 struct apple_dart_stream_map *stream_map)
556 {
557 int i;
558 struct io_pgtable_cfg *pgtbl_cfg =
559 &io_pgtable_ops_to_pgtable(domain->pgtbl_ops)->cfg;
560
561 for (i = 0; i < pgtbl_cfg->apple_dart_cfg.n_ttbrs; ++i)
562 apple_dart_hw_set_ttbr(stream_map, i,
563 pgtbl_cfg->apple_dart_cfg.ttbr[i]);
564 for (; i < stream_map->dart->hw->ttbr_count; ++i)
565 apple_dart_hw_clear_ttbr(stream_map, i);
566
567 apple_dart_hw_enable_translation(stream_map);
568 stream_map->dart->hw->invalidate_tlb(stream_map);
569 }
570
apple_dart_finalize_domain(struct iommu_domain * domain,struct apple_dart_master_cfg * cfg)571 static int apple_dart_finalize_domain(struct iommu_domain *domain,
572 struct apple_dart_master_cfg *cfg)
573 {
574 struct apple_dart_domain *dart_domain = to_dart_domain(domain);
575 struct apple_dart *dart = cfg->stream_maps[0].dart;
576 struct io_pgtable_cfg pgtbl_cfg;
577 int ret = 0;
578 int i, j;
579
580 mutex_lock(&dart_domain->init_lock);
581
582 if (dart_domain->finalized)
583 goto done;
584
585 for (i = 0; i < MAX_DARTS_PER_DEVICE; ++i) {
586 dart_domain->stream_maps[i].dart = cfg->stream_maps[i].dart;
587 for (j = 0; j < BITS_TO_LONGS(dart->num_streams); j++)
588 atomic_long_set(&dart_domain->stream_maps[i].sidmap[j],
589 cfg->stream_maps[i].sidmap[j]);
590 }
591
592 pgtbl_cfg = (struct io_pgtable_cfg){
593 .pgsize_bitmap = dart->pgsize,
594 .ias = dart->ias,
595 .oas = dart->oas,
596 .coherent_walk = 1,
597 .iommu_dev = dart->dev,
598 };
599
600 dart_domain->pgtbl_ops =
601 alloc_io_pgtable_ops(dart->hw->fmt, &pgtbl_cfg, domain);
602 if (!dart_domain->pgtbl_ops) {
603 ret = -ENOMEM;
604 goto done;
605 }
606
607 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
608 domain->geometry.aperture_start = 0;
609 domain->geometry.aperture_end = (dma_addr_t)DMA_BIT_MASK(dart->ias);
610 domain->geometry.force_aperture = true;
611
612 dart_domain->finalized = true;
613
614 done:
615 mutex_unlock(&dart_domain->init_lock);
616 return ret;
617 }
618
619 static int
apple_dart_mod_streams(struct apple_dart_atomic_stream_map * domain_maps,struct apple_dart_stream_map * master_maps,bool add_streams)620 apple_dart_mod_streams(struct apple_dart_atomic_stream_map *domain_maps,
621 struct apple_dart_stream_map *master_maps,
622 bool add_streams)
623 {
624 int i, j;
625
626 for (i = 0; i < MAX_DARTS_PER_DEVICE; ++i) {
627 if (domain_maps[i].dart != master_maps[i].dart)
628 return -EINVAL;
629 }
630
631 for (i = 0; i < MAX_DARTS_PER_DEVICE; ++i) {
632 if (!domain_maps[i].dart)
633 break;
634 for (j = 0; j < BITS_TO_LONGS(domain_maps[i].dart->num_streams); j++) {
635 if (add_streams)
636 atomic_long_or(master_maps[i].sidmap[j],
637 &domain_maps[i].sidmap[j]);
638 else
639 atomic_long_and(~master_maps[i].sidmap[j],
640 &domain_maps[i].sidmap[j]);
641 }
642 }
643
644 return 0;
645 }
646
apple_dart_domain_add_streams(struct apple_dart_domain * domain,struct apple_dart_master_cfg * cfg)647 static int apple_dart_domain_add_streams(struct apple_dart_domain *domain,
648 struct apple_dart_master_cfg *cfg)
649 {
650 return apple_dart_mod_streams(domain->stream_maps, cfg->stream_maps,
651 true);
652 }
653
apple_dart_attach_dev(struct iommu_domain * domain,struct device * dev)654 static int apple_dart_attach_dev(struct iommu_domain *domain,
655 struct device *dev)
656 {
657 int ret, i;
658 struct apple_dart_stream_map *stream_map;
659 struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev);
660 struct apple_dart_domain *dart_domain = to_dart_domain(domain);
661
662 if (cfg->stream_maps[0].dart->force_bypass &&
663 domain->type != IOMMU_DOMAIN_IDENTITY)
664 return -EINVAL;
665 if (!cfg->stream_maps[0].dart->supports_bypass &&
666 domain->type == IOMMU_DOMAIN_IDENTITY)
667 return -EINVAL;
668
669 ret = apple_dart_finalize_domain(domain, cfg);
670 if (ret)
671 return ret;
672
673 switch (domain->type) {
674 default:
675 ret = apple_dart_domain_add_streams(dart_domain, cfg);
676 if (ret)
677 return ret;
678
679 for_each_stream_map(i, cfg, stream_map)
680 apple_dart_setup_translation(dart_domain, stream_map);
681 break;
682 case IOMMU_DOMAIN_BLOCKED:
683 for_each_stream_map(i, cfg, stream_map)
684 apple_dart_hw_disable_dma(stream_map);
685 break;
686 case IOMMU_DOMAIN_IDENTITY:
687 for_each_stream_map(i, cfg, stream_map)
688 apple_dart_hw_enable_bypass(stream_map);
689 break;
690 }
691
692 return ret;
693 }
694
apple_dart_probe_device(struct device * dev)695 static struct iommu_device *apple_dart_probe_device(struct device *dev)
696 {
697 struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev);
698 struct apple_dart_stream_map *stream_map;
699 int i;
700
701 if (!cfg)
702 return ERR_PTR(-ENODEV);
703
704 for_each_stream_map(i, cfg, stream_map)
705 device_link_add(
706 dev, stream_map->dart->dev,
707 DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_SUPPLIER);
708
709 return &cfg->stream_maps[0].dart->iommu;
710 }
711
apple_dart_release_device(struct device * dev)712 static void apple_dart_release_device(struct device *dev)
713 {
714 struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev);
715
716 dev_iommu_priv_set(dev, NULL);
717 kfree(cfg);
718 }
719
apple_dart_domain_alloc(unsigned int type)720 static struct iommu_domain *apple_dart_domain_alloc(unsigned int type)
721 {
722 struct apple_dart_domain *dart_domain;
723
724 if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED &&
725 type != IOMMU_DOMAIN_IDENTITY && type != IOMMU_DOMAIN_BLOCKED)
726 return NULL;
727
728 dart_domain = kzalloc(sizeof(*dart_domain), GFP_KERNEL);
729 if (!dart_domain)
730 return NULL;
731
732 mutex_init(&dart_domain->init_lock);
733
734 /* no need to allocate pgtbl_ops or do any other finalization steps */
735 if (type == IOMMU_DOMAIN_IDENTITY || type == IOMMU_DOMAIN_BLOCKED)
736 dart_domain->finalized = true;
737
738 return &dart_domain->domain;
739 }
740
apple_dart_domain_free(struct iommu_domain * domain)741 static void apple_dart_domain_free(struct iommu_domain *domain)
742 {
743 struct apple_dart_domain *dart_domain = to_dart_domain(domain);
744
745 if (dart_domain->pgtbl_ops)
746 free_io_pgtable_ops(dart_domain->pgtbl_ops);
747
748 kfree(dart_domain);
749 }
750
apple_dart_of_xlate(struct device * dev,struct of_phandle_args * args)751 static int apple_dart_of_xlate(struct device *dev, struct of_phandle_args *args)
752 {
753 struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev);
754 struct platform_device *iommu_pdev = of_find_device_by_node(args->np);
755 struct apple_dart *dart = platform_get_drvdata(iommu_pdev);
756 struct apple_dart *cfg_dart;
757 int i, sid;
758
759 if (args->args_count != 1)
760 return -EINVAL;
761 sid = args->args[0];
762
763 if (!cfg)
764 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
765 if (!cfg)
766 return -ENOMEM;
767 dev_iommu_priv_set(dev, cfg);
768
769 cfg_dart = cfg->stream_maps[0].dart;
770 if (cfg_dart) {
771 if (cfg_dart->supports_bypass != dart->supports_bypass)
772 return -EINVAL;
773 if (cfg_dart->force_bypass != dart->force_bypass)
774 return -EINVAL;
775 if (cfg_dart->pgsize != dart->pgsize)
776 return -EINVAL;
777 }
778
779 for (i = 0; i < MAX_DARTS_PER_DEVICE; ++i) {
780 if (cfg->stream_maps[i].dart == dart) {
781 set_bit(sid, cfg->stream_maps[i].sidmap);
782 return 0;
783 }
784 }
785 for (i = 0; i < MAX_DARTS_PER_DEVICE; ++i) {
786 if (!cfg->stream_maps[i].dart) {
787 cfg->stream_maps[i].dart = dart;
788 set_bit(sid, cfg->stream_maps[i].sidmap);
789 return 0;
790 }
791 }
792
793 return -EINVAL;
794 }
795
796 static DEFINE_MUTEX(apple_dart_groups_lock);
797
apple_dart_release_group(void * iommu_data)798 static void apple_dart_release_group(void *iommu_data)
799 {
800 int i, sid;
801 struct apple_dart_stream_map *stream_map;
802 struct apple_dart_master_cfg *group_master_cfg = iommu_data;
803
804 mutex_lock(&apple_dart_groups_lock);
805
806 for_each_stream_map(i, group_master_cfg, stream_map)
807 for_each_set_bit(sid, stream_map->sidmap, stream_map->dart->num_streams)
808 stream_map->dart->sid2group[sid] = NULL;
809
810 kfree(iommu_data);
811 mutex_unlock(&apple_dart_groups_lock);
812 }
813
apple_dart_merge_master_cfg(struct apple_dart_master_cfg * dst,struct apple_dart_master_cfg * src)814 static int apple_dart_merge_master_cfg(struct apple_dart_master_cfg *dst,
815 struct apple_dart_master_cfg *src)
816 {
817 /*
818 * We know that this function is only called for groups returned from
819 * pci_device_group and that all Apple Silicon platforms never spread
820 * PCIe devices from the same bus across multiple DARTs such that we can
821 * just assume that both src and dst only have the same single DART.
822 */
823 if (src->stream_maps[1].dart)
824 return -EINVAL;
825 if (dst->stream_maps[1].dart)
826 return -EINVAL;
827 if (src->stream_maps[0].dart != dst->stream_maps[0].dart)
828 return -EINVAL;
829
830 bitmap_or(dst->stream_maps[0].sidmap,
831 dst->stream_maps[0].sidmap,
832 src->stream_maps[0].sidmap,
833 dst->stream_maps[0].dart->num_streams);
834 return 0;
835 }
836
apple_dart_device_group(struct device * dev)837 static struct iommu_group *apple_dart_device_group(struct device *dev)
838 {
839 int i, sid;
840 struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev);
841 struct apple_dart_stream_map *stream_map;
842 struct apple_dart_master_cfg *group_master_cfg;
843 struct iommu_group *group = NULL;
844 struct iommu_group *res = ERR_PTR(-EINVAL);
845
846 mutex_lock(&apple_dart_groups_lock);
847
848 for_each_stream_map(i, cfg, stream_map) {
849 for_each_set_bit(sid, stream_map->sidmap, stream_map->dart->num_streams) {
850 struct iommu_group *stream_group =
851 stream_map->dart->sid2group[sid];
852
853 if (group && group != stream_group) {
854 res = ERR_PTR(-EINVAL);
855 goto out;
856 }
857
858 group = stream_group;
859 }
860 }
861
862 if (group) {
863 res = iommu_group_ref_get(group);
864 goto out;
865 }
866
867 #ifdef CONFIG_PCI
868 if (dev_is_pci(dev))
869 group = pci_device_group(dev);
870 else
871 #endif
872 group = generic_device_group(dev);
873
874 res = ERR_PTR(-ENOMEM);
875 if (!group)
876 goto out;
877
878 group_master_cfg = iommu_group_get_iommudata(group);
879 if (group_master_cfg) {
880 int ret;
881
882 ret = apple_dart_merge_master_cfg(group_master_cfg, cfg);
883 if (ret) {
884 dev_err(dev, "Failed to merge DART IOMMU grups.\n");
885 iommu_group_put(group);
886 res = ERR_PTR(ret);
887 goto out;
888 }
889 } else {
890 group_master_cfg = kmemdup(cfg, sizeof(*group_master_cfg),
891 GFP_KERNEL);
892 if (!group_master_cfg) {
893 iommu_group_put(group);
894 goto out;
895 }
896
897 iommu_group_set_iommudata(group, group_master_cfg,
898 apple_dart_release_group);
899 }
900
901 for_each_stream_map(i, cfg, stream_map)
902 for_each_set_bit(sid, stream_map->sidmap, stream_map->dart->num_streams)
903 stream_map->dart->sid2group[sid] = group;
904
905 res = group;
906
907 out:
908 mutex_unlock(&apple_dart_groups_lock);
909 return res;
910 }
911
apple_dart_def_domain_type(struct device * dev)912 static int apple_dart_def_domain_type(struct device *dev)
913 {
914 struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev);
915
916 if (cfg->stream_maps[0].dart->force_bypass)
917 return IOMMU_DOMAIN_IDENTITY;
918 if (!cfg->stream_maps[0].dart->supports_bypass)
919 return IOMMU_DOMAIN_DMA;
920
921 return 0;
922 }
923
924 #ifndef CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR
925 /* Keep things compiling when CONFIG_PCI_APPLE isn't selected */
926 #define CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR 0
927 #endif
928 #define DOORBELL_ADDR (CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR & PAGE_MASK)
929
apple_dart_get_resv_regions(struct device * dev,struct list_head * head)930 static void apple_dart_get_resv_regions(struct device *dev,
931 struct list_head *head)
932 {
933 if (IS_ENABLED(CONFIG_PCIE_APPLE) && dev_is_pci(dev)) {
934 struct iommu_resv_region *region;
935 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
936
937 region = iommu_alloc_resv_region(DOORBELL_ADDR,
938 PAGE_SIZE, prot,
939 IOMMU_RESV_MSI, GFP_KERNEL);
940 if (!region)
941 return;
942
943 list_add_tail(®ion->list, head);
944 }
945
946 iommu_dma_get_resv_regions(dev, head);
947 }
948
949 static const struct iommu_ops apple_dart_iommu_ops = {
950 .domain_alloc = apple_dart_domain_alloc,
951 .probe_device = apple_dart_probe_device,
952 .release_device = apple_dart_release_device,
953 .device_group = apple_dart_device_group,
954 .of_xlate = apple_dart_of_xlate,
955 .def_domain_type = apple_dart_def_domain_type,
956 .get_resv_regions = apple_dart_get_resv_regions,
957 .pgsize_bitmap = -1UL, /* Restricted during dart probe */
958 .owner = THIS_MODULE,
959 .default_domain_ops = &(const struct iommu_domain_ops) {
960 .attach_dev = apple_dart_attach_dev,
961 .map_pages = apple_dart_map_pages,
962 .unmap_pages = apple_dart_unmap_pages,
963 .flush_iotlb_all = apple_dart_flush_iotlb_all,
964 .iotlb_sync = apple_dart_iotlb_sync,
965 .iotlb_sync_map = apple_dart_iotlb_sync_map,
966 .iova_to_phys = apple_dart_iova_to_phys,
967 .free = apple_dart_domain_free,
968 }
969 };
970
apple_dart_t8020_irq(int irq,void * dev)971 static irqreturn_t apple_dart_t8020_irq(int irq, void *dev)
972 {
973 struct apple_dart *dart = dev;
974 const char *fault_name = NULL;
975 u32 error = readl(dart->regs + DART_T8020_ERROR);
976 u32 error_code = FIELD_GET(DART_T8020_ERROR_CODE, error);
977 u32 addr_lo = readl(dart->regs + DART_T8020_ERROR_ADDR_LO);
978 u32 addr_hi = readl(dart->regs + DART_T8020_ERROR_ADDR_HI);
979 u64 addr = addr_lo | (((u64)addr_hi) << 32);
980 u8 stream_idx = FIELD_GET(DART_T8020_ERROR_STREAM, error);
981
982 if (!(error & DART_T8020_ERROR_FLAG))
983 return IRQ_NONE;
984
985 /* there should only be a single bit set but let's use == to be sure */
986 if (error_code == DART_T8020_ERROR_READ_FAULT)
987 fault_name = "READ FAULT";
988 else if (error_code == DART_T8020_ERROR_WRITE_FAULT)
989 fault_name = "WRITE FAULT";
990 else if (error_code == DART_T8020_ERROR_NO_PTE)
991 fault_name = "NO PTE FOR IOVA";
992 else if (error_code == DART_T8020_ERROR_NO_PMD)
993 fault_name = "NO PMD FOR IOVA";
994 else if (error_code == DART_T8020_ERROR_NO_TTBR)
995 fault_name = "NO TTBR FOR IOVA";
996 else
997 fault_name = "unknown";
998
999 dev_err_ratelimited(
1000 dart->dev,
1001 "translation fault: status:0x%x stream:%d code:0x%x (%s) at 0x%llx",
1002 error, stream_idx, error_code, fault_name, addr);
1003
1004 writel(error, dart->regs + DART_T8020_ERROR);
1005 return IRQ_HANDLED;
1006 }
1007
apple_dart_t8110_irq(int irq,void * dev)1008 static irqreturn_t apple_dart_t8110_irq(int irq, void *dev)
1009 {
1010 struct apple_dart *dart = dev;
1011 const char *fault_name = NULL;
1012 u32 error = readl(dart->regs + DART_T8110_ERROR);
1013 u32 error_code = FIELD_GET(DART_T8110_ERROR_CODE, error);
1014 u32 addr_lo = readl(dart->regs + DART_T8110_ERROR_ADDR_LO);
1015 u32 addr_hi = readl(dart->regs + DART_T8110_ERROR_ADDR_HI);
1016 u64 addr = addr_lo | (((u64)addr_hi) << 32);
1017 u8 stream_idx = FIELD_GET(DART_T8110_ERROR_STREAM, error);
1018
1019 if (!(error & DART_T8110_ERROR_FLAG))
1020 return IRQ_NONE;
1021
1022 /* there should only be a single bit set but let's use == to be sure */
1023 if (error_code == DART_T8110_ERROR_READ_FAULT)
1024 fault_name = "READ FAULT";
1025 else if (error_code == DART_T8110_ERROR_WRITE_FAULT)
1026 fault_name = "WRITE FAULT";
1027 else if (error_code == DART_T8110_ERROR_NO_PTE)
1028 fault_name = "NO PTE FOR IOVA";
1029 else if (error_code == DART_T8110_ERROR_NO_PMD)
1030 fault_name = "NO PMD FOR IOVA";
1031 else if (error_code == DART_T8110_ERROR_NO_PGD)
1032 fault_name = "NO PGD FOR IOVA";
1033 else if (error_code == DART_T8110_ERROR_NO_TTBR)
1034 fault_name = "NO TTBR FOR IOVA";
1035 else
1036 fault_name = "unknown";
1037
1038 dev_err_ratelimited(
1039 dart->dev,
1040 "translation fault: status:0x%x stream:%d code:0x%x (%s) at 0x%llx",
1041 error, stream_idx, error_code, fault_name, addr);
1042
1043 writel(error, dart->regs + DART_T8110_ERROR);
1044 return IRQ_HANDLED;
1045 }
1046
apple_dart_probe(struct platform_device * pdev)1047 static int apple_dart_probe(struct platform_device *pdev)
1048 {
1049 int ret;
1050 u32 dart_params[4];
1051 struct resource *res;
1052 struct apple_dart *dart;
1053 struct device *dev = &pdev->dev;
1054
1055 dart = devm_kzalloc(dev, sizeof(*dart), GFP_KERNEL);
1056 if (!dart)
1057 return -ENOMEM;
1058
1059 dart->dev = dev;
1060 dart->hw = of_device_get_match_data(dev);
1061 spin_lock_init(&dart->lock);
1062
1063 dart->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1064 if (IS_ERR(dart->regs))
1065 return PTR_ERR(dart->regs);
1066
1067 if (resource_size(res) < 0x4000) {
1068 dev_err(dev, "MMIO region too small (%pr)\n", res);
1069 return -EINVAL;
1070 }
1071
1072 dart->irq = platform_get_irq(pdev, 0);
1073 if (dart->irq < 0)
1074 return -ENODEV;
1075
1076 ret = devm_clk_bulk_get_all(dev, &dart->clks);
1077 if (ret < 0)
1078 return ret;
1079 dart->num_clks = ret;
1080
1081 ret = clk_bulk_prepare_enable(dart->num_clks, dart->clks);
1082 if (ret)
1083 return ret;
1084
1085 dart_params[0] = readl(dart->regs + DART_PARAMS1);
1086 dart_params[1] = readl(dart->regs + DART_PARAMS2);
1087 dart->pgsize = 1 << FIELD_GET(DART_PARAMS1_PAGE_SHIFT, dart_params[0]);
1088 dart->supports_bypass = dart_params[1] & DART_PARAMS2_BYPASS_SUPPORT;
1089
1090 switch (dart->hw->type) {
1091 case DART_T8020:
1092 case DART_T6000:
1093 dart->ias = 32;
1094 dart->oas = dart->hw->oas;
1095 dart->num_streams = dart->hw->max_sid_count;
1096 break;
1097
1098 case DART_T8110:
1099 dart_params[2] = readl(dart->regs + DART_T8110_PARAMS3);
1100 dart_params[3] = readl(dart->regs + DART_T8110_PARAMS4);
1101 dart->ias = FIELD_GET(DART_T8110_PARAMS3_VA_WIDTH, dart_params[2]);
1102 dart->oas = FIELD_GET(DART_T8110_PARAMS3_PA_WIDTH, dart_params[2]);
1103 dart->num_streams = FIELD_GET(DART_T8110_PARAMS4_NUM_SIDS, dart_params[3]);
1104 break;
1105 }
1106
1107 if (dart->num_streams > DART_MAX_STREAMS) {
1108 dev_err(&pdev->dev, "Too many streams (%d > %d)\n",
1109 dart->num_streams, DART_MAX_STREAMS);
1110 ret = -EINVAL;
1111 goto err_clk_disable;
1112 }
1113
1114 dart->force_bypass = dart->pgsize > PAGE_SIZE;
1115
1116 ret = apple_dart_hw_reset(dart);
1117 if (ret)
1118 goto err_clk_disable;
1119
1120 ret = request_irq(dart->irq, dart->hw->irq_handler, IRQF_SHARED,
1121 "apple-dart fault handler", dart);
1122 if (ret)
1123 goto err_clk_disable;
1124
1125 platform_set_drvdata(pdev, dart);
1126
1127 ret = iommu_device_sysfs_add(&dart->iommu, dev, NULL, "apple-dart.%s",
1128 dev_name(&pdev->dev));
1129 if (ret)
1130 goto err_free_irq;
1131
1132 ret = iommu_device_register(&dart->iommu, &apple_dart_iommu_ops, dev);
1133 if (ret)
1134 goto err_sysfs_remove;
1135
1136 dev_info(
1137 &pdev->dev,
1138 "DART [pagesize %x, %d streams, bypass support: %d, bypass forced: %d] initialized\n",
1139 dart->pgsize, dart->num_streams, dart->supports_bypass, dart->force_bypass);
1140 return 0;
1141
1142 err_sysfs_remove:
1143 iommu_device_sysfs_remove(&dart->iommu);
1144 err_free_irq:
1145 free_irq(dart->irq, dart);
1146 err_clk_disable:
1147 clk_bulk_disable_unprepare(dart->num_clks, dart->clks);
1148
1149 return ret;
1150 }
1151
apple_dart_remove(struct platform_device * pdev)1152 static void apple_dart_remove(struct platform_device *pdev)
1153 {
1154 struct apple_dart *dart = platform_get_drvdata(pdev);
1155
1156 apple_dart_hw_reset(dart);
1157 free_irq(dart->irq, dart);
1158
1159 iommu_device_unregister(&dart->iommu);
1160 iommu_device_sysfs_remove(&dart->iommu);
1161
1162 clk_bulk_disable_unprepare(dart->num_clks, dart->clks);
1163 }
1164
1165 static const struct apple_dart_hw apple_dart_hw_t8103 = {
1166 .type = DART_T8020,
1167 .irq_handler = apple_dart_t8020_irq,
1168 .invalidate_tlb = apple_dart_t8020_hw_invalidate_tlb,
1169 .oas = 36,
1170 .fmt = APPLE_DART,
1171 .max_sid_count = 16,
1172
1173 .enable_streams = DART_T8020_STREAMS_ENABLE,
1174 .lock = DART_T8020_CONFIG,
1175 .lock_bit = DART_T8020_CONFIG_LOCK,
1176
1177 .error = DART_T8020_ERROR,
1178
1179 .tcr = DART_T8020_TCR,
1180 .tcr_enabled = DART_T8020_TCR_TRANSLATE_ENABLE,
1181 .tcr_disabled = 0,
1182 .tcr_bypass = DART_T8020_TCR_BYPASS_DAPF | DART_T8020_TCR_BYPASS_DART,
1183
1184 .ttbr = DART_T8020_TTBR,
1185 .ttbr_valid = DART_T8020_TTBR_VALID,
1186 .ttbr_addr_field_shift = DART_T8020_TTBR_ADDR_FIELD_SHIFT,
1187 .ttbr_shift = DART_T8020_TTBR_SHIFT,
1188 .ttbr_count = 4,
1189 };
1190 static const struct apple_dart_hw apple_dart_hw_t6000 = {
1191 .type = DART_T6000,
1192 .irq_handler = apple_dart_t8020_irq,
1193 .invalidate_tlb = apple_dart_t8020_hw_invalidate_tlb,
1194 .oas = 42,
1195 .fmt = APPLE_DART2,
1196 .max_sid_count = 16,
1197
1198 .enable_streams = DART_T8020_STREAMS_ENABLE,
1199 .lock = DART_T8020_CONFIG,
1200 .lock_bit = DART_T8020_CONFIG_LOCK,
1201
1202 .error = DART_T8020_ERROR,
1203
1204 .tcr = DART_T8020_TCR,
1205 .tcr_enabled = DART_T8020_TCR_TRANSLATE_ENABLE,
1206 .tcr_disabled = 0,
1207 .tcr_bypass = DART_T8020_TCR_BYPASS_DAPF | DART_T8020_TCR_BYPASS_DART,
1208
1209 .ttbr = DART_T8020_TTBR,
1210 .ttbr_valid = DART_T8020_TTBR_VALID,
1211 .ttbr_addr_field_shift = DART_T8020_TTBR_ADDR_FIELD_SHIFT,
1212 .ttbr_shift = DART_T8020_TTBR_SHIFT,
1213 .ttbr_count = 4,
1214 };
1215
1216 static const struct apple_dart_hw apple_dart_hw_t8110 = {
1217 .type = DART_T8110,
1218 .irq_handler = apple_dart_t8110_irq,
1219 .invalidate_tlb = apple_dart_t8110_hw_invalidate_tlb,
1220 .fmt = APPLE_DART2,
1221 .max_sid_count = 256,
1222
1223 .enable_streams = DART_T8110_ENABLE_STREAMS,
1224 .lock = DART_T8110_PROTECT,
1225 .lock_bit = DART_T8110_PROTECT_TTBR_TCR,
1226
1227 .error = DART_T8110_ERROR,
1228
1229 .tcr = DART_T8110_TCR,
1230 .tcr_enabled = DART_T8110_TCR_TRANSLATE_ENABLE,
1231 .tcr_disabled = 0,
1232 .tcr_bypass = DART_T8110_TCR_BYPASS_DAPF | DART_T8110_TCR_BYPASS_DART,
1233
1234 .ttbr = DART_T8110_TTBR,
1235 .ttbr_valid = DART_T8110_TTBR_VALID,
1236 .ttbr_addr_field_shift = DART_T8110_TTBR_ADDR_FIELD_SHIFT,
1237 .ttbr_shift = DART_T8110_TTBR_SHIFT,
1238 .ttbr_count = 1,
1239 };
1240
apple_dart_suspend(struct device * dev)1241 static __maybe_unused int apple_dart_suspend(struct device *dev)
1242 {
1243 struct apple_dart *dart = dev_get_drvdata(dev);
1244 unsigned int sid, idx;
1245
1246 for (sid = 0; sid < dart->num_streams; sid++) {
1247 dart->save_tcr[sid] = readl_relaxed(dart->regs + DART_TCR(dart, sid));
1248 for (idx = 0; idx < dart->hw->ttbr_count; idx++)
1249 dart->save_ttbr[sid][idx] =
1250 readl(dart->regs + DART_TTBR(dart, sid, idx));
1251 }
1252
1253 return 0;
1254 }
1255
apple_dart_resume(struct device * dev)1256 static __maybe_unused int apple_dart_resume(struct device *dev)
1257 {
1258 struct apple_dart *dart = dev_get_drvdata(dev);
1259 unsigned int sid, idx;
1260 int ret;
1261
1262 ret = apple_dart_hw_reset(dart);
1263 if (ret) {
1264 dev_err(dev, "Failed to reset DART on resume\n");
1265 return ret;
1266 }
1267
1268 for (sid = 0; sid < dart->num_streams; sid++) {
1269 for (idx = 0; idx < dart->hw->ttbr_count; idx++)
1270 writel(dart->save_ttbr[sid][idx],
1271 dart->regs + DART_TTBR(dart, sid, idx));
1272 writel(dart->save_tcr[sid], dart->regs + DART_TCR(dart, sid));
1273 }
1274
1275 return 0;
1276 }
1277
1278 static DEFINE_SIMPLE_DEV_PM_OPS(apple_dart_pm_ops, apple_dart_suspend, apple_dart_resume);
1279
1280 static const struct of_device_id apple_dart_of_match[] = {
1281 { .compatible = "apple,t8103-dart", .data = &apple_dart_hw_t8103 },
1282 { .compatible = "apple,t8110-dart", .data = &apple_dart_hw_t8110 },
1283 { .compatible = "apple,t6000-dart", .data = &apple_dart_hw_t6000 },
1284 {},
1285 };
1286 MODULE_DEVICE_TABLE(of, apple_dart_of_match);
1287
1288 static struct platform_driver apple_dart_driver = {
1289 .driver = {
1290 .name = "apple-dart",
1291 .of_match_table = apple_dart_of_match,
1292 .suppress_bind_attrs = true,
1293 .pm = pm_sleep_ptr(&apple_dart_pm_ops),
1294 },
1295 .probe = apple_dart_probe,
1296 .remove_new = apple_dart_remove,
1297 };
1298
1299 module_platform_driver(apple_dart_driver);
1300
1301 MODULE_DESCRIPTION("IOMMU API for Apple's DART");
1302 MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>");
1303 MODULE_LICENSE("GPL v2");
1304