1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/netdevice.h>
6 #include <linux/if_ether.h>
7 #include <linux/if_vlan.h>
8 #include <linux/iopoll.h>
9 #include <linux/pci.h>
10
11 #include "wx_type.h"
12 #include "wx_lib.h"
13 #include "wx_hw.h"
14
wx_intr_disable(struct wx * wx,u64 qmask)15 static void wx_intr_disable(struct wx *wx, u64 qmask)
16 {
17 u32 mask;
18
19 mask = (qmask & U32_MAX);
20 if (mask)
21 wr32(wx, WX_PX_IMS(0), mask);
22
23 if (wx->mac.type == wx_mac_sp) {
24 mask = (qmask >> 32);
25 if (mask)
26 wr32(wx, WX_PX_IMS(1), mask);
27 }
28 }
29
wx_intr_enable(struct wx * wx,u64 qmask)30 void wx_intr_enable(struct wx *wx, u64 qmask)
31 {
32 u32 mask;
33
34 mask = (qmask & U32_MAX);
35 if (mask)
36 wr32(wx, WX_PX_IMC(0), mask);
37 if (wx->mac.type == wx_mac_sp) {
38 mask = (qmask >> 32);
39 if (mask)
40 wr32(wx, WX_PX_IMC(1), mask);
41 }
42 }
43 EXPORT_SYMBOL(wx_intr_enable);
44
45 /**
46 * wx_irq_disable - Mask off interrupt generation on the NIC
47 * @wx: board private structure
48 **/
wx_irq_disable(struct wx * wx)49 void wx_irq_disable(struct wx *wx)
50 {
51 struct pci_dev *pdev = wx->pdev;
52
53 wr32(wx, WX_PX_MISC_IEN, 0);
54 wx_intr_disable(wx, WX_INTR_ALL);
55
56 if (pdev->msix_enabled) {
57 int vector;
58
59 for (vector = 0; vector < wx->num_q_vectors; vector++)
60 synchronize_irq(wx->msix_entries[vector].vector);
61
62 synchronize_irq(wx->msix_entries[vector].vector);
63 } else {
64 synchronize_irq(pdev->irq);
65 }
66 }
67 EXPORT_SYMBOL(wx_irq_disable);
68
69 /* cmd_addr is used for some special command:
70 * 1. to be sector address, when implemented erase sector command
71 * 2. to be flash address when implemented read, write flash address
72 */
wx_fmgr_cmd_op(struct wx * wx,u32 cmd,u32 cmd_addr)73 static int wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr)
74 {
75 u32 cmd_val = 0, val = 0;
76
77 cmd_val = WX_SPI_CMD_CMD(cmd) |
78 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) |
79 cmd_addr;
80 wr32(wx, WX_SPI_CMD, cmd_val);
81
82 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000,
83 false, wx, WX_SPI_STATUS);
84 }
85
wx_flash_read_dword(struct wx * wx,u32 addr,u32 * data)86 static int wx_flash_read_dword(struct wx *wx, u32 addr, u32 *data)
87 {
88 int ret = 0;
89
90 ret = wx_fmgr_cmd_op(wx, WX_SPI_CMD_READ_DWORD, addr);
91 if (ret < 0)
92 return ret;
93
94 *data = rd32(wx, WX_SPI_DATA);
95
96 return ret;
97 }
98
wx_check_flash_load(struct wx * hw,u32 check_bit)99 int wx_check_flash_load(struct wx *hw, u32 check_bit)
100 {
101 u32 reg = 0;
102 int err = 0;
103
104 /* if there's flash existing */
105 if (!(rd32(hw, WX_SPI_STATUS) &
106 WX_SPI_STATUS_FLASH_BYPASS)) {
107 /* wait hw load flash done */
108 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000,
109 false, hw, WX_SPI_ILDR_STATUS);
110 if (err < 0)
111 wx_err(hw, "Check flash load timeout.\n");
112 }
113
114 return err;
115 }
116 EXPORT_SYMBOL(wx_check_flash_load);
117
wx_control_hw(struct wx * wx,bool drv)118 void wx_control_hw(struct wx *wx, bool drv)
119 {
120 /* True : Let firmware know the driver has taken over
121 * False : Let firmware take over control of hw
122 */
123 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD,
124 drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0);
125 }
126 EXPORT_SYMBOL(wx_control_hw);
127
128 /**
129 * wx_mng_present - returns 0 when management capability is present
130 * @wx: pointer to hardware structure
131 */
wx_mng_present(struct wx * wx)132 int wx_mng_present(struct wx *wx)
133 {
134 u32 fwsm;
135
136 fwsm = rd32(wx, WX_MIS_ST);
137 if (fwsm & WX_MIS_ST_MNG_INIT_DN)
138 return 0;
139 else
140 return -EACCES;
141 }
142 EXPORT_SYMBOL(wx_mng_present);
143
144 /* Software lock to be held while software semaphore is being accessed. */
145 static DEFINE_MUTEX(wx_sw_sync_lock);
146
147 /**
148 * wx_release_sw_sync - Release SW semaphore
149 * @wx: pointer to hardware structure
150 * @mask: Mask to specify which semaphore to release
151 *
152 * Releases the SW semaphore for the specified
153 * function (CSR, PHY0, PHY1, EEPROM, Flash)
154 **/
wx_release_sw_sync(struct wx * wx,u32 mask)155 static void wx_release_sw_sync(struct wx *wx, u32 mask)
156 {
157 mutex_lock(&wx_sw_sync_lock);
158 wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0);
159 mutex_unlock(&wx_sw_sync_lock);
160 }
161
162 /**
163 * wx_acquire_sw_sync - Acquire SW semaphore
164 * @wx: pointer to hardware structure
165 * @mask: Mask to specify which semaphore to acquire
166 *
167 * Acquires the SW semaphore for the specified
168 * function (CSR, PHY0, PHY1, EEPROM, Flash)
169 **/
wx_acquire_sw_sync(struct wx * wx,u32 mask)170 static int wx_acquire_sw_sync(struct wx *wx, u32 mask)
171 {
172 u32 sem = 0;
173 int ret = 0;
174
175 mutex_lock(&wx_sw_sync_lock);
176 ret = read_poll_timeout(rd32, sem, !(sem & mask),
177 5000, 2000000, false, wx, WX_MNG_SWFW_SYNC);
178 if (!ret) {
179 sem |= mask;
180 wr32(wx, WX_MNG_SWFW_SYNC, sem);
181 } else {
182 wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem);
183 }
184 mutex_unlock(&wx_sw_sync_lock);
185
186 return ret;
187 }
188
189 /**
190 * wx_host_interface_command - Issue command to manageability block
191 * @wx: pointer to the HW structure
192 * @buffer: contains the command to write and where the return status will
193 * be placed
194 * @length: length of buffer, must be multiple of 4 bytes
195 * @timeout: time in ms to wait for command completion
196 * @return_data: read and return data from the buffer (true) or not (false)
197 * Needed because FW structures are big endian and decoding of
198 * these fields can be 8 bit or 16 bit based on command. Decoding
199 * is not easily understood without making a table of commands.
200 * So we will leave this up to the caller to read back the data
201 * in these cases.
202 **/
wx_host_interface_command(struct wx * wx,u32 * buffer,u32 length,u32 timeout,bool return_data)203 int wx_host_interface_command(struct wx *wx, u32 *buffer,
204 u32 length, u32 timeout, bool return_data)
205 {
206 u32 hdr_size = sizeof(struct wx_hic_hdr);
207 u32 hicr, i, bi, buf[64] = {};
208 int status = 0;
209 u32 dword_len;
210 u16 buf_len;
211
212 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) {
213 wx_err(wx, "Buffer length failure buffersize=%d.\n", length);
214 return -EINVAL;
215 }
216
217 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB);
218 if (status != 0)
219 return status;
220
221 /* Calculate length in DWORDs. We must be DWORD aligned */
222 if ((length % (sizeof(u32))) != 0) {
223 wx_err(wx, "Buffer length failure, not aligned to dword");
224 status = -EINVAL;
225 goto rel_out;
226 }
227
228 dword_len = length >> 2;
229
230 /* The device driver writes the relevant command block
231 * into the ram area.
232 */
233 for (i = 0; i < dword_len; i++) {
234 wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i]));
235 /* write flush */
236 buf[i] = rd32a(wx, WX_MNG_MBOX, i);
237 }
238 /* Setting this bit tells the ARC that a new command is pending. */
239 wr32m(wx, WX_MNG_MBOX_CTL,
240 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY);
241
242 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000,
243 timeout * 1000, false, wx, WX_MNG_MBOX_CTL);
244
245 /* Check command completion */
246 if (status) {
247 wx_dbg(wx, "Command has failed with no status valid.\n");
248
249 buf[0] = rd32(wx, WX_MNG_MBOX);
250 if ((buffer[0] & 0xff) != (~buf[0] >> 24)) {
251 status = -EINVAL;
252 goto rel_out;
253 }
254 if ((buf[0] & 0xff0000) >> 16 == 0x80) {
255 wx_dbg(wx, "It's unknown cmd.\n");
256 status = -EINVAL;
257 goto rel_out;
258 }
259
260 wx_dbg(wx, "write value:\n");
261 for (i = 0; i < dword_len; i++)
262 wx_dbg(wx, "%x ", buffer[i]);
263 wx_dbg(wx, "read value:\n");
264 for (i = 0; i < dword_len; i++)
265 wx_dbg(wx, "%x ", buf[i]);
266 }
267
268 if (!return_data)
269 goto rel_out;
270
271 /* Calculate length in DWORDs */
272 dword_len = hdr_size >> 2;
273
274 /* first pull in the header so we know the buffer length */
275 for (bi = 0; bi < dword_len; bi++) {
276 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi);
277 le32_to_cpus(&buffer[bi]);
278 }
279
280 /* If there is any thing in data position pull it in */
281 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len;
282 if (buf_len == 0)
283 goto rel_out;
284
285 if (length < buf_len + hdr_size) {
286 wx_err(wx, "Buffer not large enough for reply message.\n");
287 status = -EFAULT;
288 goto rel_out;
289 }
290
291 /* Calculate length in DWORDs, add 3 for odd lengths */
292 dword_len = (buf_len + 3) >> 2;
293
294 /* Pull in the rest of the buffer (bi is where we left off) */
295 for (; bi <= dword_len; bi++) {
296 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi);
297 le32_to_cpus(&buffer[bi]);
298 }
299
300 rel_out:
301 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB);
302 return status;
303 }
304 EXPORT_SYMBOL(wx_host_interface_command);
305
306 /**
307 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd
308 * assuming that the semaphore is already obtained.
309 * @wx: pointer to hardware structure
310 * @offset: offset of word in the EEPROM to read
311 * @data: word read from the EEPROM
312 *
313 * Reads a 16 bit word from the EEPROM using the hostif.
314 **/
wx_read_ee_hostif_data(struct wx * wx,u16 offset,u16 * data)315 static int wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data)
316 {
317 struct wx_hic_read_shadow_ram buffer;
318 int status;
319
320 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
321 buffer.hdr.req.buf_lenh = 0;
322 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
323 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
324
325 /* convert offset from words to bytes */
326 buffer.address = (__force u32)cpu_to_be32(offset * 2);
327 /* one word */
328 buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
329
330 status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer),
331 WX_HI_COMMAND_TIMEOUT, false);
332
333 if (status != 0)
334 return status;
335
336 *data = (u16)rd32a(wx, WX_MNG_MBOX, FW_NVM_DATA_OFFSET);
337
338 return status;
339 }
340
341 /**
342 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd
343 * @wx: pointer to hardware structure
344 * @offset: offset of word in the EEPROM to read
345 * @data: word read from the EEPROM
346 *
347 * Reads a 16 bit word from the EEPROM using the hostif.
348 **/
wx_read_ee_hostif(struct wx * wx,u16 offset,u16 * data)349 int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data)
350 {
351 int status = 0;
352
353 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
354 if (status == 0) {
355 status = wx_read_ee_hostif_data(wx, offset, data);
356 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
357 }
358
359 return status;
360 }
361 EXPORT_SYMBOL(wx_read_ee_hostif);
362
363 /**
364 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif
365 * @wx: pointer to hardware structure
366 * @offset: offset of word in the EEPROM to read
367 * @words: number of words
368 * @data: word(s) read from the EEPROM
369 *
370 * Reads a 16 bit word(s) from the EEPROM using the hostif.
371 **/
wx_read_ee_hostif_buffer(struct wx * wx,u16 offset,u16 words,u16 * data)372 int wx_read_ee_hostif_buffer(struct wx *wx,
373 u16 offset, u16 words, u16 *data)
374 {
375 struct wx_hic_read_shadow_ram buffer;
376 u32 current_word = 0;
377 u16 words_to_read;
378 u32 value = 0;
379 int status;
380 u32 i;
381
382 /* Take semaphore for the entire operation. */
383 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
384 if (status != 0)
385 return status;
386
387 while (words) {
388 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
389 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
390 else
391 words_to_read = words;
392
393 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
394 buffer.hdr.req.buf_lenh = 0;
395 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
396 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
397
398 /* convert offset from words to bytes */
399 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2);
400 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
401
402 status = wx_host_interface_command(wx, (u32 *)&buffer,
403 sizeof(buffer),
404 WX_HI_COMMAND_TIMEOUT,
405 false);
406
407 if (status != 0) {
408 wx_err(wx, "Host interface command failed\n");
409 goto out;
410 }
411
412 for (i = 0; i < words_to_read; i++) {
413 u32 reg = WX_MNG_MBOX + (FW_NVM_DATA_OFFSET << 2) + 2 * i;
414
415 value = rd32(wx, reg);
416 data[current_word] = (u16)(value & 0xffff);
417 current_word++;
418 i++;
419 if (i < words_to_read) {
420 value >>= 16;
421 data[current_word] = (u16)(value & 0xffff);
422 current_word++;
423 }
424 }
425 words -= words_to_read;
426 }
427
428 out:
429 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
430 return status;
431 }
432 EXPORT_SYMBOL(wx_read_ee_hostif_buffer);
433
434 /**
435 * wx_init_eeprom_params - Initialize EEPROM params
436 * @wx: pointer to hardware structure
437 *
438 * Initializes the EEPROM parameters wx_eeprom_info within the
439 * wx_hw struct in order to set up EEPROM access.
440 **/
wx_init_eeprom_params(struct wx * wx)441 void wx_init_eeprom_params(struct wx *wx)
442 {
443 struct wx_eeprom_info *eeprom = &wx->eeprom;
444 u16 eeprom_size;
445 u16 data = 0x80;
446
447 if (eeprom->type == wx_eeprom_uninitialized) {
448 eeprom->semaphore_delay = 10;
449 eeprom->type = wx_eeprom_none;
450
451 if (!(rd32(wx, WX_SPI_STATUS) &
452 WX_SPI_STATUS_FLASH_BYPASS)) {
453 eeprom->type = wx_flash;
454
455 eeprom_size = 4096;
456 eeprom->word_size = eeprom_size >> 1;
457
458 wx_dbg(wx, "Eeprom params: type = %d, size = %d\n",
459 eeprom->type, eeprom->word_size);
460 }
461 }
462
463 if (wx->mac.type == wx_mac_sp) {
464 if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) {
465 wx_err(wx, "NVM Read Error\n");
466 return;
467 }
468 data = data >> 1;
469 }
470
471 eeprom->sw_region_offset = data;
472 }
473 EXPORT_SYMBOL(wx_init_eeprom_params);
474
475 /**
476 * wx_get_mac_addr - Generic get MAC address
477 * @wx: pointer to hardware structure
478 * @mac_addr: Adapter MAC address
479 *
480 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
481 * A reset of the adapter must be performed prior to calling this function
482 * in order for the MAC address to have been loaded from the EEPROM into RAR0
483 **/
wx_get_mac_addr(struct wx * wx,u8 * mac_addr)484 void wx_get_mac_addr(struct wx *wx, u8 *mac_addr)
485 {
486 u32 rar_high;
487 u32 rar_low;
488 u16 i;
489
490 wr32(wx, WX_PSR_MAC_SWC_IDX, 0);
491 rar_high = rd32(wx, WX_PSR_MAC_SWC_AD_H);
492 rar_low = rd32(wx, WX_PSR_MAC_SWC_AD_L);
493
494 for (i = 0; i < 2; i++)
495 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
496
497 for (i = 0; i < 4; i++)
498 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
499 }
500 EXPORT_SYMBOL(wx_get_mac_addr);
501
502 /**
503 * wx_set_rar - Set Rx address register
504 * @wx: pointer to hardware structure
505 * @index: Receive address register to write
506 * @addr: Address to put into receive address register
507 * @pools: VMDq "set" or "pool" index
508 * @enable_addr: set flag that address is active
509 *
510 * Puts an ethernet address into a receive address register.
511 **/
wx_set_rar(struct wx * wx,u32 index,u8 * addr,u64 pools,u32 enable_addr)512 static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools,
513 u32 enable_addr)
514 {
515 u32 rar_entries = wx->mac.num_rar_entries;
516 u32 rar_low, rar_high;
517
518 /* Make sure we are using a valid rar index range */
519 if (index >= rar_entries) {
520 wx_err(wx, "RAR index %d is out of range.\n", index);
521 return -EINVAL;
522 }
523
524 /* select the MAC address */
525 wr32(wx, WX_PSR_MAC_SWC_IDX, index);
526
527 /* setup VMDq pool mapping */
528 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF);
529 if (wx->mac.type == wx_mac_sp)
530 wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32);
531
532 /* HW expects these in little endian so we reverse the byte
533 * order from network order (big endian) to little endian
534 *
535 * Some parts put the VMDq setting in the extra RAH bits,
536 * so save everything except the lower 16 bits that hold part
537 * of the address and the address valid bit.
538 */
539 rar_low = ((u32)addr[5] |
540 ((u32)addr[4] << 8) |
541 ((u32)addr[3] << 16) |
542 ((u32)addr[2] << 24));
543 rar_high = ((u32)addr[1] |
544 ((u32)addr[0] << 8));
545 if (enable_addr != 0)
546 rar_high |= WX_PSR_MAC_SWC_AD_H_AV;
547
548 wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low);
549 wr32m(wx, WX_PSR_MAC_SWC_AD_H,
550 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) |
551 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) |
552 WX_PSR_MAC_SWC_AD_H_AV),
553 rar_high);
554
555 return 0;
556 }
557
558 /**
559 * wx_clear_rar - Remove Rx address register
560 * @wx: pointer to hardware structure
561 * @index: Receive address register to write
562 *
563 * Clears an ethernet address from a receive address register.
564 **/
wx_clear_rar(struct wx * wx,u32 index)565 static int wx_clear_rar(struct wx *wx, u32 index)
566 {
567 u32 rar_entries = wx->mac.num_rar_entries;
568
569 /* Make sure we are using a valid rar index range */
570 if (index >= rar_entries) {
571 wx_err(wx, "RAR index %d is out of range.\n", index);
572 return -EINVAL;
573 }
574
575 /* Some parts put the VMDq setting in the extra RAH bits,
576 * so save everything except the lower 16 bits that hold part
577 * of the address and the address valid bit.
578 */
579 wr32(wx, WX_PSR_MAC_SWC_IDX, index);
580
581 wr32(wx, WX_PSR_MAC_SWC_VM_L, 0);
582 wr32(wx, WX_PSR_MAC_SWC_VM_H, 0);
583
584 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0);
585 wr32m(wx, WX_PSR_MAC_SWC_AD_H,
586 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) |
587 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) |
588 WX_PSR_MAC_SWC_AD_H_AV),
589 0);
590
591 return 0;
592 }
593
594 /**
595 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address
596 * @wx: pointer to hardware struct
597 * @rar: receive address register index to disassociate
598 * @vmdq: VMDq pool index to remove from the rar
599 **/
wx_clear_vmdq(struct wx * wx,u32 rar,u32 __maybe_unused vmdq)600 static int wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq)
601 {
602 u32 rar_entries = wx->mac.num_rar_entries;
603 u32 mpsar_lo, mpsar_hi;
604
605 /* Make sure we are using a valid rar index range */
606 if (rar >= rar_entries) {
607 wx_err(wx, "RAR index %d is out of range.\n", rar);
608 return -EINVAL;
609 }
610
611 wr32(wx, WX_PSR_MAC_SWC_IDX, rar);
612 mpsar_lo = rd32(wx, WX_PSR_MAC_SWC_VM_L);
613 mpsar_hi = rd32(wx, WX_PSR_MAC_SWC_VM_H);
614
615 if (!mpsar_lo && !mpsar_hi)
616 return 0;
617
618 /* was that the last pool using this rar? */
619 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
620 wx_clear_rar(wx, rar);
621
622 return 0;
623 }
624
625 /**
626 * wx_init_uta_tables - Initialize the Unicast Table Array
627 * @wx: pointer to hardware structure
628 **/
wx_init_uta_tables(struct wx * wx)629 static void wx_init_uta_tables(struct wx *wx)
630 {
631 int i;
632
633 wx_dbg(wx, " Clearing UTA\n");
634
635 for (i = 0; i < 128; i++)
636 wr32(wx, WX_PSR_UC_TBL(i), 0);
637 }
638
639 /**
640 * wx_init_rx_addrs - Initializes receive address filters.
641 * @wx: pointer to hardware structure
642 *
643 * Places the MAC address in receive address register 0 and clears the rest
644 * of the receive address registers. Clears the multicast table. Assumes
645 * the receiver is in reset when the routine is called.
646 **/
wx_init_rx_addrs(struct wx * wx)647 void wx_init_rx_addrs(struct wx *wx)
648 {
649 u32 rar_entries = wx->mac.num_rar_entries;
650 u32 psrctl;
651 int i;
652
653 /* If the current mac address is valid, assume it is a software override
654 * to the permanent address.
655 * Otherwise, use the permanent address from the eeprom.
656 */
657 if (!is_valid_ether_addr(wx->mac.addr)) {
658 /* Get the MAC address from the RAR0 for later reference */
659 wx_get_mac_addr(wx, wx->mac.addr);
660 wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr);
661 } else {
662 /* Setup the receive address. */
663 wx_dbg(wx, "Overriding MAC Address in RAR[0]\n");
664 wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr);
665
666 wx_set_rar(wx, 0, wx->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV);
667
668 if (wx->mac.type == wx_mac_sp) {
669 /* clear VMDq pool/queue selection for RAR 0 */
670 wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL);
671 }
672 }
673
674 /* Zero out the other receive addresses. */
675 wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1);
676 for (i = 1; i < rar_entries; i++) {
677 wr32(wx, WX_PSR_MAC_SWC_IDX, i);
678 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0);
679 wr32(wx, WX_PSR_MAC_SWC_AD_H, 0);
680 }
681
682 /* Clear the MTA */
683 wx->addr_ctrl.mta_in_use = 0;
684 psrctl = rd32(wx, WX_PSR_CTL);
685 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE);
686 psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT;
687 wr32(wx, WX_PSR_CTL, psrctl);
688 wx_dbg(wx, " Clearing MTA\n");
689 for (i = 0; i < wx->mac.mcft_size; i++)
690 wr32(wx, WX_PSR_MC_TBL(i), 0);
691
692 wx_init_uta_tables(wx);
693 }
694 EXPORT_SYMBOL(wx_init_rx_addrs);
695
wx_sync_mac_table(struct wx * wx)696 static void wx_sync_mac_table(struct wx *wx)
697 {
698 int i;
699
700 for (i = 0; i < wx->mac.num_rar_entries; i++) {
701 if (wx->mac_table[i].state & WX_MAC_STATE_MODIFIED) {
702 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) {
703 wx_set_rar(wx, i,
704 wx->mac_table[i].addr,
705 wx->mac_table[i].pools,
706 WX_PSR_MAC_SWC_AD_H_AV);
707 } else {
708 wx_clear_rar(wx, i);
709 }
710 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED);
711 }
712 }
713 }
714
715 /* this function destroys the first RAR entry */
wx_mac_set_default_filter(struct wx * wx,u8 * addr)716 void wx_mac_set_default_filter(struct wx *wx, u8 *addr)
717 {
718 memcpy(&wx->mac_table[0].addr, addr, ETH_ALEN);
719 wx->mac_table[0].pools = 1ULL;
720 wx->mac_table[0].state = (WX_MAC_STATE_DEFAULT | WX_MAC_STATE_IN_USE);
721 wx_set_rar(wx, 0, wx->mac_table[0].addr,
722 wx->mac_table[0].pools,
723 WX_PSR_MAC_SWC_AD_H_AV);
724 }
725 EXPORT_SYMBOL(wx_mac_set_default_filter);
726
wx_flush_sw_mac_table(struct wx * wx)727 void wx_flush_sw_mac_table(struct wx *wx)
728 {
729 u32 i;
730
731 for (i = 0; i < wx->mac.num_rar_entries; i++) {
732 if (!(wx->mac_table[i].state & WX_MAC_STATE_IN_USE))
733 continue;
734
735 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED;
736 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE;
737 memset(wx->mac_table[i].addr, 0, ETH_ALEN);
738 wx->mac_table[i].pools = 0;
739 }
740 wx_sync_mac_table(wx);
741 }
742 EXPORT_SYMBOL(wx_flush_sw_mac_table);
743
wx_add_mac_filter(struct wx * wx,u8 * addr,u16 pool)744 static int wx_add_mac_filter(struct wx *wx, u8 *addr, u16 pool)
745 {
746 u32 i;
747
748 if (is_zero_ether_addr(addr))
749 return -EINVAL;
750
751 for (i = 0; i < wx->mac.num_rar_entries; i++) {
752 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) {
753 if (ether_addr_equal(addr, wx->mac_table[i].addr)) {
754 if (wx->mac_table[i].pools != (1ULL << pool)) {
755 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN);
756 wx->mac_table[i].pools |= (1ULL << pool);
757 wx_sync_mac_table(wx);
758 return i;
759 }
760 }
761 }
762
763 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE)
764 continue;
765 wx->mac_table[i].state |= (WX_MAC_STATE_MODIFIED |
766 WX_MAC_STATE_IN_USE);
767 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN);
768 wx->mac_table[i].pools |= (1ULL << pool);
769 wx_sync_mac_table(wx);
770 return i;
771 }
772 return -ENOMEM;
773 }
774
wx_del_mac_filter(struct wx * wx,u8 * addr,u16 pool)775 static int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool)
776 {
777 u32 i;
778
779 if (is_zero_ether_addr(addr))
780 return -EINVAL;
781
782 /* search table for addr, if found, set to 0 and sync */
783 for (i = 0; i < wx->mac.num_rar_entries; i++) {
784 if (!ether_addr_equal(addr, wx->mac_table[i].addr))
785 continue;
786
787 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED;
788 wx->mac_table[i].pools &= ~(1ULL << pool);
789 if (!wx->mac_table[i].pools) {
790 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE;
791 memset(wx->mac_table[i].addr, 0, ETH_ALEN);
792 }
793 wx_sync_mac_table(wx);
794 return 0;
795 }
796 return -ENOMEM;
797 }
798
wx_available_rars(struct wx * wx)799 static int wx_available_rars(struct wx *wx)
800 {
801 u32 i, count = 0;
802
803 for (i = 0; i < wx->mac.num_rar_entries; i++) {
804 if (wx->mac_table[i].state == 0)
805 count++;
806 }
807
808 return count;
809 }
810
811 /**
812 * wx_write_uc_addr_list - write unicast addresses to RAR table
813 * @netdev: network interface device structure
814 * @pool: index for mac table
815 *
816 * Writes unicast address list to the RAR table.
817 * Returns: -ENOMEM on failure/insufficient address space
818 * 0 on no addresses written
819 * X on writing X addresses to the RAR table
820 **/
wx_write_uc_addr_list(struct net_device * netdev,int pool)821 static int wx_write_uc_addr_list(struct net_device *netdev, int pool)
822 {
823 struct wx *wx = netdev_priv(netdev);
824 int count = 0;
825
826 /* return ENOMEM indicating insufficient memory for addresses */
827 if (netdev_uc_count(netdev) > wx_available_rars(wx))
828 return -ENOMEM;
829
830 if (!netdev_uc_empty(netdev)) {
831 struct netdev_hw_addr *ha;
832
833 netdev_for_each_uc_addr(ha, netdev) {
834 wx_del_mac_filter(wx, ha->addr, pool);
835 wx_add_mac_filter(wx, ha->addr, pool);
836 count++;
837 }
838 }
839 return count;
840 }
841
842 /**
843 * wx_mta_vector - Determines bit-vector in multicast table to set
844 * @wx: pointer to private structure
845 * @mc_addr: the multicast address
846 *
847 * Extracts the 12 bits, from a multicast address, to determine which
848 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
849 * incoming rx multicast addresses, to determine the bit-vector to check in
850 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
851 * by the MO field of the MCSTCTRL. The MO field is set during initialization
852 * to mc_filter_type.
853 **/
wx_mta_vector(struct wx * wx,u8 * mc_addr)854 static u32 wx_mta_vector(struct wx *wx, u8 *mc_addr)
855 {
856 u32 vector = 0;
857
858 switch (wx->mac.mc_filter_type) {
859 case 0: /* use bits [47:36] of the address */
860 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
861 break;
862 case 1: /* use bits [46:35] of the address */
863 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
864 break;
865 case 2: /* use bits [45:34] of the address */
866 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
867 break;
868 case 3: /* use bits [43:32] of the address */
869 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
870 break;
871 default: /* Invalid mc_filter_type */
872 wx_err(wx, "MC filter type param set incorrectly\n");
873 break;
874 }
875
876 /* vector can only be 12-bits or boundary will be exceeded */
877 vector &= 0xFFF;
878 return vector;
879 }
880
881 /**
882 * wx_set_mta - Set bit-vector in multicast table
883 * @wx: pointer to private structure
884 * @mc_addr: Multicast address
885 *
886 * Sets the bit-vector in the multicast table.
887 **/
wx_set_mta(struct wx * wx,u8 * mc_addr)888 static void wx_set_mta(struct wx *wx, u8 *mc_addr)
889 {
890 u32 vector, vector_bit, vector_reg;
891
892 wx->addr_ctrl.mta_in_use++;
893
894 vector = wx_mta_vector(wx, mc_addr);
895 wx_dbg(wx, " bit-vector = 0x%03X\n", vector);
896
897 /* The MTA is a register array of 128 32-bit registers. It is treated
898 * like an array of 4096 bits. We want to set bit
899 * BitArray[vector_value]. So we figure out what register the bit is
900 * in, read it, OR in the new bit, then write back the new value. The
901 * register is determined by the upper 7 bits of the vector value and
902 * the bit within that register are determined by the lower 5 bits of
903 * the value.
904 */
905 vector_reg = (vector >> 5) & 0x7F;
906 vector_bit = vector & 0x1F;
907 wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
908 }
909
910 /**
911 * wx_update_mc_addr_list - Updates MAC list of multicast addresses
912 * @wx: pointer to private structure
913 * @netdev: pointer to net device structure
914 *
915 * The given list replaces any existing list. Clears the MC addrs from receive
916 * address registers and the multicast table. Uses unused receive address
917 * registers for the first multicast addresses, and hashes the rest into the
918 * multicast table.
919 **/
wx_update_mc_addr_list(struct wx * wx,struct net_device * netdev)920 static void wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev)
921 {
922 struct netdev_hw_addr *ha;
923 u32 i, psrctl;
924
925 /* Set the new number of MC addresses that we are being requested to
926 * use.
927 */
928 wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
929 wx->addr_ctrl.mta_in_use = 0;
930
931 /* Clear mta_shadow */
932 wx_dbg(wx, " Clearing MTA\n");
933 memset(&wx->mac.mta_shadow, 0, sizeof(wx->mac.mta_shadow));
934
935 /* Update mta_shadow */
936 netdev_for_each_mc_addr(ha, netdev) {
937 wx_dbg(wx, " Adding the multicast addresses:\n");
938 wx_set_mta(wx, ha->addr);
939 }
940
941 /* Enable mta */
942 for (i = 0; i < wx->mac.mcft_size; i++)
943 wr32a(wx, WX_PSR_MC_TBL(0), i,
944 wx->mac.mta_shadow[i]);
945
946 if (wx->addr_ctrl.mta_in_use > 0) {
947 psrctl = rd32(wx, WX_PSR_CTL);
948 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE);
949 psrctl |= WX_PSR_CTL_MFE |
950 (wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT);
951 wr32(wx, WX_PSR_CTL, psrctl);
952 }
953
954 wx_dbg(wx, "Update mc addr list Complete\n");
955 }
956
957 /**
958 * wx_write_mc_addr_list - write multicast addresses to MTA
959 * @netdev: network interface device structure
960 *
961 * Writes multicast address list to the MTA hash table.
962 * Returns: 0 on no addresses written
963 * X on writing X addresses to MTA
964 **/
wx_write_mc_addr_list(struct net_device * netdev)965 static int wx_write_mc_addr_list(struct net_device *netdev)
966 {
967 struct wx *wx = netdev_priv(netdev);
968
969 if (!netif_running(netdev))
970 return 0;
971
972 wx_update_mc_addr_list(wx, netdev);
973
974 return netdev_mc_count(netdev);
975 }
976
977 /**
978 * wx_set_mac - Change the Ethernet Address of the NIC
979 * @netdev: network interface device structure
980 * @p: pointer to an address structure
981 *
982 * Returns 0 on success, negative on failure
983 **/
wx_set_mac(struct net_device * netdev,void * p)984 int wx_set_mac(struct net_device *netdev, void *p)
985 {
986 struct wx *wx = netdev_priv(netdev);
987 struct sockaddr *addr = p;
988 int retval;
989
990 retval = eth_prepare_mac_addr_change(netdev, addr);
991 if (retval)
992 return retval;
993
994 wx_del_mac_filter(wx, wx->mac.addr, 0);
995 eth_hw_addr_set(netdev, addr->sa_data);
996 memcpy(wx->mac.addr, addr->sa_data, netdev->addr_len);
997
998 wx_mac_set_default_filter(wx, wx->mac.addr);
999
1000 return 0;
1001 }
1002 EXPORT_SYMBOL(wx_set_mac);
1003
wx_disable_rx(struct wx * wx)1004 void wx_disable_rx(struct wx *wx)
1005 {
1006 u32 pfdtxgswc;
1007 u32 rxctrl;
1008
1009 rxctrl = rd32(wx, WX_RDB_PB_CTL);
1010 if (rxctrl & WX_RDB_PB_CTL_RXEN) {
1011 pfdtxgswc = rd32(wx, WX_PSR_CTL);
1012 if (pfdtxgswc & WX_PSR_CTL_SW_EN) {
1013 pfdtxgswc &= ~WX_PSR_CTL_SW_EN;
1014 wr32(wx, WX_PSR_CTL, pfdtxgswc);
1015 wx->mac.set_lben = true;
1016 } else {
1017 wx->mac.set_lben = false;
1018 }
1019 rxctrl &= ~WX_RDB_PB_CTL_RXEN;
1020 wr32(wx, WX_RDB_PB_CTL, rxctrl);
1021
1022 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) ||
1023 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) {
1024 /* disable mac receiver */
1025 wr32m(wx, WX_MAC_RX_CFG,
1026 WX_MAC_RX_CFG_RE, 0);
1027 }
1028 }
1029 }
1030 EXPORT_SYMBOL(wx_disable_rx);
1031
wx_enable_rx(struct wx * wx)1032 static void wx_enable_rx(struct wx *wx)
1033 {
1034 u32 psrctl;
1035
1036 /* enable mac receiver */
1037 wr32m(wx, WX_MAC_RX_CFG,
1038 WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
1039
1040 wr32m(wx, WX_RDB_PB_CTL,
1041 WX_RDB_PB_CTL_RXEN, WX_RDB_PB_CTL_RXEN);
1042
1043 if (wx->mac.set_lben) {
1044 psrctl = rd32(wx, WX_PSR_CTL);
1045 psrctl |= WX_PSR_CTL_SW_EN;
1046 wr32(wx, WX_PSR_CTL, psrctl);
1047 wx->mac.set_lben = false;
1048 }
1049 }
1050
1051 /**
1052 * wx_set_rxpba - Initialize Rx packet buffer
1053 * @wx: pointer to private structure
1054 **/
wx_set_rxpba(struct wx * wx)1055 static void wx_set_rxpba(struct wx *wx)
1056 {
1057 u32 rxpktsize, txpktsize, txpbthresh;
1058
1059 rxpktsize = wx->mac.rx_pb_size << WX_RDB_PB_SZ_SHIFT;
1060 wr32(wx, WX_RDB_PB_SZ(0), rxpktsize);
1061
1062 /* Only support an equally distributed Tx packet buffer strategy. */
1063 txpktsize = wx->mac.tx_pb_size;
1064 txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX;
1065 wr32(wx, WX_TDB_PB_SZ(0), txpktsize);
1066 wr32(wx, WX_TDM_PB_THRE(0), txpbthresh);
1067 }
1068
wx_configure_port(struct wx * wx)1069 static void wx_configure_port(struct wx *wx)
1070 {
1071 u32 value, i;
1072
1073 value = WX_CFG_PORT_CTL_D_VLAN | WX_CFG_PORT_CTL_QINQ;
1074 wr32m(wx, WX_CFG_PORT_CTL,
1075 WX_CFG_PORT_CTL_D_VLAN |
1076 WX_CFG_PORT_CTL_QINQ,
1077 value);
1078
1079 wr32(wx, WX_CFG_TAG_TPID(0),
1080 ETH_P_8021Q | ETH_P_8021AD << 16);
1081 wx->tpid[0] = ETH_P_8021Q;
1082 wx->tpid[1] = ETH_P_8021AD;
1083 for (i = 1; i < 4; i++)
1084 wr32(wx, WX_CFG_TAG_TPID(i),
1085 ETH_P_8021Q | ETH_P_8021Q << 16);
1086 for (i = 2; i < 8; i++)
1087 wx->tpid[i] = ETH_P_8021Q;
1088 }
1089
1090 /**
1091 * wx_disable_sec_rx_path - Stops the receive data path
1092 * @wx: pointer to private structure
1093 *
1094 * Stops the receive data path and waits for the HW to internally empty
1095 * the Rx security block
1096 **/
wx_disable_sec_rx_path(struct wx * wx)1097 static int wx_disable_sec_rx_path(struct wx *wx)
1098 {
1099 u32 secrx;
1100
1101 wr32m(wx, WX_RSC_CTL,
1102 WX_RSC_CTL_RX_DIS, WX_RSC_CTL_RX_DIS);
1103
1104 return read_poll_timeout(rd32, secrx, secrx & WX_RSC_ST_RSEC_RDY,
1105 1000, 40000, false, wx, WX_RSC_ST);
1106 }
1107
1108 /**
1109 * wx_enable_sec_rx_path - Enables the receive data path
1110 * @wx: pointer to private structure
1111 *
1112 * Enables the receive data path.
1113 **/
wx_enable_sec_rx_path(struct wx * wx)1114 static void wx_enable_sec_rx_path(struct wx *wx)
1115 {
1116 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_RX_DIS, 0);
1117 WX_WRITE_FLUSH(wx);
1118 }
1119
wx_vlan_strip_control(struct wx * wx,bool enable)1120 static void wx_vlan_strip_control(struct wx *wx, bool enable)
1121 {
1122 int i, j;
1123
1124 for (i = 0; i < wx->num_rx_queues; i++) {
1125 struct wx_ring *ring = wx->rx_ring[i];
1126
1127 j = ring->reg_idx;
1128 wr32m(wx, WX_PX_RR_CFG(j), WX_PX_RR_CFG_VLAN,
1129 enable ? WX_PX_RR_CFG_VLAN : 0);
1130 }
1131 }
1132
wx_set_rx_mode(struct net_device * netdev)1133 void wx_set_rx_mode(struct net_device *netdev)
1134 {
1135 struct wx *wx = netdev_priv(netdev);
1136 netdev_features_t features;
1137 u32 fctrl, vmolr, vlnctrl;
1138 int count;
1139
1140 features = netdev->features;
1141
1142 /* Check for Promiscuous and All Multicast modes */
1143 fctrl = rd32(wx, WX_PSR_CTL);
1144 fctrl &= ~(WX_PSR_CTL_UPE | WX_PSR_CTL_MPE);
1145 vmolr = rd32(wx, WX_PSR_VM_L2CTL(0));
1146 vmolr &= ~(WX_PSR_VM_L2CTL_UPE |
1147 WX_PSR_VM_L2CTL_MPE |
1148 WX_PSR_VM_L2CTL_ROPE |
1149 WX_PSR_VM_L2CTL_ROMPE);
1150 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL);
1151 vlnctrl &= ~(WX_PSR_VLAN_CTL_VFE | WX_PSR_VLAN_CTL_CFIEN);
1152
1153 /* set all bits that we expect to always be set */
1154 fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE;
1155 vmolr |= WX_PSR_VM_L2CTL_BAM |
1156 WX_PSR_VM_L2CTL_AUPE |
1157 WX_PSR_VM_L2CTL_VACC;
1158 vlnctrl |= WX_PSR_VLAN_CTL_VFE;
1159
1160 wx->addr_ctrl.user_set_promisc = false;
1161 if (netdev->flags & IFF_PROMISC) {
1162 wx->addr_ctrl.user_set_promisc = true;
1163 fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE;
1164 /* pf don't want packets routing to vf, so clear UPE */
1165 vmolr |= WX_PSR_VM_L2CTL_MPE;
1166 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE;
1167 }
1168
1169 if (netdev->flags & IFF_ALLMULTI) {
1170 fctrl |= WX_PSR_CTL_MPE;
1171 vmolr |= WX_PSR_VM_L2CTL_MPE;
1172 }
1173
1174 if (netdev->features & NETIF_F_RXALL) {
1175 vmolr |= (WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_MPE);
1176 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE;
1177 /* receive bad packets */
1178 wr32m(wx, WX_RSC_CTL,
1179 WX_RSC_CTL_SAVE_MAC_ERR,
1180 WX_RSC_CTL_SAVE_MAC_ERR);
1181 } else {
1182 vmolr |= WX_PSR_VM_L2CTL_ROPE | WX_PSR_VM_L2CTL_ROMPE;
1183 }
1184
1185 /* Write addresses to available RAR registers, if there is not
1186 * sufficient space to store all the addresses then enable
1187 * unicast promiscuous mode
1188 */
1189 count = wx_write_uc_addr_list(netdev, 0);
1190 if (count < 0) {
1191 vmolr &= ~WX_PSR_VM_L2CTL_ROPE;
1192 vmolr |= WX_PSR_VM_L2CTL_UPE;
1193 }
1194
1195 /* Write addresses to the MTA, if the attempt fails
1196 * then we should just turn on promiscuous mode so
1197 * that we can at least receive multicast traffic
1198 */
1199 count = wx_write_mc_addr_list(netdev);
1200 if (count < 0) {
1201 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE;
1202 vmolr |= WX_PSR_VM_L2CTL_MPE;
1203 }
1204
1205 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl);
1206 wr32(wx, WX_PSR_CTL, fctrl);
1207 wr32(wx, WX_PSR_VM_L2CTL(0), vmolr);
1208
1209 if ((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1210 (features & NETIF_F_HW_VLAN_STAG_RX))
1211 wx_vlan_strip_control(wx, true);
1212 else
1213 wx_vlan_strip_control(wx, false);
1214
1215 }
1216 EXPORT_SYMBOL(wx_set_rx_mode);
1217
wx_set_rx_buffer_len(struct wx * wx)1218 static void wx_set_rx_buffer_len(struct wx *wx)
1219 {
1220 struct net_device *netdev = wx->netdev;
1221 u32 mhadd, max_frame;
1222
1223 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
1224 /* adjust max frame to be at least the size of a standard frame */
1225 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
1226 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
1227
1228 mhadd = rd32(wx, WX_PSR_MAX_SZ);
1229 if (max_frame != mhadd)
1230 wr32(wx, WX_PSR_MAX_SZ, max_frame);
1231 }
1232
1233 /**
1234 * wx_change_mtu - Change the Maximum Transfer Unit
1235 * @netdev: network interface device structure
1236 * @new_mtu: new value for maximum frame size
1237 *
1238 * Returns 0 on success, negative on failure
1239 **/
wx_change_mtu(struct net_device * netdev,int new_mtu)1240 int wx_change_mtu(struct net_device *netdev, int new_mtu)
1241 {
1242 struct wx *wx = netdev_priv(netdev);
1243
1244 netdev->mtu = new_mtu;
1245 wx_set_rx_buffer_len(wx);
1246
1247 return 0;
1248 }
1249 EXPORT_SYMBOL(wx_change_mtu);
1250
1251 /* Disable the specified rx queue */
wx_disable_rx_queue(struct wx * wx,struct wx_ring * ring)1252 void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring)
1253 {
1254 u8 reg_idx = ring->reg_idx;
1255 u32 rxdctl;
1256 int ret;
1257
1258 /* write value back with RRCFG.EN bit cleared */
1259 wr32m(wx, WX_PX_RR_CFG(reg_idx),
1260 WX_PX_RR_CFG_RR_EN, 0);
1261
1262 /* the hardware may take up to 100us to really disable the rx queue */
1263 ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN),
1264 10, 100, true, wx, WX_PX_RR_CFG(reg_idx));
1265
1266 if (ret == -ETIMEDOUT) {
1267 /* Just for information */
1268 wx_err(wx,
1269 "RRCFG.EN on Rx queue %d not cleared within the polling period\n",
1270 reg_idx);
1271 }
1272 }
1273 EXPORT_SYMBOL(wx_disable_rx_queue);
1274
wx_enable_rx_queue(struct wx * wx,struct wx_ring * ring)1275 static void wx_enable_rx_queue(struct wx *wx, struct wx_ring *ring)
1276 {
1277 u8 reg_idx = ring->reg_idx;
1278 u32 rxdctl;
1279 int ret;
1280
1281 ret = read_poll_timeout(rd32, rxdctl, rxdctl & WX_PX_RR_CFG_RR_EN,
1282 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx));
1283
1284 if (ret == -ETIMEDOUT) {
1285 /* Just for information */
1286 wx_err(wx,
1287 "RRCFG.EN on Rx queue %d not set within the polling period\n",
1288 reg_idx);
1289 }
1290 }
1291
wx_configure_srrctl(struct wx * wx,struct wx_ring * rx_ring)1292 static void wx_configure_srrctl(struct wx *wx,
1293 struct wx_ring *rx_ring)
1294 {
1295 u16 reg_idx = rx_ring->reg_idx;
1296 u32 srrctl;
1297
1298 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
1299 srrctl &= ~(WX_PX_RR_CFG_RR_HDR_SZ |
1300 WX_PX_RR_CFG_RR_BUF_SZ |
1301 WX_PX_RR_CFG_SPLIT_MODE);
1302 /* configure header buffer length, needed for RSC */
1303 srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT;
1304
1305 /* configure the packet buffer length */
1306 srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT;
1307
1308 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);
1309 }
1310
wx_configure_tx_ring(struct wx * wx,struct wx_ring * ring)1311 static void wx_configure_tx_ring(struct wx *wx,
1312 struct wx_ring *ring)
1313 {
1314 u32 txdctl = WX_PX_TR_CFG_ENABLE;
1315 u8 reg_idx = ring->reg_idx;
1316 u64 tdba = ring->dma;
1317 int ret;
1318
1319 /* disable queue to avoid issues while updating state */
1320 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH);
1321 WX_WRITE_FLUSH(wx);
1322
1323 wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32));
1324 wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba));
1325
1326 /* reset head and tail pointers */
1327 wr32(wx, WX_PX_TR_RP(reg_idx), 0);
1328 wr32(wx, WX_PX_TR_WP(reg_idx), 0);
1329 ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx);
1330
1331 if (ring->count < WX_MAX_TXD)
1332 txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT;
1333 txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT;
1334
1335 /* reinitialize tx_buffer_info */
1336 memset(ring->tx_buffer_info, 0,
1337 sizeof(struct wx_tx_buffer) * ring->count);
1338
1339 /* enable queue */
1340 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl);
1341
1342 /* poll to verify queue is enabled */
1343 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE,
1344 1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx));
1345 if (ret == -ETIMEDOUT)
1346 wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx);
1347 }
1348
wx_configure_rx_ring(struct wx * wx,struct wx_ring * ring)1349 static void wx_configure_rx_ring(struct wx *wx,
1350 struct wx_ring *ring)
1351 {
1352 u16 reg_idx = ring->reg_idx;
1353 union wx_rx_desc *rx_desc;
1354 u64 rdba = ring->dma;
1355 u32 rxdctl;
1356
1357 /* disable queue to avoid issues while updating state */
1358 rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
1359 wx_disable_rx_queue(wx, ring);
1360
1361 wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32));
1362 wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba));
1363
1364 if (ring->count == WX_MAX_RXD)
1365 rxdctl |= 0 << WX_PX_RR_CFG_RR_SIZE_SHIFT;
1366 else
1367 rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT;
1368
1369 rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT;
1370 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl);
1371
1372 /* reset head and tail pointers */
1373 wr32(wx, WX_PX_RR_RP(reg_idx), 0);
1374 wr32(wx, WX_PX_RR_WP(reg_idx), 0);
1375 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx);
1376
1377 wx_configure_srrctl(wx, ring);
1378
1379 /* initialize rx_buffer_info */
1380 memset(ring->rx_buffer_info, 0,
1381 sizeof(struct wx_rx_buffer) * ring->count);
1382
1383 /* initialize Rx descriptor 0 */
1384 rx_desc = WX_RX_DESC(ring, 0);
1385 rx_desc->wb.upper.length = 0;
1386
1387 /* enable receive descriptor ring */
1388 wr32m(wx, WX_PX_RR_CFG(reg_idx),
1389 WX_PX_RR_CFG_RR_EN, WX_PX_RR_CFG_RR_EN);
1390
1391 wx_enable_rx_queue(wx, ring);
1392 wx_alloc_rx_buffers(ring, wx_desc_unused(ring));
1393 }
1394
1395 /**
1396 * wx_configure_tx - Configure Transmit Unit after Reset
1397 * @wx: pointer to private structure
1398 *
1399 * Configure the Tx unit of the MAC after a reset.
1400 **/
wx_configure_tx(struct wx * wx)1401 static void wx_configure_tx(struct wx *wx)
1402 {
1403 u32 i;
1404
1405 /* TDM_CTL.TE must be before Tx queues are enabled */
1406 wr32m(wx, WX_TDM_CTL,
1407 WX_TDM_CTL_TE, WX_TDM_CTL_TE);
1408
1409 /* Setup the HW Tx Head and Tail descriptor pointers */
1410 for (i = 0; i < wx->num_tx_queues; i++)
1411 wx_configure_tx_ring(wx, wx->tx_ring[i]);
1412
1413 wr32m(wx, WX_TSC_BUF_AE, WX_TSC_BUF_AE_THR, 0x10);
1414
1415 if (wx->mac.type == wx_mac_em)
1416 wr32m(wx, WX_TSC_CTL, WX_TSC_CTL_TX_DIS | WX_TSC_CTL_TSEC_DIS, 0x1);
1417
1418 /* enable mac transmitter */
1419 wr32m(wx, WX_MAC_TX_CFG,
1420 WX_MAC_TX_CFG_TE, WX_MAC_TX_CFG_TE);
1421 }
1422
wx_restore_vlan(struct wx * wx)1423 static void wx_restore_vlan(struct wx *wx)
1424 {
1425 u16 vid = 1;
1426
1427 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), 0);
1428
1429 for_each_set_bit_from(vid, wx->active_vlans, VLAN_N_VID)
1430 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), vid);
1431 }
1432
1433 /**
1434 * wx_configure_rx - Configure Receive Unit after Reset
1435 * @wx: pointer to private structure
1436 *
1437 * Configure the Rx unit of the MAC after a reset.
1438 **/
wx_configure_rx(struct wx * wx)1439 void wx_configure_rx(struct wx *wx)
1440 {
1441 u32 psrtype, i;
1442 int ret;
1443
1444 wx_disable_rx(wx);
1445
1446 psrtype = WX_RDB_PL_CFG_L4HDR |
1447 WX_RDB_PL_CFG_L3HDR |
1448 WX_RDB_PL_CFG_L2HDR |
1449 WX_RDB_PL_CFG_TUN_TUNHDR;
1450 wr32(wx, WX_RDB_PL_CFG(0), psrtype);
1451
1452 /* enable hw crc stripping */
1453 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_CRC_STRIP, WX_RSC_CTL_CRC_STRIP);
1454
1455 if (wx->mac.type == wx_mac_sp) {
1456 u32 psrctl;
1457
1458 /* RSC Setup */
1459 psrctl = rd32(wx, WX_PSR_CTL);
1460 psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */
1461 psrctl |= WX_PSR_CTL_RSC_DIS;
1462 wr32(wx, WX_PSR_CTL, psrctl);
1463 }
1464
1465 /* set_rx_buffer_len must be called before ring initialization */
1466 wx_set_rx_buffer_len(wx);
1467
1468 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1469 * the Base and Length of the Rx Descriptor Ring
1470 */
1471 for (i = 0; i < wx->num_rx_queues; i++)
1472 wx_configure_rx_ring(wx, wx->rx_ring[i]);
1473
1474 /* Enable all receives, disable security engine prior to block traffic */
1475 ret = wx_disable_sec_rx_path(wx);
1476 if (ret < 0)
1477 wx_err(wx, "The register status is abnormal, please check device.");
1478
1479 wx_enable_rx(wx);
1480 wx_enable_sec_rx_path(wx);
1481 }
1482 EXPORT_SYMBOL(wx_configure_rx);
1483
wx_configure_isb(struct wx * wx)1484 static void wx_configure_isb(struct wx *wx)
1485 {
1486 /* set ISB Address */
1487 wr32(wx, WX_PX_ISB_ADDR_L, wx->isb_dma & DMA_BIT_MASK(32));
1488 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
1489 wr32(wx, WX_PX_ISB_ADDR_H, upper_32_bits(wx->isb_dma));
1490 }
1491
wx_configure(struct wx * wx)1492 void wx_configure(struct wx *wx)
1493 {
1494 wx_set_rxpba(wx);
1495 wx_configure_port(wx);
1496
1497 wx_set_rx_mode(wx->netdev);
1498 wx_restore_vlan(wx);
1499 wx_enable_sec_rx_path(wx);
1500
1501 wx_configure_tx(wx);
1502 wx_configure_rx(wx);
1503 wx_configure_isb(wx);
1504 }
1505 EXPORT_SYMBOL(wx_configure);
1506
1507 /**
1508 * wx_disable_pcie_master - Disable PCI-express master access
1509 * @wx: pointer to hardware structure
1510 *
1511 * Disables PCI-Express master access and verifies there are no pending
1512 * requests.
1513 **/
wx_disable_pcie_master(struct wx * wx)1514 int wx_disable_pcie_master(struct wx *wx)
1515 {
1516 int status = 0;
1517 u32 val;
1518
1519 /* Always set this bit to ensure any future transactions are blocked */
1520 pci_clear_master(wx->pdev);
1521
1522 /* Exit if master requests are blocked */
1523 if (!(rd32(wx, WX_PX_TRANSACTION_PENDING)))
1524 return 0;
1525
1526 /* Poll for master request bit to clear */
1527 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT,
1528 false, wx, WX_PX_TRANSACTION_PENDING);
1529 if (status < 0)
1530 wx_err(wx, "PCIe transaction pending bit did not clear.\n");
1531
1532 return status;
1533 }
1534 EXPORT_SYMBOL(wx_disable_pcie_master);
1535
1536 /**
1537 * wx_stop_adapter - Generic stop Tx/Rx units
1538 * @wx: pointer to hardware structure
1539 *
1540 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts,
1541 * disables transmit and receive units. The adapter_stopped flag is used by
1542 * the shared code and drivers to determine if the adapter is in a stopped
1543 * state and should not touch the hardware.
1544 **/
wx_stop_adapter(struct wx * wx)1545 int wx_stop_adapter(struct wx *wx)
1546 {
1547 u16 i;
1548
1549 /* Set the adapter_stopped flag so other driver functions stop touching
1550 * the hardware
1551 */
1552 wx->adapter_stopped = true;
1553
1554 /* Disable the receive unit */
1555 wx_disable_rx(wx);
1556
1557 /* Set interrupt mask to stop interrupts from being generated */
1558 wx_intr_disable(wx, WX_INTR_ALL);
1559
1560 /* Clear any pending interrupts, flush previous writes */
1561 wr32(wx, WX_PX_MISC_IC, 0xffffffff);
1562 wr32(wx, WX_BME_CTL, 0x3);
1563
1564 /* Disable the transmit unit. Each queue must be disabled. */
1565 for (i = 0; i < wx->mac.max_tx_queues; i++) {
1566 wr32m(wx, WX_PX_TR_CFG(i),
1567 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE,
1568 WX_PX_TR_CFG_SWFLSH);
1569 }
1570
1571 /* Disable the receive unit by stopping each queue */
1572 for (i = 0; i < wx->mac.max_rx_queues; i++) {
1573 wr32m(wx, WX_PX_RR_CFG(i),
1574 WX_PX_RR_CFG_RR_EN, 0);
1575 }
1576
1577 /* flush all queues disables */
1578 WX_WRITE_FLUSH(wx);
1579
1580 /* Prevent the PCI-E bus from hanging by disabling PCI-E master
1581 * access and verify no pending requests
1582 */
1583 return wx_disable_pcie_master(wx);
1584 }
1585 EXPORT_SYMBOL(wx_stop_adapter);
1586
wx_reset_misc(struct wx * wx)1587 void wx_reset_misc(struct wx *wx)
1588 {
1589 int i;
1590
1591 /* receive packets that size > 2048 */
1592 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE);
1593
1594 /* clear counters on read */
1595 wr32m(wx, WX_MMC_CONTROL,
1596 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD);
1597
1598 wr32m(wx, WX_MAC_RX_FLOW_CTRL,
1599 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE);
1600
1601 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
1602
1603 wr32m(wx, WX_MIS_RST_ST,
1604 WX_MIS_RST_ST_RST_INIT, 0x1E00);
1605
1606 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
1607 wr32(wx, WX_PSR_MNG_FLEX_SEL, 0);
1608 for (i = 0; i < 16; i++) {
1609 wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0);
1610 wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0);
1611 wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0);
1612 }
1613 wr32(wx, WX_PSR_LAN_FLEX_SEL, 0);
1614 for (i = 0; i < 16; i++) {
1615 wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0);
1616 wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0);
1617 wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0);
1618 }
1619
1620 /* set pause frame dst mac addr */
1621 wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001);
1622 wr32(wx, WX_RDB_PFCMACDAH, 0x0180);
1623 }
1624 EXPORT_SYMBOL(wx_reset_misc);
1625
1626 /**
1627 * wx_get_pcie_msix_counts - Gets MSI-X vector count
1628 * @wx: pointer to hardware structure
1629 * @msix_count: number of MSI interrupts that can be obtained
1630 * @max_msix_count: number of MSI interrupts that mac need
1631 *
1632 * Read PCIe configuration space, and get the MSI-X vector count from
1633 * the capabilities table.
1634 **/
wx_get_pcie_msix_counts(struct wx * wx,u16 * msix_count,u16 max_msix_count)1635 int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count)
1636 {
1637 struct pci_dev *pdev = wx->pdev;
1638 struct device *dev = &pdev->dev;
1639 int pos;
1640
1641 *msix_count = 1;
1642 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
1643 if (!pos) {
1644 dev_err(dev, "Unable to find MSI-X Capabilities\n");
1645 return -EINVAL;
1646 }
1647 pci_read_config_word(pdev,
1648 pos + PCI_MSIX_FLAGS,
1649 msix_count);
1650 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK;
1651 /* MSI-X count is zero-based in HW */
1652 *msix_count += 1;
1653
1654 if (*msix_count > max_msix_count)
1655 *msix_count = max_msix_count;
1656
1657 return 0;
1658 }
1659 EXPORT_SYMBOL(wx_get_pcie_msix_counts);
1660
wx_sw_init(struct wx * wx)1661 int wx_sw_init(struct wx *wx)
1662 {
1663 struct pci_dev *pdev = wx->pdev;
1664 u32 ssid = 0;
1665 int err = 0;
1666
1667 wx->vendor_id = pdev->vendor;
1668 wx->device_id = pdev->device;
1669 wx->revision_id = pdev->revision;
1670 wx->oem_svid = pdev->subsystem_vendor;
1671 wx->oem_ssid = pdev->subsystem_device;
1672 wx->bus.device = PCI_SLOT(pdev->devfn);
1673 wx->bus.func = PCI_FUNC(pdev->devfn);
1674
1675 if (wx->oem_svid == PCI_VENDOR_ID_WANGXUN) {
1676 wx->subsystem_vendor_id = pdev->subsystem_vendor;
1677 wx->subsystem_device_id = pdev->subsystem_device;
1678 } else {
1679 err = wx_flash_read_dword(wx, 0xfffdc, &ssid);
1680 if (err < 0) {
1681 wx_err(wx, "read of internal subsystem device id failed\n");
1682 return err;
1683 }
1684
1685 wx->subsystem_device_id = swab16((u16)ssid);
1686 }
1687
1688 wx->mac_table = kcalloc(wx->mac.num_rar_entries,
1689 sizeof(struct wx_mac_addr),
1690 GFP_KERNEL);
1691 if (!wx->mac_table) {
1692 wx_err(wx, "mac_table allocation failed\n");
1693 return -ENOMEM;
1694 }
1695
1696 return 0;
1697 }
1698 EXPORT_SYMBOL(wx_sw_init);
1699
1700 /**
1701 * wx_find_vlvf_slot - find the vlanid or the first empty slot
1702 * @wx: pointer to hardware structure
1703 * @vlan: VLAN id to write to VLAN filter
1704 *
1705 * return the VLVF index where this VLAN id should be placed
1706 *
1707 **/
wx_find_vlvf_slot(struct wx * wx,u32 vlan)1708 static int wx_find_vlvf_slot(struct wx *wx, u32 vlan)
1709 {
1710 u32 bits = 0, first_empty_slot = 0;
1711 int regindex;
1712
1713 /* short cut the special case */
1714 if (vlan == 0)
1715 return 0;
1716
1717 /* Search for the vlan id in the VLVF entries. Save off the first empty
1718 * slot found along the way
1719 */
1720 for (regindex = 1; regindex < WX_PSR_VLAN_SWC_ENTRIES; regindex++) {
1721 wr32(wx, WX_PSR_VLAN_SWC_IDX, regindex);
1722 bits = rd32(wx, WX_PSR_VLAN_SWC);
1723 if (!bits && !(first_empty_slot))
1724 first_empty_slot = regindex;
1725 else if ((bits & 0x0FFF) == vlan)
1726 break;
1727 }
1728
1729 if (regindex >= WX_PSR_VLAN_SWC_ENTRIES) {
1730 if (first_empty_slot)
1731 regindex = first_empty_slot;
1732 else
1733 regindex = -ENOMEM;
1734 }
1735
1736 return regindex;
1737 }
1738
1739 /**
1740 * wx_set_vlvf - Set VLAN Pool Filter
1741 * @wx: pointer to hardware structure
1742 * @vlan: VLAN id to write to VLAN filter
1743 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1744 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1745 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
1746 * should be changed
1747 *
1748 * Turn on/off specified bit in VLVF table.
1749 **/
wx_set_vlvf(struct wx * wx,u32 vlan,u32 vind,bool vlan_on,bool * vfta_changed)1750 static int wx_set_vlvf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on,
1751 bool *vfta_changed)
1752 {
1753 int vlvf_index;
1754 u32 vt, bits;
1755
1756 /* If VT Mode is set
1757 * Either vlan_on
1758 * make sure the vlan is in VLVF
1759 * set the vind bit in the matching VLVFB
1760 * Or !vlan_on
1761 * clear the pool bit and possibly the vind
1762 */
1763 vt = rd32(wx, WX_CFG_PORT_CTL);
1764 if (!(vt & WX_CFG_PORT_CTL_NUM_VT_MASK))
1765 return 0;
1766
1767 vlvf_index = wx_find_vlvf_slot(wx, vlan);
1768 if (vlvf_index < 0)
1769 return vlvf_index;
1770
1771 wr32(wx, WX_PSR_VLAN_SWC_IDX, vlvf_index);
1772 if (vlan_on) {
1773 /* set the pool bit */
1774 if (vind < 32) {
1775 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L);
1776 bits |= (1 << vind);
1777 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits);
1778 } else {
1779 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H);
1780 bits |= (1 << (vind - 32));
1781 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits);
1782 }
1783 } else {
1784 /* clear the pool bit */
1785 if (vind < 32) {
1786 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L);
1787 bits &= ~(1 << vind);
1788 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits);
1789 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_H);
1790 } else {
1791 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H);
1792 bits &= ~(1 << (vind - 32));
1793 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits);
1794 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_L);
1795 }
1796 }
1797
1798 if (bits) {
1799 wr32(wx, WX_PSR_VLAN_SWC, (WX_PSR_VLAN_SWC_VIEN | vlan));
1800 if (!vlan_on && vfta_changed)
1801 *vfta_changed = false;
1802 } else {
1803 wr32(wx, WX_PSR_VLAN_SWC, 0);
1804 }
1805
1806 return 0;
1807 }
1808
1809 /**
1810 * wx_set_vfta - Set VLAN filter table
1811 * @wx: pointer to hardware structure
1812 * @vlan: VLAN id to write to VLAN filter
1813 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1814 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1815 *
1816 * Turn on/off specified VLAN in the VLAN filter table.
1817 **/
wx_set_vfta(struct wx * wx,u32 vlan,u32 vind,bool vlan_on)1818 static int wx_set_vfta(struct wx *wx, u32 vlan, u32 vind, bool vlan_on)
1819 {
1820 u32 bitindex, vfta, targetbit;
1821 bool vfta_changed = false;
1822 int regindex, ret;
1823
1824 /* this is a 2 part operation - first the VFTA, then the
1825 * VLVF and VLVFB if VT Mode is set
1826 * We don't write the VFTA until we know the VLVF part succeeded.
1827 */
1828
1829 /* Part 1
1830 * The VFTA is a bitstring made up of 128 32-bit registers
1831 * that enable the particular VLAN id, much like the MTA:
1832 * bits[11-5]: which register
1833 * bits[4-0]: which bit in the register
1834 */
1835 regindex = (vlan >> 5) & 0x7F;
1836 bitindex = vlan & 0x1F;
1837 targetbit = (1 << bitindex);
1838 /* errata 5 */
1839 vfta = wx->mac.vft_shadow[regindex];
1840 if (vlan_on) {
1841 if (!(vfta & targetbit)) {
1842 vfta |= targetbit;
1843 vfta_changed = true;
1844 }
1845 } else {
1846 if ((vfta & targetbit)) {
1847 vfta &= ~targetbit;
1848 vfta_changed = true;
1849 }
1850 }
1851 /* Part 2
1852 * Call wx_set_vlvf to set VLVFB and VLVF
1853 */
1854 ret = wx_set_vlvf(wx, vlan, vind, vlan_on, &vfta_changed);
1855 if (ret != 0)
1856 return ret;
1857
1858 if (vfta_changed)
1859 wr32(wx, WX_PSR_VLAN_TBL(regindex), vfta);
1860 wx->mac.vft_shadow[regindex] = vfta;
1861
1862 return 0;
1863 }
1864
1865 /**
1866 * wx_clear_vfta - Clear VLAN filter table
1867 * @wx: pointer to hardware structure
1868 *
1869 * Clears the VLAN filer table, and the VMDq index associated with the filter
1870 **/
wx_clear_vfta(struct wx * wx)1871 static void wx_clear_vfta(struct wx *wx)
1872 {
1873 u32 offset;
1874
1875 for (offset = 0; offset < wx->mac.vft_size; offset++) {
1876 wr32(wx, WX_PSR_VLAN_TBL(offset), 0);
1877 wx->mac.vft_shadow[offset] = 0;
1878 }
1879
1880 for (offset = 0; offset < WX_PSR_VLAN_SWC_ENTRIES; offset++) {
1881 wr32(wx, WX_PSR_VLAN_SWC_IDX, offset);
1882 wr32(wx, WX_PSR_VLAN_SWC, 0);
1883 wr32(wx, WX_PSR_VLAN_SWC_VM_L, 0);
1884 wr32(wx, WX_PSR_VLAN_SWC_VM_H, 0);
1885 }
1886 }
1887
wx_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)1888 int wx_vlan_rx_add_vid(struct net_device *netdev,
1889 __be16 proto, u16 vid)
1890 {
1891 struct wx *wx = netdev_priv(netdev);
1892
1893 /* add VID to filter table */
1894 wx_set_vfta(wx, vid, VMDQ_P(0), true);
1895 set_bit(vid, wx->active_vlans);
1896
1897 return 0;
1898 }
1899 EXPORT_SYMBOL(wx_vlan_rx_add_vid);
1900
wx_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)1901 int wx_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
1902 {
1903 struct wx *wx = netdev_priv(netdev);
1904
1905 /* remove VID from filter table */
1906 if (vid)
1907 wx_set_vfta(wx, vid, VMDQ_P(0), false);
1908 clear_bit(vid, wx->active_vlans);
1909
1910 return 0;
1911 }
1912 EXPORT_SYMBOL(wx_vlan_rx_kill_vid);
1913
1914 /**
1915 * wx_start_hw - Prepare hardware for Tx/Rx
1916 * @wx: pointer to hardware structure
1917 *
1918 * Starts the hardware using the generic start_hw function
1919 * and the generation start_hw function.
1920 * Then performs revision-specific operations, if any.
1921 **/
wx_start_hw(struct wx * wx)1922 void wx_start_hw(struct wx *wx)
1923 {
1924 int i;
1925
1926 /* Clear the VLAN filter table */
1927 wx_clear_vfta(wx);
1928 WX_WRITE_FLUSH(wx);
1929 /* Clear the rate limiters */
1930 for (i = 0; i < wx->mac.max_tx_queues; i++) {
1931 wr32(wx, WX_TDM_RP_IDX, i);
1932 wr32(wx, WX_TDM_RP_RATE, 0);
1933 }
1934 }
1935 EXPORT_SYMBOL(wx_start_hw);
1936
1937 MODULE_LICENSE("GPL");
1938