1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 *
5 * Copyright (C) 2008,2009 STMicroelectronics
6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
7 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
8 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
9 */
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/seq_file.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25
26 /* Since we request GPIOs from ourself */
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
32
33 #include "../core.h"
34 #include "../pinctrl-utils.h"
35
36 #include "pinctrl-nomadik.h"
37
38 /*
39 * The GPIO module in the Nomadik family of Systems-on-Chip is an
40 * AMBA device, managing 32 pins and alternate functions. The logic block
41 * is currently used in the Nomadik and ux500.
42 *
43 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
44 */
45
46 /*
47 * pin configurations are represented by 32-bit integers:
48 *
49 * bit 0.. 8 - Pin Number (512 Pins Maximum)
50 * bit 9..10 - Alternate Function Selection
51 * bit 11..12 - Pull up/down state
52 * bit 13 - Sleep mode behaviour
53 * bit 14 - Direction
54 * bit 15 - Value (if output)
55 * bit 16..18 - SLPM pull up/down state
56 * bit 19..20 - SLPM direction
57 * bit 21..22 - SLPM Value (if output)
58 * bit 23..25 - PDIS value (if input)
59 * bit 26 - Gpio mode
60 * bit 27 - Sleep mode
61 *
62 * to facilitate the definition, the following macros are provided
63 *
64 * PIN_CFG_DEFAULT - default config (0):
65 * pull up/down = disabled
66 * sleep mode = input/wakeup
67 * direction = input
68 * value = low
69 * SLPM direction = same as normal
70 * SLPM pull = same as normal
71 * SLPM value = same as normal
72 *
73 * PIN_CFG - default config with alternate function
74 */
75
76 typedef unsigned long pin_cfg_t;
77
78 #define PIN_NUM_MASK 0x1ff
79 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
80
81 #define PIN_ALT_SHIFT 9
82 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
83 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
84 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
85 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
86 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
87 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
88
89 #define PIN_PULL_SHIFT 11
90 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
91 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
92 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
93 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
94 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
95
96 #define PIN_SLPM_SHIFT 13
97 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
98 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
99 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
100 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
101 /* These two replace the above in DB8500v2+ */
102 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
103 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
104 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
105
106 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
107 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
108
109 #define PIN_DIR_SHIFT 14
110 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
111 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
112 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
113 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
114
115 #define PIN_VAL_SHIFT 15
116 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
117 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
118 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
119 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
120
121 #define PIN_SLPM_PULL_SHIFT 16
122 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
123 #define PIN_SLPM_PULL(x) \
124 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
125 #define PIN_SLPM_PULL_NONE \
126 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
127 #define PIN_SLPM_PULL_UP \
128 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
129 #define PIN_SLPM_PULL_DOWN \
130 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
131
132 #define PIN_SLPM_DIR_SHIFT 19
133 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
134 #define PIN_SLPM_DIR(x) \
135 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
136 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
137 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
138
139 #define PIN_SLPM_VAL_SHIFT 21
140 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
141 #define PIN_SLPM_VAL(x) \
142 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
143 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
144 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
145
146 #define PIN_SLPM_PDIS_SHIFT 23
147 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
148 #define PIN_SLPM_PDIS(x) \
149 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
150 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
151 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
152 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
153
154 #define PIN_LOWEMI_SHIFT 25
155 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
156 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
157 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
158 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
159
160 #define PIN_GPIOMODE_SHIFT 26
161 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
162 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
163 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
164 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
165
166 #define PIN_SLEEPMODE_SHIFT 27
167 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
168 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
169 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
170 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
171
172
173 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
174 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
175 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
176 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
177 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
178 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
179
180 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
181 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
182 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
183 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
184 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
185
186 #define PIN_CFG_DEFAULT (0)
187
188 #define PIN_CFG(num, alt) \
189 (PIN_CFG_DEFAULT |\
190 (PIN_NUM(num) | PIN_##alt))
191
192 #define PIN_CFG_INPUT(num, alt, pull) \
193 (PIN_CFG_DEFAULT |\
194 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
195
196 #define PIN_CFG_OUTPUT(num, alt, val) \
197 (PIN_CFG_DEFAULT |\
198 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
199
200 /*
201 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
202 * the "gpio" namespace for generic and cross-machine functions
203 */
204
205 #define GPIO_BLOCK_SHIFT 5
206 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
207 #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
208
209 /* Register in the logic block */
210 #define NMK_GPIO_DAT 0x00
211 #define NMK_GPIO_DATS 0x04
212 #define NMK_GPIO_DATC 0x08
213 #define NMK_GPIO_PDIS 0x0c
214 #define NMK_GPIO_DIR 0x10
215 #define NMK_GPIO_DIRS 0x14
216 #define NMK_GPIO_DIRC 0x18
217 #define NMK_GPIO_SLPC 0x1c
218 #define NMK_GPIO_AFSLA 0x20
219 #define NMK_GPIO_AFSLB 0x24
220 #define NMK_GPIO_LOWEMI 0x28
221
222 #define NMK_GPIO_RIMSC 0x40
223 #define NMK_GPIO_FIMSC 0x44
224 #define NMK_GPIO_IS 0x48
225 #define NMK_GPIO_IC 0x4c
226 #define NMK_GPIO_RWIMSC 0x50
227 #define NMK_GPIO_FWIMSC 0x54
228 #define NMK_GPIO_WKS 0x58
229 /* These appear in DB8540 and later ASICs */
230 #define NMK_GPIO_EDGELEVEL 0x5C
231 #define NMK_GPIO_LEVEL 0x60
232
233
234 /* Pull up/down values */
235 enum nmk_gpio_pull {
236 NMK_GPIO_PULL_NONE,
237 NMK_GPIO_PULL_UP,
238 NMK_GPIO_PULL_DOWN,
239 };
240
241 /* Sleep mode */
242 enum nmk_gpio_slpm {
243 NMK_GPIO_SLPM_INPUT,
244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
245 NMK_GPIO_SLPM_NOCHANGE,
246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
247 };
248
249 struct nmk_gpio_chip {
250 struct gpio_chip chip;
251 void __iomem *addr;
252 struct clk *clk;
253 unsigned int bank;
254 void (*set_ioforce)(bool enable);
255 spinlock_t lock;
256 bool sleepmode;
257 /* Keep track of configured edges */
258 u32 edge_rising;
259 u32 edge_falling;
260 u32 real_wake;
261 u32 rwimsc;
262 u32 fwimsc;
263 u32 rimsc;
264 u32 fimsc;
265 u32 pull_up;
266 u32 lowemi;
267 };
268
269 /**
270 * struct nmk_pinctrl - state container for the Nomadik pin controller
271 * @dev: containing device pointer
272 * @pctl: corresponding pin controller device
273 * @soc: SoC data for this specific chip
274 * @prcm_base: PRCM register range virtual base
275 */
276 struct nmk_pinctrl {
277 struct device *dev;
278 struct pinctrl_dev *pctl;
279 const struct nmk_pinctrl_soc_data *soc;
280 void __iomem *prcm_base;
281 };
282
283 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
284
285 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
286
287 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
288
__nmk_gpio_set_mode(struct nmk_gpio_chip * nmk_chip,unsigned offset,int gpio_mode)289 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
290 unsigned offset, int gpio_mode)
291 {
292 u32 afunc, bfunc;
293
294 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
295 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
296 if (gpio_mode & NMK_GPIO_ALT_A)
297 afunc |= BIT(offset);
298 if (gpio_mode & NMK_GPIO_ALT_B)
299 bfunc |= BIT(offset);
300 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
301 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
302 }
303
__nmk_gpio_set_slpm(struct nmk_gpio_chip * nmk_chip,unsigned offset,enum nmk_gpio_slpm mode)304 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
305 unsigned offset, enum nmk_gpio_slpm mode)
306 {
307 u32 slpm;
308
309 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
310 if (mode == NMK_GPIO_SLPM_NOCHANGE)
311 slpm |= BIT(offset);
312 else
313 slpm &= ~BIT(offset);
314 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
315 }
316
__nmk_gpio_set_pull(struct nmk_gpio_chip * nmk_chip,unsigned offset,enum nmk_gpio_pull pull)317 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
318 unsigned offset, enum nmk_gpio_pull pull)
319 {
320 u32 pdis;
321
322 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
323 if (pull == NMK_GPIO_PULL_NONE) {
324 pdis |= BIT(offset);
325 nmk_chip->pull_up &= ~BIT(offset);
326 } else {
327 pdis &= ~BIT(offset);
328 }
329
330 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
331
332 if (pull == NMK_GPIO_PULL_UP) {
333 nmk_chip->pull_up |= BIT(offset);
334 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
335 } else if (pull == NMK_GPIO_PULL_DOWN) {
336 nmk_chip->pull_up &= ~BIT(offset);
337 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
338 }
339 }
340
__nmk_gpio_set_lowemi(struct nmk_gpio_chip * nmk_chip,unsigned offset,bool lowemi)341 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
342 unsigned offset, bool lowemi)
343 {
344 bool enabled = nmk_chip->lowemi & BIT(offset);
345
346 if (lowemi == enabled)
347 return;
348
349 if (lowemi)
350 nmk_chip->lowemi |= BIT(offset);
351 else
352 nmk_chip->lowemi &= ~BIT(offset);
353
354 writel_relaxed(nmk_chip->lowemi,
355 nmk_chip->addr + NMK_GPIO_LOWEMI);
356 }
357
__nmk_gpio_make_input(struct nmk_gpio_chip * nmk_chip,unsigned offset)358 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
359 unsigned offset)
360 {
361 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
362 }
363
__nmk_gpio_set_output(struct nmk_gpio_chip * nmk_chip,unsigned offset,int val)364 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
365 unsigned offset, int val)
366 {
367 if (val)
368 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
369 else
370 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
371 }
372
__nmk_gpio_make_output(struct nmk_gpio_chip * nmk_chip,unsigned offset,int val)373 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
374 unsigned offset, int val)
375 {
376 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
377 __nmk_gpio_set_output(nmk_chip, offset, val);
378 }
379
__nmk_gpio_set_mode_safe(struct nmk_gpio_chip * nmk_chip,unsigned offset,int gpio_mode,bool glitch)380 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
381 unsigned offset, int gpio_mode,
382 bool glitch)
383 {
384 u32 rwimsc = nmk_chip->rwimsc;
385 u32 fwimsc = nmk_chip->fwimsc;
386
387 if (glitch && nmk_chip->set_ioforce) {
388 u32 bit = BIT(offset);
389
390 /* Prevent spurious wakeups */
391 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
392 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
393
394 nmk_chip->set_ioforce(true);
395 }
396
397 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
398
399 if (glitch && nmk_chip->set_ioforce) {
400 nmk_chip->set_ioforce(false);
401
402 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
403 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
404 }
405 }
406
407 static void
nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip * nmk_chip,unsigned offset)408 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
409 {
410 u32 falling = nmk_chip->fimsc & BIT(offset);
411 u32 rising = nmk_chip->rimsc & BIT(offset);
412 int gpio = nmk_chip->chip.base + offset;
413 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
414 struct irq_data *d = irq_get_irq_data(irq);
415
416 if (!rising && !falling)
417 return;
418
419 if (!d || !irqd_irq_disabled(d))
420 return;
421
422 if (rising) {
423 nmk_chip->rimsc &= ~BIT(offset);
424 writel_relaxed(nmk_chip->rimsc,
425 nmk_chip->addr + NMK_GPIO_RIMSC);
426 }
427
428 if (falling) {
429 nmk_chip->fimsc &= ~BIT(offset);
430 writel_relaxed(nmk_chip->fimsc,
431 nmk_chip->addr + NMK_GPIO_FIMSC);
432 }
433
434 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
435 }
436
nmk_write_masked(void __iomem * reg,u32 mask,u32 value)437 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
438 {
439 u32 val;
440
441 val = readl(reg);
442 val = ((val & ~mask) | (value & mask));
443 writel(val, reg);
444 }
445
nmk_prcm_altcx_set_mode(struct nmk_pinctrl * npct,unsigned offset,unsigned alt_num)446 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
447 unsigned offset, unsigned alt_num)
448 {
449 int i;
450 u16 reg;
451 u8 bit;
452 u8 alt_index;
453 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
454 const u16 *gpiocr_regs;
455
456 if (!npct->prcm_base)
457 return;
458
459 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
460 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
461 alt_num);
462 return;
463 }
464
465 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
466 if (npct->soc->altcx_pins[i].pin == offset)
467 break;
468 }
469 if (i == npct->soc->npins_altcx) {
470 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
471 offset);
472 return;
473 }
474
475 pin_desc = npct->soc->altcx_pins + i;
476 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
477
478 /*
479 * If alt_num is NULL, just clear current ALTCx selection
480 * to make sure we come back to a pure ALTC selection
481 */
482 if (!alt_num) {
483 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
484 if (pin_desc->altcx[i].used == true) {
485 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
486 bit = pin_desc->altcx[i].control_bit;
487 if (readl(npct->prcm_base + reg) & BIT(bit)) {
488 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
489 dev_dbg(npct->dev,
490 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
491 offset, i+1);
492 }
493 }
494 }
495 return;
496 }
497
498 alt_index = alt_num - 1;
499 if (pin_desc->altcx[alt_index].used == false) {
500 dev_warn(npct->dev,
501 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
502 offset, alt_num);
503 return;
504 }
505
506 /*
507 * Check if any other ALTCx functions are activated on this pin
508 * and disable it first.
509 */
510 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
511 if (i == alt_index)
512 continue;
513 if (pin_desc->altcx[i].used == true) {
514 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
515 bit = pin_desc->altcx[i].control_bit;
516 if (readl(npct->prcm_base + reg) & BIT(bit)) {
517 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
518 dev_dbg(npct->dev,
519 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
520 offset, i+1);
521 }
522 }
523 }
524
525 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
526 bit = pin_desc->altcx[alt_index].control_bit;
527 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
528 offset, alt_index+1);
529 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
530 }
531
532 /*
533 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
534 * - Save SLPM registers
535 * - Set SLPM=0 for the IOs you want to switch and others to 1
536 * - Configure the GPIO registers for the IOs that are being switched
537 * - Set IOFORCE=1
538 * - Modify the AFLSA/B registers for the IOs that are being switched
539 * - Set IOFORCE=0
540 * - Restore SLPM registers
541 * - Any spurious wake up event during switch sequence to be ignored and
542 * cleared
543 */
nmk_gpio_glitch_slpm_init(unsigned int * slpm)544 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
545 {
546 int i;
547
548 for (i = 0; i < NUM_BANKS; i++) {
549 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
550 unsigned int temp = slpm[i];
551
552 if (!chip)
553 break;
554
555 clk_enable(chip->clk);
556
557 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
558 writel(temp, chip->addr + NMK_GPIO_SLPC);
559 }
560 }
561
nmk_gpio_glitch_slpm_restore(unsigned int * slpm)562 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
563 {
564 int i;
565
566 for (i = 0; i < NUM_BANKS; i++) {
567 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
568
569 if (!chip)
570 break;
571
572 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
573
574 clk_disable(chip->clk);
575 }
576 }
577
nmk_prcm_gpiocr_get_mode(struct pinctrl_dev * pctldev,int gpio)578 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
579 {
580 int i;
581 u16 reg;
582 u8 bit;
583 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
584 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
585 const u16 *gpiocr_regs;
586
587 if (!npct->prcm_base)
588 return NMK_GPIO_ALT_C;
589
590 for (i = 0; i < npct->soc->npins_altcx; i++) {
591 if (npct->soc->altcx_pins[i].pin == gpio)
592 break;
593 }
594 if (i == npct->soc->npins_altcx)
595 return NMK_GPIO_ALT_C;
596
597 pin_desc = npct->soc->altcx_pins + i;
598 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
599 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
600 if (pin_desc->altcx[i].used == true) {
601 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
602 bit = pin_desc->altcx[i].control_bit;
603 if (readl(npct->prcm_base + reg) & BIT(bit))
604 return NMK_GPIO_ALT_C+i+1;
605 }
606 }
607 return NMK_GPIO_ALT_C;
608 }
609
610 /* IRQ functions */
611
nmk_gpio_irq_ack(struct irq_data * d)612 static void nmk_gpio_irq_ack(struct irq_data *d)
613 {
614 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
615 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
616
617 clk_enable(nmk_chip->clk);
618 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
619 clk_disable(nmk_chip->clk);
620 }
621
622 enum nmk_gpio_irq_type {
623 NORMAL,
624 WAKE,
625 };
626
__nmk_gpio_irq_modify(struct nmk_gpio_chip * nmk_chip,int offset,enum nmk_gpio_irq_type which,bool enable)627 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
628 int offset, enum nmk_gpio_irq_type which,
629 bool enable)
630 {
631 u32 *rimscval;
632 u32 *fimscval;
633 u32 rimscreg;
634 u32 fimscreg;
635
636 if (which == NORMAL) {
637 rimscreg = NMK_GPIO_RIMSC;
638 fimscreg = NMK_GPIO_FIMSC;
639 rimscval = &nmk_chip->rimsc;
640 fimscval = &nmk_chip->fimsc;
641 } else {
642 rimscreg = NMK_GPIO_RWIMSC;
643 fimscreg = NMK_GPIO_FWIMSC;
644 rimscval = &nmk_chip->rwimsc;
645 fimscval = &nmk_chip->fwimsc;
646 }
647
648 /* we must individually set/clear the two edges */
649 if (nmk_chip->edge_rising & BIT(offset)) {
650 if (enable)
651 *rimscval |= BIT(offset);
652 else
653 *rimscval &= ~BIT(offset);
654 writel(*rimscval, nmk_chip->addr + rimscreg);
655 }
656 if (nmk_chip->edge_falling & BIT(offset)) {
657 if (enable)
658 *fimscval |= BIT(offset);
659 else
660 *fimscval &= ~BIT(offset);
661 writel(*fimscval, nmk_chip->addr + fimscreg);
662 }
663 }
664
__nmk_gpio_set_wake(struct nmk_gpio_chip * nmk_chip,int offset,bool on)665 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
666 int offset, bool on)
667 {
668 /*
669 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
670 * disabled, since setting SLPM to 1 increases power consumption, and
671 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
672 */
673 if (nmk_chip->sleepmode && on) {
674 __nmk_gpio_set_slpm(nmk_chip, offset,
675 NMK_GPIO_SLPM_WAKEUP_ENABLE);
676 }
677
678 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
679 }
680
nmk_gpio_irq_maskunmask(struct nmk_gpio_chip * nmk_chip,struct irq_data * d,bool enable)681 static void nmk_gpio_irq_maskunmask(struct nmk_gpio_chip *nmk_chip,
682 struct irq_data *d, bool enable)
683 {
684 unsigned long flags;
685
686 clk_enable(nmk_chip->clk);
687 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
688 spin_lock(&nmk_chip->lock);
689
690 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
691
692 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
693 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
694
695 spin_unlock(&nmk_chip->lock);
696 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
697 clk_disable(nmk_chip->clk);
698 }
699
nmk_gpio_irq_mask(struct irq_data * d)700 static void nmk_gpio_irq_mask(struct irq_data *d)
701 {
702 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
703 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
704
705 nmk_gpio_irq_maskunmask(nmk_chip, d, false);
706 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
707 }
708
nmk_gpio_irq_unmask(struct irq_data * d)709 static void nmk_gpio_irq_unmask(struct irq_data *d)
710 {
711 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
712 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
713
714 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
715 nmk_gpio_irq_maskunmask(nmk_chip, d, true);
716 }
717
nmk_gpio_irq_set_wake(struct irq_data * d,unsigned int on)718 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
719 {
720 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
721 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
722 unsigned long flags;
723
724 clk_enable(nmk_chip->clk);
725 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
726 spin_lock(&nmk_chip->lock);
727
728 if (irqd_irq_disabled(d))
729 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
730
731 if (on)
732 nmk_chip->real_wake |= BIT(d->hwirq);
733 else
734 nmk_chip->real_wake &= ~BIT(d->hwirq);
735
736 spin_unlock(&nmk_chip->lock);
737 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
738 clk_disable(nmk_chip->clk);
739
740 return 0;
741 }
742
nmk_gpio_irq_set_type(struct irq_data * d,unsigned int type)743 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
744 {
745 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
746 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
747 bool enabled = !irqd_irq_disabled(d);
748 bool wake = irqd_is_wakeup_set(d);
749 unsigned long flags;
750
751 if (type & IRQ_TYPE_LEVEL_HIGH)
752 return -EINVAL;
753 if (type & IRQ_TYPE_LEVEL_LOW)
754 return -EINVAL;
755
756 clk_enable(nmk_chip->clk);
757 spin_lock_irqsave(&nmk_chip->lock, flags);
758
759 if (enabled)
760 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
761
762 if (enabled || wake)
763 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
764
765 nmk_chip->edge_rising &= ~BIT(d->hwirq);
766 if (type & IRQ_TYPE_EDGE_RISING)
767 nmk_chip->edge_rising |= BIT(d->hwirq);
768
769 nmk_chip->edge_falling &= ~BIT(d->hwirq);
770 if (type & IRQ_TYPE_EDGE_FALLING)
771 nmk_chip->edge_falling |= BIT(d->hwirq);
772
773 if (enabled)
774 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
775
776 if (enabled || wake)
777 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
778
779 spin_unlock_irqrestore(&nmk_chip->lock, flags);
780 clk_disable(nmk_chip->clk);
781
782 return 0;
783 }
784
nmk_gpio_irq_startup(struct irq_data * d)785 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
786 {
787 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
788 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
789
790 clk_enable(nmk_chip->clk);
791 nmk_gpio_irq_unmask(d);
792 return 0;
793 }
794
nmk_gpio_irq_shutdown(struct irq_data * d)795 static void nmk_gpio_irq_shutdown(struct irq_data *d)
796 {
797 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
798 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
799
800 nmk_gpio_irq_mask(d);
801 clk_disable(nmk_chip->clk);
802 }
803
nmk_gpio_irq_handler(struct irq_desc * desc)804 static void nmk_gpio_irq_handler(struct irq_desc *desc)
805 {
806 struct irq_chip *host_chip = irq_desc_get_chip(desc);
807 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
808 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
809 u32 status;
810
811 chained_irq_enter(host_chip, desc);
812
813 clk_enable(nmk_chip->clk);
814 status = readl(nmk_chip->addr + NMK_GPIO_IS);
815 clk_disable(nmk_chip->clk);
816
817 while (status) {
818 int bit = __ffs(status);
819
820 generic_handle_domain_irq(chip->irq.domain, bit);
821 status &= ~BIT(bit);
822 }
823
824 chained_irq_exit(host_chip, desc);
825 }
826
827 /* I/O Functions */
828
nmk_gpio_get_dir(struct gpio_chip * chip,unsigned offset)829 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
830 {
831 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
832 int dir;
833
834 clk_enable(nmk_chip->clk);
835
836 dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);
837
838 clk_disable(nmk_chip->clk);
839
840 if (dir)
841 return GPIO_LINE_DIRECTION_OUT;
842
843 return GPIO_LINE_DIRECTION_IN;
844 }
845
nmk_gpio_make_input(struct gpio_chip * chip,unsigned offset)846 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
847 {
848 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
849
850 clk_enable(nmk_chip->clk);
851
852 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
853
854 clk_disable(nmk_chip->clk);
855
856 return 0;
857 }
858
nmk_gpio_get_input(struct gpio_chip * chip,unsigned offset)859 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
860 {
861 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
862 int value;
863
864 clk_enable(nmk_chip->clk);
865
866 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
867
868 clk_disable(nmk_chip->clk);
869
870 return value;
871 }
872
nmk_gpio_set_output(struct gpio_chip * chip,unsigned offset,int val)873 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
874 int val)
875 {
876 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
877
878 clk_enable(nmk_chip->clk);
879
880 __nmk_gpio_set_output(nmk_chip, offset, val);
881
882 clk_disable(nmk_chip->clk);
883 }
884
nmk_gpio_make_output(struct gpio_chip * chip,unsigned offset,int val)885 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
886 int val)
887 {
888 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
889
890 clk_enable(nmk_chip->clk);
891
892 __nmk_gpio_make_output(nmk_chip, offset, val);
893
894 clk_disable(nmk_chip->clk);
895
896 return 0;
897 }
898
899 #ifdef CONFIG_DEBUG_FS
nmk_gpio_get_mode(struct nmk_gpio_chip * nmk_chip,int offset)900 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
901 {
902 u32 afunc, bfunc;
903
904 clk_enable(nmk_chip->clk);
905
906 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
907 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
908
909 clk_disable(nmk_chip->clk);
910
911 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
912 }
913
nmk_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)914 static void nmk_gpio_dbg_show_one(struct seq_file *s,
915 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
916 unsigned offset, unsigned gpio)
917 {
918 const char *label = gpiochip_is_requested(chip, offset);
919 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
920 int mode;
921 bool is_out;
922 bool data_out;
923 bool pull;
924 const char *modes[] = {
925 [NMK_GPIO_ALT_GPIO] = "gpio",
926 [NMK_GPIO_ALT_A] = "altA",
927 [NMK_GPIO_ALT_B] = "altB",
928 [NMK_GPIO_ALT_C] = "altC",
929 [NMK_GPIO_ALT_C+1] = "altC1",
930 [NMK_GPIO_ALT_C+2] = "altC2",
931 [NMK_GPIO_ALT_C+3] = "altC3",
932 [NMK_GPIO_ALT_C+4] = "altC4",
933 };
934
935 clk_enable(nmk_chip->clk);
936 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
937 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
938 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
939 mode = nmk_gpio_get_mode(nmk_chip, offset);
940 if ((mode == NMK_GPIO_ALT_C) && pctldev)
941 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
942
943 if (is_out) {
944 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
945 gpio,
946 label ?: "(none)",
947 data_out ? "hi" : "lo",
948 (mode < 0) ? "unknown" : modes[mode]);
949 } else {
950 int irq = chip->to_irq(chip, offset);
951 const int pullidx = pull ? 1 : 0;
952 int val;
953 static const char * const pulls[] = {
954 "none ",
955 "pull enabled",
956 };
957
958 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
959 gpio,
960 label ?: "(none)",
961 pulls[pullidx],
962 (mode < 0) ? "unknown" : modes[mode]);
963
964 val = nmk_gpio_get_input(chip, offset);
965 seq_printf(s, " VAL %d", val);
966
967 /*
968 * This races with request_irq(), set_irq_type(),
969 * and set_irq_wake() ... but those are "rare".
970 */
971 if (irq > 0 && irq_has_action(irq)) {
972 char *trigger;
973 bool wake;
974
975 if (nmk_chip->edge_rising & BIT(offset))
976 trigger = "edge-rising";
977 else if (nmk_chip->edge_falling & BIT(offset))
978 trigger = "edge-falling";
979 else
980 trigger = "edge-undefined";
981
982 wake = !!(nmk_chip->real_wake & BIT(offset));
983
984 seq_printf(s, " irq-%d %s%s",
985 irq, trigger, wake ? " wakeup" : "");
986 }
987 }
988 clk_disable(nmk_chip->clk);
989 }
990
nmk_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)991 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
992 {
993 unsigned i;
994 unsigned gpio = chip->base;
995
996 for (i = 0; i < chip->ngpio; i++, gpio++) {
997 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
998 seq_printf(s, "\n");
999 }
1000 }
1001
1002 #else
nmk_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)1003 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1004 struct pinctrl_dev *pctldev,
1005 struct gpio_chip *chip,
1006 unsigned offset, unsigned gpio)
1007 {
1008 }
1009 #define nmk_gpio_dbg_show NULL
1010 #endif
1011
1012 /*
1013 * We will allocate memory for the state container using devm* allocators
1014 * binding to the first device reaching this point, it doesn't matter if
1015 * it is the pin controller or GPIO driver. However we need to use the right
1016 * platform device when looking up resources so pay attention to pdev.
1017 */
nmk_gpio_populate_chip(struct device_node * np,struct platform_device * pdev)1018 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1019 struct platform_device *pdev)
1020 {
1021 struct nmk_gpio_chip *nmk_chip;
1022 struct platform_device *gpio_pdev;
1023 struct gpio_chip *chip;
1024 struct resource *res;
1025 struct clk *clk;
1026 void __iomem *base;
1027 u32 id;
1028
1029 gpio_pdev = of_find_device_by_node(np);
1030 if (!gpio_pdev) {
1031 pr_err("populate \"%pOFn\": device not found\n", np);
1032 return ERR_PTR(-ENODEV);
1033 }
1034 if (of_property_read_u32(np, "gpio-bank", &id)) {
1035 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1036 platform_device_put(gpio_pdev);
1037 return ERR_PTR(-EINVAL);
1038 }
1039
1040 /* Already populated? */
1041 nmk_chip = nmk_gpio_chips[id];
1042 if (nmk_chip) {
1043 platform_device_put(gpio_pdev);
1044 return nmk_chip;
1045 }
1046
1047 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1048 if (!nmk_chip) {
1049 platform_device_put(gpio_pdev);
1050 return ERR_PTR(-ENOMEM);
1051 }
1052
1053 nmk_chip->bank = id;
1054 chip = &nmk_chip->chip;
1055 chip->base = id * NMK_GPIO_PER_CHIP;
1056 chip->ngpio = NMK_GPIO_PER_CHIP;
1057 chip->label = dev_name(&gpio_pdev->dev);
1058 chip->parent = &gpio_pdev->dev;
1059
1060 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1061 base = devm_ioremap_resource(&pdev->dev, res);
1062 if (IS_ERR(base)) {
1063 platform_device_put(gpio_pdev);
1064 return ERR_CAST(base);
1065 }
1066 nmk_chip->addr = base;
1067
1068 clk = clk_get(&gpio_pdev->dev, NULL);
1069 if (IS_ERR(clk)) {
1070 platform_device_put(gpio_pdev);
1071 return (void *) clk;
1072 }
1073 clk_prepare(clk);
1074 nmk_chip->clk = clk;
1075
1076 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1077 nmk_gpio_chips[id] = nmk_chip;
1078 return nmk_chip;
1079 }
1080
nmk_gpio_irq_print_chip(struct irq_data * d,struct seq_file * p)1081 static void nmk_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
1082 {
1083 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1084 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
1085
1086 seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank,
1087 gc->base, gc->base + gc->ngpio - 1);
1088 }
1089
1090 static const struct irq_chip nmk_irq_chip = {
1091 .irq_ack = nmk_gpio_irq_ack,
1092 .irq_mask = nmk_gpio_irq_mask,
1093 .irq_unmask = nmk_gpio_irq_unmask,
1094 .irq_set_type = nmk_gpio_irq_set_type,
1095 .irq_set_wake = nmk_gpio_irq_set_wake,
1096 .irq_startup = nmk_gpio_irq_startup,
1097 .irq_shutdown = nmk_gpio_irq_shutdown,
1098 .irq_print_chip = nmk_gpio_irq_print_chip,
1099 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1100 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1101 };
1102
nmk_gpio_probe(struct platform_device * dev)1103 static int nmk_gpio_probe(struct platform_device *dev)
1104 {
1105 struct device_node *np = dev->dev.of_node;
1106 struct nmk_gpio_chip *nmk_chip;
1107 struct gpio_chip *chip;
1108 struct gpio_irq_chip *girq;
1109 bool supports_sleepmode;
1110 int irq;
1111 int ret;
1112
1113 nmk_chip = nmk_gpio_populate_chip(np, dev);
1114 if (IS_ERR(nmk_chip)) {
1115 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1116 return PTR_ERR(nmk_chip);
1117 }
1118
1119 supports_sleepmode =
1120 of_property_read_bool(np, "st,supports-sleepmode");
1121
1122 /* Correct platform device ID */
1123 dev->id = nmk_chip->bank;
1124
1125 irq = platform_get_irq(dev, 0);
1126 if (irq < 0)
1127 return irq;
1128
1129 /*
1130 * The virt address in nmk_chip->addr is in the nomadik register space,
1131 * so we can simply convert the resource address, without remapping
1132 */
1133 nmk_chip->sleepmode = supports_sleepmode;
1134 spin_lock_init(&nmk_chip->lock);
1135
1136 chip = &nmk_chip->chip;
1137 chip->parent = &dev->dev;
1138 chip->request = gpiochip_generic_request;
1139 chip->free = gpiochip_generic_free;
1140 chip->get_direction = nmk_gpio_get_dir;
1141 chip->direction_input = nmk_gpio_make_input;
1142 chip->get = nmk_gpio_get_input;
1143 chip->direction_output = nmk_gpio_make_output;
1144 chip->set = nmk_gpio_set_output;
1145 chip->dbg_show = nmk_gpio_dbg_show;
1146 chip->can_sleep = false;
1147 chip->owner = THIS_MODULE;
1148
1149 girq = &chip->irq;
1150 gpio_irq_chip_set_chip(girq, &nmk_irq_chip);
1151 girq->parent_handler = nmk_gpio_irq_handler;
1152 girq->num_parents = 1;
1153 girq->parents = devm_kcalloc(&dev->dev, 1,
1154 sizeof(*girq->parents),
1155 GFP_KERNEL);
1156 if (!girq->parents)
1157 return -ENOMEM;
1158 girq->parents[0] = irq;
1159 girq->default_type = IRQ_TYPE_NONE;
1160 girq->handler = handle_edge_irq;
1161
1162 clk_enable(nmk_chip->clk);
1163 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1164 clk_disable(nmk_chip->clk);
1165
1166 ret = gpiochip_add_data(chip, nmk_chip);
1167 if (ret)
1168 return ret;
1169
1170 platform_set_drvdata(dev, nmk_chip);
1171
1172 dev_info(&dev->dev, "chip registered\n");
1173
1174 return 0;
1175 }
1176
nmk_get_groups_cnt(struct pinctrl_dev * pctldev)1177 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1178 {
1179 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1180
1181 return npct->soc->ngroups;
1182 }
1183
nmk_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)1184 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1185 unsigned selector)
1186 {
1187 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1188
1189 return npct->soc->groups[selector].grp.name;
1190 }
1191
nmk_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)1192 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1193 const unsigned **pins,
1194 unsigned *npins)
1195 {
1196 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1197
1198 *pins = npct->soc->groups[selector].grp.pins;
1199 *npins = npct->soc->groups[selector].grp.npins;
1200 return 0;
1201 }
1202
find_nmk_gpio_from_pin(unsigned pin)1203 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1204 {
1205 int i;
1206 struct nmk_gpio_chip *nmk_gpio;
1207
1208 for(i = 0; i < NMK_MAX_BANKS; i++) {
1209 nmk_gpio = nmk_gpio_chips[i];
1210 if (!nmk_gpio)
1211 continue;
1212 if (pin >= nmk_gpio->chip.base &&
1213 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1214 return nmk_gpio;
1215 }
1216 return NULL;
1217 }
1218
find_gc_from_pin(unsigned pin)1219 static struct gpio_chip *find_gc_from_pin(unsigned pin)
1220 {
1221 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1222
1223 if (nmk_gpio)
1224 return &nmk_gpio->chip;
1225 return NULL;
1226 }
1227
nmk_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)1228 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1229 unsigned offset)
1230 {
1231 struct gpio_chip *chip = find_gc_from_pin(offset);
1232
1233 if (!chip) {
1234 seq_printf(s, "invalid pin offset");
1235 return;
1236 }
1237 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1238 }
1239
nmk_dt_add_map_mux(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,const char * group,const char * function)1240 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1241 unsigned *num_maps, const char *group,
1242 const char *function)
1243 {
1244 if (*num_maps == *reserved_maps)
1245 return -ENOSPC;
1246
1247 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1248 (*map)[*num_maps].data.mux.group = group;
1249 (*map)[*num_maps].data.mux.function = function;
1250 (*num_maps)++;
1251
1252 return 0;
1253 }
1254
nmk_dt_add_map_configs(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,const char * group,unsigned long * configs,unsigned num_configs)1255 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1256 unsigned *reserved_maps,
1257 unsigned *num_maps, const char *group,
1258 unsigned long *configs, unsigned num_configs)
1259 {
1260 unsigned long *dup_configs;
1261
1262 if (*num_maps == *reserved_maps)
1263 return -ENOSPC;
1264
1265 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1266 GFP_KERNEL);
1267 if (!dup_configs)
1268 return -ENOMEM;
1269
1270 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1271
1272 (*map)[*num_maps].data.configs.group_or_pin = group;
1273 (*map)[*num_maps].data.configs.configs = dup_configs;
1274 (*map)[*num_maps].data.configs.num_configs = num_configs;
1275 (*num_maps)++;
1276
1277 return 0;
1278 }
1279
1280 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1281 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1282 .size = ARRAY_SIZE(y), }
1283
1284 static const unsigned long nmk_pin_input_modes[] = {
1285 PIN_INPUT_NOPULL,
1286 PIN_INPUT_PULLUP,
1287 PIN_INPUT_PULLDOWN,
1288 };
1289
1290 static const unsigned long nmk_pin_output_modes[] = {
1291 PIN_OUTPUT_LOW,
1292 PIN_OUTPUT_HIGH,
1293 PIN_DIR_OUTPUT,
1294 };
1295
1296 static const unsigned long nmk_pin_sleep_modes[] = {
1297 PIN_SLEEPMODE_DISABLED,
1298 PIN_SLEEPMODE_ENABLED,
1299 };
1300
1301 static const unsigned long nmk_pin_sleep_input_modes[] = {
1302 PIN_SLPM_INPUT_NOPULL,
1303 PIN_SLPM_INPUT_PULLUP,
1304 PIN_SLPM_INPUT_PULLDOWN,
1305 PIN_SLPM_DIR_INPUT,
1306 };
1307
1308 static const unsigned long nmk_pin_sleep_output_modes[] = {
1309 PIN_SLPM_OUTPUT_LOW,
1310 PIN_SLPM_OUTPUT_HIGH,
1311 PIN_SLPM_DIR_OUTPUT,
1312 };
1313
1314 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1315 PIN_SLPM_WAKEUP_DISABLE,
1316 PIN_SLPM_WAKEUP_ENABLE,
1317 };
1318
1319 static const unsigned long nmk_pin_gpio_modes[] = {
1320 PIN_GPIOMODE_DISABLED,
1321 PIN_GPIOMODE_ENABLED,
1322 };
1323
1324 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1325 PIN_SLPM_PDIS_DISABLED,
1326 PIN_SLPM_PDIS_ENABLED,
1327 };
1328
1329 struct nmk_cfg_param {
1330 const char *property;
1331 unsigned long config;
1332 const unsigned long *choice;
1333 int size;
1334 };
1335
1336 static const struct nmk_cfg_param nmk_cfg_params[] = {
1337 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1338 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1339 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1340 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1341 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1342 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1343 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1344 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1345 };
1346
nmk_dt_pin_config(int index,int val,unsigned long * config)1347 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1348 {
1349 if (nmk_cfg_params[index].choice == NULL)
1350 *config = nmk_cfg_params[index].config;
1351 else {
1352 /* test if out of range */
1353 if (val < nmk_cfg_params[index].size) {
1354 *config = nmk_cfg_params[index].config |
1355 nmk_cfg_params[index].choice[val];
1356 }
1357 }
1358 return 0;
1359 }
1360
nmk_find_pin_name(struct pinctrl_dev * pctldev,const char * pin_name)1361 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1362 {
1363 int i, pin_number;
1364 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1365
1366 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1367 for (i = 0; i < npct->soc->npins; i++)
1368 if (npct->soc->pins[i].number == pin_number)
1369 return npct->soc->pins[i].name;
1370 return NULL;
1371 }
1372
nmk_pinctrl_dt_get_config(struct device_node * np,unsigned long * configs)1373 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1374 unsigned long *configs)
1375 {
1376 bool has_config = 0;
1377 unsigned long cfg = 0;
1378 int i, val, ret;
1379
1380 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1381 ret = of_property_read_u32(np,
1382 nmk_cfg_params[i].property, &val);
1383 if (ret != -EINVAL) {
1384 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1385 *configs |= cfg;
1386 has_config = 1;
1387 }
1388 }
1389 }
1390
1391 return has_config;
1392 }
1393
nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)1394 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1395 struct device_node *np,
1396 struct pinctrl_map **map,
1397 unsigned *reserved_maps,
1398 unsigned *num_maps)
1399 {
1400 int ret;
1401 const char *function = NULL;
1402 unsigned long configs = 0;
1403 bool has_config = 0;
1404 struct property *prop;
1405 struct device_node *np_config;
1406
1407 ret = of_property_read_string(np, "function", &function);
1408 if (ret >= 0) {
1409 const char *group;
1410
1411 ret = of_property_count_strings(np, "groups");
1412 if (ret < 0)
1413 goto exit;
1414
1415 ret = pinctrl_utils_reserve_map(pctldev, map,
1416 reserved_maps,
1417 num_maps, ret);
1418 if (ret < 0)
1419 goto exit;
1420
1421 of_property_for_each_string(np, "groups", prop, group) {
1422 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1423 group, function);
1424 if (ret < 0)
1425 goto exit;
1426 }
1427 }
1428
1429 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1430 np_config = of_parse_phandle(np, "ste,config", 0);
1431 if (np_config) {
1432 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1433 of_node_put(np_config);
1434 }
1435 if (has_config) {
1436 const char *gpio_name;
1437 const char *pin;
1438
1439 ret = of_property_count_strings(np, "pins");
1440 if (ret < 0)
1441 goto exit;
1442 ret = pinctrl_utils_reserve_map(pctldev, map,
1443 reserved_maps,
1444 num_maps, ret);
1445 if (ret < 0)
1446 goto exit;
1447
1448 of_property_for_each_string(np, "pins", prop, pin) {
1449 gpio_name = nmk_find_pin_name(pctldev, pin);
1450
1451 ret = nmk_dt_add_map_configs(map, reserved_maps,
1452 num_maps,
1453 gpio_name, &configs, 1);
1454 if (ret < 0)
1455 goto exit;
1456 }
1457 }
1458
1459 exit:
1460 return ret;
1461 }
1462
nmk_pinctrl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,unsigned * num_maps)1463 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1464 struct device_node *np_config,
1465 struct pinctrl_map **map, unsigned *num_maps)
1466 {
1467 unsigned reserved_maps;
1468 struct device_node *np;
1469 int ret;
1470
1471 reserved_maps = 0;
1472 *map = NULL;
1473 *num_maps = 0;
1474
1475 for_each_child_of_node(np_config, np) {
1476 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1477 &reserved_maps, num_maps);
1478 if (ret < 0) {
1479 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1480 of_node_put(np);
1481 return ret;
1482 }
1483 }
1484
1485 return 0;
1486 }
1487
1488 static const struct pinctrl_ops nmk_pinctrl_ops = {
1489 .get_groups_count = nmk_get_groups_cnt,
1490 .get_group_name = nmk_get_group_name,
1491 .get_group_pins = nmk_get_group_pins,
1492 .pin_dbg_show = nmk_pin_dbg_show,
1493 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1494 .dt_free_map = pinctrl_utils_free_map,
1495 };
1496
nmk_pmx_get_funcs_cnt(struct pinctrl_dev * pctldev)1497 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1498 {
1499 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1500
1501 return npct->soc->nfunctions;
1502 }
1503
nmk_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned function)1504 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1505 unsigned function)
1506 {
1507 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1508
1509 return npct->soc->functions[function].name;
1510 }
1511
nmk_pmx_get_func_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_groups)1512 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1513 unsigned function,
1514 const char * const **groups,
1515 unsigned * const num_groups)
1516 {
1517 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1518
1519 *groups = npct->soc->functions[function].groups;
1520 *num_groups = npct->soc->functions[function].ngroups;
1521
1522 return 0;
1523 }
1524
nmk_pmx_set(struct pinctrl_dev * pctldev,unsigned function,unsigned group)1525 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1526 unsigned group)
1527 {
1528 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1529 const struct nmk_pingroup *g;
1530 static unsigned int slpm[NUM_BANKS];
1531 unsigned long flags = 0;
1532 bool glitch;
1533 int ret = -EINVAL;
1534 int i;
1535
1536 g = &npct->soc->groups[group];
1537
1538 if (g->altsetting < 0)
1539 return -EINVAL;
1540
1541 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->grp.name, g->grp.npins);
1542
1543 /*
1544 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1545 * we may pass through an undesired state. In this case we take
1546 * some extra care.
1547 *
1548 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1549 * - Save SLPM registers (since we have a shadow register in the
1550 * nmk_chip we're using that as backup)
1551 * - Set SLPM=0 for the IOs you want to switch and others to 1
1552 * - Configure the GPIO registers for the IOs that are being switched
1553 * - Set IOFORCE=1
1554 * - Modify the AFLSA/B registers for the IOs that are being switched
1555 * - Set IOFORCE=0
1556 * - Restore SLPM registers
1557 * - Any spurious wake up event during switch sequence to be ignored
1558 * and cleared
1559 *
1560 * We REALLY need to save ALL slpm registers, because the external
1561 * IOFORCE will switch *all* ports to their sleepmode setting to as
1562 * to avoid glitches. (Not just one port!)
1563 */
1564 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1565
1566 if (glitch) {
1567 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1568
1569 /* Initially don't put any pins to sleep when switching */
1570 memset(slpm, 0xff, sizeof(slpm));
1571
1572 /*
1573 * Then mask the pins that need to be sleeping now when we're
1574 * switching to the ALT C function.
1575 */
1576 for (i = 0; i < g->grp.npins; i++) {
1577 unsigned int bit = g->grp.pins[i] % NMK_GPIO_PER_CHIP;
1578 slpm[g->grp.pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(bit);
1579 }
1580 nmk_gpio_glitch_slpm_init(slpm);
1581 }
1582
1583 for (i = 0; i < g->grp.npins; i++) {
1584 struct nmk_gpio_chip *nmk_chip;
1585 unsigned bit;
1586
1587 nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i]);
1588 if (!nmk_chip) {
1589 dev_err(npct->dev,
1590 "invalid pin offset %d in group %s at index %d\n",
1591 g->grp.pins[i], g->grp.name, i);
1592 goto out_glitch;
1593 }
1594 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->grp.pins[i], g->altsetting);
1595
1596 clk_enable(nmk_chip->clk);
1597 bit = g->grp.pins[i] % NMK_GPIO_PER_CHIP;
1598 /*
1599 * If the pin is switching to altfunc, and there was an
1600 * interrupt installed on it which has been lazy disabled,
1601 * actually mask the interrupt to prevent spurious interrupts
1602 * that would occur while the pin is under control of the
1603 * peripheral. Only SKE does this.
1604 */
1605 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1606
1607 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1608 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1609 clk_disable(nmk_chip->clk);
1610
1611 /*
1612 * Call PRCM GPIOCR config function in case ALTC
1613 * has been selected:
1614 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1615 * must be set.
1616 * - If selection is pure ALTC and previous selection was ALTCx,
1617 * then some bits in PRCM GPIOCR registers must be cleared.
1618 */
1619 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1620 nmk_prcm_altcx_set_mode(npct, g->grp.pins[i],
1621 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1622 }
1623
1624 /* When all pins are successfully reconfigured we get here */
1625 ret = 0;
1626
1627 out_glitch:
1628 if (glitch) {
1629 nmk_gpio_glitch_slpm_restore(slpm);
1630 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1631 }
1632
1633 return ret;
1634 }
1635
nmk_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)1636 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1637 struct pinctrl_gpio_range *range,
1638 unsigned offset)
1639 {
1640 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1641 struct nmk_gpio_chip *nmk_chip;
1642 struct gpio_chip *chip;
1643 unsigned bit;
1644
1645 if (!range) {
1646 dev_err(npct->dev, "invalid range\n");
1647 return -EINVAL;
1648 }
1649 if (!range->gc) {
1650 dev_err(npct->dev, "missing GPIO chip in range\n");
1651 return -EINVAL;
1652 }
1653 chip = range->gc;
1654 nmk_chip = gpiochip_get_data(chip);
1655
1656 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1657
1658 clk_enable(nmk_chip->clk);
1659 bit = offset % NMK_GPIO_PER_CHIP;
1660 /* There is no glitch when converting any pin to GPIO */
1661 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1662 clk_disable(nmk_chip->clk);
1663
1664 return 0;
1665 }
1666
nmk_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)1667 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1668 struct pinctrl_gpio_range *range,
1669 unsigned offset)
1670 {
1671 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1672
1673 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1674 /* Set the pin to some default state, GPIO is usually default */
1675 }
1676
1677 static const struct pinmux_ops nmk_pinmux_ops = {
1678 .get_functions_count = nmk_pmx_get_funcs_cnt,
1679 .get_function_name = nmk_pmx_get_func_name,
1680 .get_function_groups = nmk_pmx_get_func_groups,
1681 .set_mux = nmk_pmx_set,
1682 .gpio_request_enable = nmk_gpio_request_enable,
1683 .gpio_disable_free = nmk_gpio_disable_free,
1684 .strict = true,
1685 };
1686
nmk_pin_config_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)1687 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1688 unsigned long *config)
1689 {
1690 /* Not implemented */
1691 return -EINVAL;
1692 }
1693
nmk_pin_config_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * configs,unsigned num_configs)1694 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1695 unsigned long *configs, unsigned num_configs)
1696 {
1697 static const char *pullnames[] = {
1698 [NMK_GPIO_PULL_NONE] = "none",
1699 [NMK_GPIO_PULL_UP] = "up",
1700 [NMK_GPIO_PULL_DOWN] = "down",
1701 [3] /* illegal */ = "??"
1702 };
1703 static const char *slpmnames[] = {
1704 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1705 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1706 };
1707 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1708 struct nmk_gpio_chip *nmk_chip;
1709 unsigned bit;
1710 pin_cfg_t cfg;
1711 int pull, slpm, output, val, i;
1712 bool lowemi, gpiomode, sleep;
1713
1714 nmk_chip = find_nmk_gpio_from_pin(pin);
1715 if (!nmk_chip) {
1716 dev_err(npct->dev,
1717 "invalid pin offset %d\n", pin);
1718 return -EINVAL;
1719 }
1720
1721 for (i = 0; i < num_configs; i++) {
1722 /*
1723 * The pin config contains pin number and altfunction fields,
1724 * here we just ignore that part. It's being handled by the
1725 * framework and pinmux callback respectively.
1726 */
1727 cfg = (pin_cfg_t) configs[i];
1728 pull = PIN_PULL(cfg);
1729 slpm = PIN_SLPM(cfg);
1730 output = PIN_DIR(cfg);
1731 val = PIN_VAL(cfg);
1732 lowemi = PIN_LOWEMI(cfg);
1733 gpiomode = PIN_GPIOMODE(cfg);
1734 sleep = PIN_SLEEPMODE(cfg);
1735
1736 if (sleep) {
1737 int slpm_pull = PIN_SLPM_PULL(cfg);
1738 int slpm_output = PIN_SLPM_DIR(cfg);
1739 int slpm_val = PIN_SLPM_VAL(cfg);
1740
1741 /* All pins go into GPIO mode at sleep */
1742 gpiomode = true;
1743
1744 /*
1745 * The SLPM_* values are normal values + 1 to allow zero
1746 * to mean "same as normal".
1747 */
1748 if (slpm_pull)
1749 pull = slpm_pull - 1;
1750 if (slpm_output)
1751 output = slpm_output - 1;
1752 if (slpm_val)
1753 val = slpm_val - 1;
1754
1755 dev_dbg(nmk_chip->chip.parent,
1756 "pin %d: sleep pull %s, dir %s, val %s\n",
1757 pin,
1758 slpm_pull ? pullnames[pull] : "same",
1759 slpm_output ? (output ? "output" : "input")
1760 : "same",
1761 slpm_val ? (val ? "high" : "low") : "same");
1762 }
1763
1764 dev_dbg(nmk_chip->chip.parent,
1765 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1766 pin, cfg, pullnames[pull], slpmnames[slpm],
1767 output ? "output " : "input",
1768 output ? (val ? "high" : "low") : "",
1769 lowemi ? "on" : "off");
1770
1771 clk_enable(nmk_chip->clk);
1772 bit = pin % NMK_GPIO_PER_CHIP;
1773 if (gpiomode)
1774 /* No glitch when going to GPIO mode */
1775 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1776 if (output)
1777 __nmk_gpio_make_output(nmk_chip, bit, val);
1778 else {
1779 __nmk_gpio_make_input(nmk_chip, bit);
1780 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1781 }
1782 /* TODO: isn't this only applicable on output pins? */
1783 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1784
1785 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1786 clk_disable(nmk_chip->clk);
1787 } /* for each config */
1788
1789 return 0;
1790 }
1791
1792 static const struct pinconf_ops nmk_pinconf_ops = {
1793 .pin_config_get = nmk_pin_config_get,
1794 .pin_config_set = nmk_pin_config_set,
1795 };
1796
1797 static struct pinctrl_desc nmk_pinctrl_desc = {
1798 .name = "pinctrl-nomadik",
1799 .pctlops = &nmk_pinctrl_ops,
1800 .pmxops = &nmk_pinmux_ops,
1801 .confops = &nmk_pinconf_ops,
1802 .owner = THIS_MODULE,
1803 };
1804
1805 static const struct of_device_id nmk_pinctrl_match[] = {
1806 {
1807 .compatible = "stericsson,stn8815-pinctrl",
1808 .data = (void *)PINCTRL_NMK_STN8815,
1809 },
1810 {
1811 .compatible = "stericsson,db8500-pinctrl",
1812 .data = (void *)PINCTRL_NMK_DB8500,
1813 },
1814 {},
1815 };
1816
1817 #ifdef CONFIG_PM_SLEEP
nmk_pinctrl_suspend(struct device * dev)1818 static int nmk_pinctrl_suspend(struct device *dev)
1819 {
1820 struct nmk_pinctrl *npct;
1821
1822 npct = dev_get_drvdata(dev);
1823 if (!npct)
1824 return -EINVAL;
1825
1826 return pinctrl_force_sleep(npct->pctl);
1827 }
1828
nmk_pinctrl_resume(struct device * dev)1829 static int nmk_pinctrl_resume(struct device *dev)
1830 {
1831 struct nmk_pinctrl *npct;
1832
1833 npct = dev_get_drvdata(dev);
1834 if (!npct)
1835 return -EINVAL;
1836
1837 return pinctrl_force_default(npct->pctl);
1838 }
1839 #endif
1840
nmk_pinctrl_probe(struct platform_device * pdev)1841 static int nmk_pinctrl_probe(struct platform_device *pdev)
1842 {
1843 const struct of_device_id *match;
1844 struct device_node *np = pdev->dev.of_node;
1845 struct device_node *prcm_np;
1846 struct nmk_pinctrl *npct;
1847 unsigned int version = 0;
1848 int i;
1849
1850 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1851 if (!npct)
1852 return -ENOMEM;
1853
1854 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1855 if (!match)
1856 return -ENODEV;
1857 version = (unsigned int) match->data;
1858
1859 /* Poke in other ASIC variants here */
1860 if (version == PINCTRL_NMK_STN8815)
1861 nmk_pinctrl_stn8815_init(&npct->soc);
1862 if (version == PINCTRL_NMK_DB8500)
1863 nmk_pinctrl_db8500_init(&npct->soc);
1864
1865 /*
1866 * Since we depend on the GPIO chips to provide clock and register base
1867 * for the pin control operations, make sure that we have these
1868 * populated before we continue. Follow the phandles to instantiate
1869 * them. The GPIO portion of the actual hardware may be probed before
1870 * or after this point: it shouldn't matter as the APIs are orthogonal.
1871 */
1872 for (i = 0; i < NMK_MAX_BANKS; i++) {
1873 struct device_node *gpio_np;
1874 struct nmk_gpio_chip *nmk_chip;
1875
1876 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1877 if (gpio_np) {
1878 dev_info(&pdev->dev,
1879 "populate NMK GPIO %d \"%pOFn\"\n",
1880 i, gpio_np);
1881 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1882 if (IS_ERR(nmk_chip))
1883 dev_err(&pdev->dev,
1884 "could not populate nmk chip struct "
1885 "- continue anyway\n");
1886 of_node_put(gpio_np);
1887 }
1888 }
1889
1890 prcm_np = of_parse_phandle(np, "prcm", 0);
1891 if (prcm_np) {
1892 npct->prcm_base = of_iomap(prcm_np, 0);
1893 of_node_put(prcm_np);
1894 }
1895 if (!npct->prcm_base) {
1896 if (version == PINCTRL_NMK_STN8815) {
1897 dev_info(&pdev->dev,
1898 "No PRCM base, "
1899 "assuming no ALT-Cx control is available\n");
1900 } else {
1901 dev_err(&pdev->dev, "missing PRCM base address\n");
1902 return -EINVAL;
1903 }
1904 }
1905
1906 nmk_pinctrl_desc.pins = npct->soc->pins;
1907 nmk_pinctrl_desc.npins = npct->soc->npins;
1908 npct->dev = &pdev->dev;
1909
1910 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1911 if (IS_ERR(npct->pctl)) {
1912 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1913 return PTR_ERR(npct->pctl);
1914 }
1915
1916 platform_set_drvdata(pdev, npct);
1917 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1918
1919 return 0;
1920 }
1921
1922 static const struct of_device_id nmk_gpio_match[] = {
1923 { .compatible = "st,nomadik-gpio", },
1924 {}
1925 };
1926
1927 static struct platform_driver nmk_gpio_driver = {
1928 .driver = {
1929 .name = "gpio",
1930 .of_match_table = nmk_gpio_match,
1931 },
1932 .probe = nmk_gpio_probe,
1933 };
1934
1935 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1936 nmk_pinctrl_suspend,
1937 nmk_pinctrl_resume);
1938
1939 static struct platform_driver nmk_pinctrl_driver = {
1940 .driver = {
1941 .name = "pinctrl-nomadik",
1942 .of_match_table = nmk_pinctrl_match,
1943 .pm = &nmk_pinctrl_pm_ops,
1944 },
1945 .probe = nmk_pinctrl_probe,
1946 };
1947
nmk_gpio_init(void)1948 static int __init nmk_gpio_init(void)
1949 {
1950 return platform_driver_register(&nmk_gpio_driver);
1951 }
1952 subsys_initcall(nmk_gpio_init);
1953
nmk_pinctrl_init(void)1954 static int __init nmk_pinctrl_init(void)
1955 {
1956 return platform_driver_register(&nmk_pinctrl_driver);
1957 }
1958 core_initcall(nmk_pinctrl_init);
1959