| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/cmsis/inc/ |
| D | core_cm0.h | 348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm1.h | 348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm0plus.h | 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_sc000.h | 359 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_armv8mbl.h | 394 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_sc300.h | 386 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm3.h | 386 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm23.h | 394 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm4.h | 456 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm7.h | 467 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_armv8mml.h | 511 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm33.h | 517 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm35p.h | 511 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_armv81mml.h | 518 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm55.h | 523 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/ |
| D | hal_trace.c | 197 uint32_t CCR; member
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| /device/soc/asrmicro/asr582x/liteos_m/sdk/drivers/driver/inc/ |
| D | duet.h | 288 __IO uint32_t CCR; // 0x10 member
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| /device/soc/st/stm32f4xx/sdk/Drivers/CMSIS/Include/ |
| D | core_cm4.h | 447 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| /device/soc/chipsea/cst85/liteos_m/sdk/bsp/arch/cmsis/ |
| D | core_cm4.h | 447 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| /device/soc/asrmicro/asr582x/liteos_m/sdk/drivers/platform/CMSIS/Include/ |
| D | core_cm4.h | 443 …__IOM uint32_t CCR; /* !< Offset: 0x014 (R/W) Configuration Control Register */ member
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| /device/soc/st/stm32f407zg/uniproton/board/common/ |
| D | stm32f4xx.h | 558 …__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base … member
1036 __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ member
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| /device/soc/st/common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/ |
| D | stm32mp157axx_ca7.h | 351 …__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ member
528 …__IO uint32_t CCR; /*!< DAC calibration control register, Address offs… member
665 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ member
713 …__IO uint32_t CCR; /*!< MDMA channel x control register, Address offse… member
734 …__IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Addre… member
1242 …__IO uint32_t CCR; /*VREF control and status register Address … member
2261 …__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0… member
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| /device/soc/st/stm32f4xx/sdk/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ |
| D | stm32f407xx.h | 206 …__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base … member
566 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ member
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