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1 /**
2   ******************************************************************************
3   * @file    stm32f4xx.h
4   * @author  MCD Application Team
5   * @version V1.4.0
6   * @date    04-August-2014
7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
8   *          This file contains all the peripheral register's definitions, bits
9   *          definitions and memory mapping for STM32F4xx devices.
10   *
11   *          The file is the unique include file that the application programmer
12   *          is using in the C source code, usually in main.c. This file contains:
13   *           - Configuration section that allows to select:
14   *              - The device used in the target application
15   *              - To use or not the peripheral�s drivers in application code(i.e.
16   *                code will be based on direct access to peripheral�s registers
17   *                rather than drivers API), this option is controlled by
18   *                "#define USE_STDPERIPH_DRIVER"
19   *              - To change few application-specific parameters such as the HSE
20   *                crystal frequency
21   *           - Data structures and the address mapping for all peripherals
22   *           - Peripheral's registers declarations and bits definition
23   *           - Macros to access peripheral�s registers hardware
24   *
25   ******************************************************************************
26   * @attention
27   *
28   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
29   *
30   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
31   * You may not use this file except in compliance with the License.
32   * You may obtain a copy of the License at:
33   *
34   *        http://www.st.com/software_license_agreement_liberty_v2
35   *
36   * Unless required by applicable law or agreed to in writing, software
37   * distributed under the License is distributed on an "AS IS" BASIS,
38   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
39   * See the License for the specific language governing permissions and
40   * limitations under the License.
41   *
42   ******************************************************************************
43   */
44 
45 /** @addtogroup CMSIS
46   * @{
47   */
48 
49 /** @addtogroup stm32f4xx
50   * @{
51   */
52 
53 #ifndef __STM32F4xx_H
54 #define __STM32F4xx_H
55 
56 #ifdef __cplusplus
57  extern "C" {
58 #endif /* __cplusplus */
59 
60 /** @addtogroup Library_configuration_section
61   * @{
62   */
63 
64 /* Uncomment the line below according to the target STM32 device used in your
65    application
66   */
67 
68 #if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
69   /* #define STM32F40_41xxx */   /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,
70                                       STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE,
71                                       STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
72 
73   /* #define STM32F427_437xx */  /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,
74                                       STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
75 
76   /* #define STM32F429_439xx */  /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,
77                                       STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI,
78                                       STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
79                                       STM32F439IG and STM32F439II Devices */
80 
81   /* #define STM32F401xx */      /*!< STM32F401CB, STM32F401CC,  STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC
82                                       STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */
83 
84   /* #define STM32F411xE */      /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
85 #endif
86 
87 /* Old STM32F40XX definition, maintained for legacy purpose */
88 #ifdef STM32F40XX
89   #define STM32F40_41xxx
90 #endif /* STM32F40XX */
91 
92 /* Old STM32F427X definition, maintained for legacy purpose */
93 #ifdef STM32F427X
94   #define STM32F427_437xx
95 #endif /* STM32F427X */
96 
97 /*  Tip: To avoid modifying this file each time you need to switch between these
98         devices, you can define the device in your toolchain compiler preprocessor.
99   */
100 
101 #if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
102  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
103 #endif
104 
105 #if !defined  (USE_STDPERIPH_DRIVER)
106 /**
107  * @brief Comment the line below if you will not use the peripherals drivers.
108    In this case, these drivers will not be included and the application code will
109    be based on direct access to peripherals registers
110    */
111 #ifdef DRIVERS_HDF
112 #define USE_STDPERIPH_DRIVER
113 #endif
114 #endif /* USE_STDPERIPH_DRIVER */
115 
116 /**
117  * @brief In the following line adjust the value of External High Speed oscillator (HSE)
118    used in your application
119 
120    Tip: To avoid modifying this file each time you need to use different HSE, you
121         can define the HSE value in your toolchain compiler preprocessor.
122   */
123 
124 #if !defined  (HSE_VALUE)
125   #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
126 
127 #endif /* HSE_VALUE */
128 
129 /**
130  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
131    Timeout value
132    */
133 #if !defined  (HSE_STARTUP_TIMEOUT)
134   #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x05000)   /*!< Time out for HSE start up */
135 #endif /* HSE_STARTUP_TIMEOUT */
136 
137 #if !defined  (HSI_VALUE)
138   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
139 #endif /* HSI_VALUE */
140 
141 /**
142  * @brief STM32F4XX Standard Peripherals Library version number V1.4.0
143    */
144 #define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
145 #define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
146 #define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
147 #define __STM32F4XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
148 #define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
149                                              |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
150                                              |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
151                                              |(__STM32F4XX_STDPERIPH_VERSION_RC))
152 
153 /**
154   * @}
155   */
156 
157 /** @addtogroup Configuration_section_for_CMSIS
158   * @{
159   */
160 
161 /**
162  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
163  */
164 #define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
165 #define __MPU_PRESENT             1       /*!< STM32F4XX provides an MPU                     */
166 #define __NVIC_PRIO_BITS          4       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
167 #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
168 #define __FPU_PRESENT             1       /*!< FPU present                                   */
169 
170 /**
171  * @brief STM32F4XX Interrupt Number Definition, according to the selected device
172  *        in @ref Library_configuration_section
173  */
174 typedef enum IRQn
175 {
176 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
177   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
178   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
179   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
180   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
181   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
182   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
183   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
184   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
185 /******  STM32 specific Interrupt Numbers **********************************************************************/
186   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
187   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
188   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
189   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
190   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
191   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
192   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
193   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
194   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
195   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
196   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
197   DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
198   DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
199   DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
200   DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
201   DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
202   DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
203   DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
204   ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
205 
206 #if defined (STM32F40_41xxx)
207   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
208   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
209   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
210   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
211   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
212   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
213   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
214   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
215   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
216   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
217   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
218   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
219   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
220   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
221   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
222   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
223   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
224   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
225   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
226   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
227   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
228   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
229   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
230   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
231   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
232   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
233   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
234   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
235   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
236   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
237   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
238   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
239   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
240   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
241   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
242   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
243   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
244   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
245   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
246   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
247   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
248   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
249   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
250   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
251   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
252   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
253   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
254   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
255   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
256   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
257   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
258   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
259   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
260   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
261   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
262   OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
263   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
264   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
265   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
266   DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
267   CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
268   HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
269   FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
270 #endif /* STM32F40_41xxx */
271 
272 // #if defined (STM32F427_437xx)
273 //   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
274 //   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
275 //   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
276 //   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
277 //   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
278 //   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
279 //   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
280 //   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
281 //   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
282 //   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
283 //   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
284 //   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
285 //   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
286 //   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
287 //   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
288 //   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
289 //   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
290 //   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
291 //   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
292 //   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
293 //   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
294 //   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
295 //   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
296 //   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
297 //   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
298 //   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
299 //   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
300 //   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
301 //   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
302 //   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
303 //   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
304 //   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
305 //   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
306 //   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
307 //   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
308 //   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
309 //   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
310 //   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
311 //   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
312 //   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
313 //   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
314 //   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
315 //   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
316 //   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
317 //   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
318 //   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
319 //   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
320 //   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
321 //   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
322 //   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
323 //   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
324 //   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
325 //   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
326 //   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
327 //   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
328 //   OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
329 //   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
330 //   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
331 //   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
332 //   DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
333 //   CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
334 //   HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
335 //   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
336 //   UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
337 //   UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
338 //   SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
339 //   SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
340 //   SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
341 //   SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
342 //   DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
343 // #endif /* STM32F427_437xx */
344 
345 // #if defined (STM32F429_439xx)
346 //   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
347 //   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
348 //   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
349 //   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
350 //   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
351 //   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
352 //   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
353 //   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
354 //   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
355 //   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
356 //   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
357 //   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
358 //   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
359 //   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
360 //   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
361 //   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
362 //   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
363 //   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
364 //   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
365 //   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
366 //   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
367 //   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
368 //   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
369 //   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
370 //   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
371 //   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
372 //   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
373 //   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
374 //   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
375 //   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
376 //   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
377 //   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
378 //   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
379 //   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
380 //   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
381 //   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
382 //   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
383 //   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
384 //   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
385 //   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
386 //   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
387 //   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
388 //   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
389 //   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
390 //   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
391 //   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
392 //   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
393 //   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
394 //   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
395 //   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
396 //   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
397 //   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
398 //   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
399 //   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
400 //   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
401 //   OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
402 //   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
403 //   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
404 //   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
405 //   DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
406 //   CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
407 //   HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
408 //   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
409 //   UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
410 //   UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
411 //   SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
412 //   SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
413 //   SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
414 //   SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
415 //   LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
416 //   LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
417 //   DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
418 // #endif /* STM32F429_439xx */
419 
420 #if defined (STM32F401xx) || defined (STM32F411xE)
421   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
422   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
423   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
424   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
425   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
426   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
427   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
428   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
429   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
430   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
431   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
432   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
433   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
434   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
435   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
436   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
437   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
438   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
439   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
440   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
441   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
442   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
443   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
444   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
445   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
446   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
447   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
448   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
449   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
450   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
451   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
452   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
453   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
454   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
455   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
456   FPU_IRQn                    = 81,      /*!< FPU global interrupt                                             */
457 #if defined (STM32F401xx)
458   SPI4_IRQn                   = 84       /*!< SPI4 global Interrupt                                            */
459 #endif /* STM32F411xE */
460 #if defined (STM32F411xE)
461   SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
462   SPI5_IRQn                   = 85      /*!< SPI5 global Interrupt                                             */
463 #endif /* STM32F411xE */
464 #endif /* STM32F401xx || STM32F411xE */
465 
466 } IRQn_Type;
467 
468 /**
469   * @}
470   */
471 
472 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
473 #include "system_stm32f4xx.h"
474 #include <stdint.h>
475 
476 /** @addtogroup Exported_types
477   * @{
478   */
479 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
480 typedef int32_t  s32;
481 typedef int16_t s16;
482 typedef int8_t  s8;
483 
484 typedef const int32_t sc32;  /*!< Read Only */
485 typedef const int16_t sc16;  /*!< Read Only */
486 typedef const int8_t sc8;   /*!< Read Only */
487 
488 typedef __IO int32_t  vs32;
489 typedef __IO int16_t  vs16;
490 typedef __IO int8_t   vs8;
491 
492 typedef __I int32_t vsc32;  /*!< Read Only */
493 typedef __I int16_t vsc16;  /*!< Read Only */
494 typedef __I int8_t vsc8;   /*!< Read Only */
495 
496 typedef uint32_t  u32;
497 typedef uint16_t u16;
498 typedef uint8_t  u8;
499 
500 typedef const uint32_t uc32;  /*!< Read Only */
501 typedef const uint16_t uc16;  /*!< Read Only */
502 typedef const uint8_t uc8;   /*!< Read Only */
503 
504 typedef __IO uint32_t  vu32;
505 typedef __IO uint16_t vu16;
506 typedef __IO uint8_t  vu8;
507 
508 typedef __I uint32_t vuc32;  /*!< Read Only */
509 typedef __I uint16_t vuc16;  /*!< Read Only */
510 typedef __I uint8_t vuc8;   /*!< Read Only */
511 
512 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
513 
514 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
515 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
516 
517 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
518 
519 /**
520   * @}
521   */
522 
523 /** @addtogroup Peripheral_registers_structures
524   * @{
525   */
526 
527 /**
528   * @brief Analog to Digital Converter
529   */
530 
531 typedef struct
532 {
533   __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
534   __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
535   __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
536   __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
537   __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
538   __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
539   __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
540   __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
541   __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
542   __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
543   __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
544   __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
545   __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
546   __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
547   __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
548   __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
549   __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
550   __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
551   __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
552   __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
553 } ADC_TypeDef;
554 
555 typedef struct
556 {
557   __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
558   __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
559   __IO uint32_t CDR;    /*!< ADC common regular data register for dual
560                              AND triple modes,                            Address offset: ADC1 base address + 0x308 */
561 } ADC_Common_TypeDef;
562 
563 
564 /**
565   * @brief Controller Area Network TxMailBox
566   */
567 
568 typedef struct
569 {
570   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
571   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
572   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
573   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
574 } CAN_TxMailBox_TypeDef;
575 
576 /**
577   * @brief Controller Area Network FIFOMailBox
578   */
579 
580 typedef struct
581 {
582   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
583   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
584   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
585   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
586 } CAN_FIFOMailBox_TypeDef;
587 
588 /**
589   * @brief Controller Area Network FilterRegister
590   */
591 
592 typedef struct
593 {
594   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
595   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
596 } CAN_FilterRegister_TypeDef;
597 
598 /**
599   * @brief Controller Area Network
600   */
601 
602 typedef struct
603 {
604   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
605   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
606   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
607   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
608   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
609   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
610   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
611   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
612   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
613   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
614   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
615   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
616   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
617   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
618   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
619   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
620   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
621   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
622   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
623   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
624   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
625   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
626 } CAN_TypeDef;
627 
628 /**
629   * @brief CRC calculation unit
630   */
631 
632 typedef struct
633 {
634   __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
635   __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
636   uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
637   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
638   __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
639 } CRC_TypeDef;
640 
641 /**
642   * @brief Digital to Analog Converter
643   */
644 
645 typedef struct
646 {
647   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
648   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
649   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
650   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
651   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
652   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
653   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
654   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
655   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
656   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
657   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
658   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
659   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
660   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
661 } DAC_TypeDef;
662 
663 /**
664   * @brief Debug MCU
665   */
666 
667 typedef struct
668 {
669   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
670   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
671   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
672   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
673 }DBGMCU_TypeDef;
674 
675 /**
676   * @brief DCMI
677   */
678 
679 typedef struct
680 {
681   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
682   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
683   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
684   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
685   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
686   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
687   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
688   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
689   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
690   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
691   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
692 } DCMI_TypeDef;
693 
694 /**
695   * @brief DMA Controller
696   */
697 
698 typedef struct
699 {
700   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
701   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
702   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
703   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
704   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
705   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
706 } DMA_Stream_TypeDef;
707 
708 typedef struct
709 {
710   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
711   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
712   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
713   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
714 } DMA_TypeDef;
715 
716 /**
717   * @brief DMA2D Controller
718   */
719 
720 typedef struct
721 {
722   __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
723   __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
724   __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
725   __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
726   __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
727   __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
728   __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
729   __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
730   __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
731   __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
732   __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
733   __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
734   __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
735   __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
736   __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
737   __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
738   __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
739   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
740   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
741   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
742   uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
743   __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
744   __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
745 } DMA2D_TypeDef;
746 
747 /**
748   * @brief Ethernet MAC
749   */
750 
751 typedef struct
752 {
753   __IO uint32_t MACCR;
754   __IO uint32_t MACFFR;
755   __IO uint32_t MACHTHR;
756   __IO uint32_t MACHTLR;
757   __IO uint32_t MACMIIAR;
758   __IO uint32_t MACMIIDR;
759   __IO uint32_t MACFCR;
760   __IO uint32_t MACVLANTR;             /*    8 */
761   uint32_t      RESERVED0[2];
762   __IO uint32_t MACRWUFFR;             /*   11 */
763   __IO uint32_t MACPMTCSR;
764   uint32_t      RESERVED1[2];
765   __IO uint32_t MACSR;                 /*   15 */
766   __IO uint32_t MACIMR;
767   __IO uint32_t MACA0HR;
768   __IO uint32_t MACA0LR;
769   __IO uint32_t MACA1HR;
770   __IO uint32_t MACA1LR;
771   __IO uint32_t MACA2HR;
772   __IO uint32_t MACA2LR;
773   __IO uint32_t MACA3HR;
774   __IO uint32_t MACA3LR;               /*   24 */
775   uint32_t      RESERVED2[40];
776   __IO uint32_t MMCCR;                 /*   65 */
777   __IO uint32_t MMCRIR;
778   __IO uint32_t MMCTIR;
779   __IO uint32_t MMCRIMR;
780   __IO uint32_t MMCTIMR;               /*   69 */
781   uint32_t      RESERVED3[14];
782   __IO uint32_t MMCTGFSCCR;            /*   84 */
783   __IO uint32_t MMCTGFMSCCR;
784   uint32_t      RESERVED4[5];
785   __IO uint32_t MMCTGFCR;
786   uint32_t      RESERVED5[10];
787   __IO uint32_t MMCRFCECR;
788   __IO uint32_t MMCRFAECR;
789   uint32_t      RESERVED6[10];
790   __IO uint32_t MMCRGUFCR;
791   uint32_t      RESERVED7[334];
792   __IO uint32_t PTPTSCR;
793   __IO uint32_t PTPSSIR;
794   __IO uint32_t PTPTSHR;
795   __IO uint32_t PTPTSLR;
796   __IO uint32_t PTPTSHUR;
797   __IO uint32_t PTPTSLUR;
798   __IO uint32_t PTPTSAR;
799   __IO uint32_t PTPTTHR;
800   __IO uint32_t PTPTTLR;
801   __IO uint32_t RESERVED8;
802   __IO uint32_t PTPTSSR;
803   uint32_t      RESERVED9[565];
804   __IO uint32_t DMABMR;
805   __IO uint32_t DMATPDR;
806   __IO uint32_t DMARPDR;
807   __IO uint32_t DMARDLAR;
808   __IO uint32_t DMATDLAR;
809   __IO uint32_t DMASR;
810   __IO uint32_t DMAOMR;
811   __IO uint32_t DMAIER;
812   __IO uint32_t DMAMFBOCR;
813   __IO uint32_t DMARSWTR;
814   uint32_t      RESERVED10[8];
815   __IO uint32_t DMACHTDR;
816   __IO uint32_t DMACHRDR;
817   __IO uint32_t DMACHTBAR;
818   __IO uint32_t DMACHRBAR;
819 } ETH_TypeDef;
820 
821 /**
822   * @brief External Interrupt/Event Controller
823   */
824 
825 typedef struct
826 {
827   __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
828   __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
829   __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
830   __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
831   __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
832   __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
833 } EXTI_TypeDef;
834 
835 /**
836   * @brief FLASH Registers
837   */
838 
839 typedef struct
840 {
841   __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
842   __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
843   __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
844   __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
845   __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
846   __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
847   __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
848 } FLASH_TypeDef;
849 
850 #if defined (STM32F40_41xxx)
851 /**
852   * @brief Flexible Static Memory Controller
853   */
854 
855 typedef struct
856 {
857   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
858 } FSMC_Bank1_TypeDef;
859 
860 /**
861   * @brief Flexible Static Memory Controller Bank1E
862   */
863 
864 typedef struct
865 {
866   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
867 } FSMC_Bank1E_TypeDef;
868 
869 /**
870   * @brief Flexible Static Memory Controller Bank2
871   */
872 
873 typedef struct
874 {
875   __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
876   __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
877   __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
878   __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
879   uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
880   __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
881 } FSMC_Bank2_TypeDef;
882 
883 /**
884   * @brief Flexible Static Memory Controller Bank3
885   */
886 
887 typedef struct
888 {
889   __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
890   __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
891   __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
892   __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
893   uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
894   __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
895 } FSMC_Bank3_TypeDef;
896 
897 /**
898   * @brief Flexible Static Memory Controller Bank4
899   */
900 
901 typedef struct
902 {
903   __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
904   __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
905   __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
906   __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
907   __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
908 } FSMC_Bank4_TypeDef;
909 #endif /* STM32F40_41xxx */
910 
911 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
912 /**
913   * @brief Flexible Memory Controller
914   */
915 
916 typedef struct
917 {
918   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
919 } FMC_Bank1_TypeDef;
920 
921 /**
922   * @brief Flexible Memory Controller Bank1E
923   */
924 
925 typedef struct
926 {
927   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
928 } FMC_Bank1E_TypeDef;
929 
930 /**
931   * @brief Flexible Memory Controller Bank2
932   */
933 
934 typedef struct
935 {
936   __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
937   __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
938   __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
939   __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
940   uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
941   __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
942 } FMC_Bank2_TypeDef;
943 
944 /**
945   * @brief Flexible Memory Controller Bank3
946   */
947 
948 typedef struct
949 {
950   __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
951   __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
952   __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
953   __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
954   uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
955   __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
956 } FMC_Bank3_TypeDef;
957 
958 /**
959   * @brief Flexible Memory Controller Bank4
960   */
961 
962 typedef struct
963 {
964   __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
965   __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
966   __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
967   __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
968   __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
969 } FMC_Bank4_TypeDef;
970 
971 /**
972   * @brief Flexible Memory Controller Bank5_6
973   */
974 
975 typedef struct
976 {
977   __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
978   __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
979   __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
980   __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
981   __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
982 } FMC_Bank5_6_TypeDef;
983 #endif /* STM32F427_437xx ||  STM32F429_439xx */
984 
985 /**
986   * @brief General Purpose I/O
987   */
988 
989 typedef struct
990 {
991   __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
992   __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
993   __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
994   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
995   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
996   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
997   __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
998   __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
999   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
1000   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
1001 } GPIO_TypeDef;
1002 
1003 /**
1004   * @brief System configuration controller
1005   */
1006 
1007 typedef struct
1008 {
1009   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
1010   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
1011   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1012   uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
1013   __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
1014 } SYSCFG_TypeDef;
1015 
1016 /**
1017   * @brief Inter-integrated Circuit Interface
1018   */
1019 
1020 typedef struct
1021 {
1022   __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
1023   uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */
1024   __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
1025   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */
1026   __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
1027   uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */
1028   __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
1029   uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */
1030   __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
1031   uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */
1032   __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
1033   uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */
1034   __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
1035   uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */
1036   __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
1037   uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */
1038   __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
1039   uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */
1040   __IO uint16_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
1041   uint16_t      RESERVED9;  /*!< Reserved, 0x26                                   */
1042 } I2C_TypeDef;
1043 
1044 /**
1045   * @brief Independent WATCHDOG
1046   */
1047 
1048 typedef struct
1049 {
1050   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
1051   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
1052   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
1053   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
1054 } IWDG_TypeDef;
1055 
1056 /**
1057   * @brief LCD-TFT Display Controller
1058   */
1059 
1060 typedef struct
1061 {
1062   uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
1063   __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
1064   __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
1065   __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
1066   __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
1067   __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
1068   uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
1069   __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
1070   uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
1071   __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
1072   uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
1073   __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
1074   __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
1075   __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
1076   __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1077   __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
1078   __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
1079 } LTDC_TypeDef;
1080 
1081 /**
1082   * @brief LCD-TFT Display layer x Controller
1083   */
1084 
1085 typedef struct
1086 {
1087   __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
1088   __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1089   __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
1090   __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
1091   __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
1092   __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
1093   __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
1094   __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
1095   uint32_t      RESERVED0[2];  /*!< Reserved */
1096   __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
1097   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
1098   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
1099   uint32_t      RESERVED1[3];  /*!< Reserved */
1100   __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
1101 
1102 } LTDC_Layer_TypeDef;
1103 
1104 /**
1105   * @brief Power Control
1106   */
1107 
1108 typedef struct
1109 {
1110   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
1111   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
1112 } PWR_TypeDef;
1113 
1114 /**
1115   * @brief Reset and Clock Control
1116   */
1117 
1118 typedef struct
1119 {
1120   __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
1121   __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
1122   __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
1123   __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
1124   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
1125   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
1126   __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
1127   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
1128   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
1129   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
1130   uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
1131   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
1132   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
1133   __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
1134   uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
1135   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
1136   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
1137   uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
1138   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
1139   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
1140   __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
1141   uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
1142   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
1143   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
1144   uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
1145   __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
1146   __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
1147   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
1148   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
1149   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
1150   __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
1151   __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
1152 
1153 } RCC_TypeDef;
1154 
1155 /**
1156   * @brief Real-Time Clock
1157   */
1158 
1159 typedef struct
1160 {
1161   __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
1162   __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
1163   __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
1164   __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
1165   __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
1166   __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
1167   __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
1168   __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
1169   __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
1170   __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
1171   __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
1172   __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
1173   __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
1174   __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
1175   __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
1176   __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
1177   __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
1178   __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
1179   __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
1180   uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
1181   __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
1182   __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
1183   __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
1184   __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
1185   __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
1186   __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
1187   __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
1188   __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
1189   __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
1190   __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
1191   __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
1192   __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
1193   __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
1194   __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
1195   __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
1196   __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
1197   __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
1198   __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
1199   __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
1200   __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
1201 } RTC_TypeDef;
1202 
1203 
1204 /**
1205   * @brief Serial Audio Interface
1206   */
1207 
1208 typedef struct
1209 {
1210   __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
1211 } SAI_TypeDef;
1212 
1213 typedef struct
1214 {
1215   __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
1216   __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
1217   __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
1218   __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
1219   __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
1220   __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
1221   __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
1222   __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
1223 } SAI_Block_TypeDef;
1224 
1225 /**
1226   * @brief SD host Interface
1227   */
1228 
1229 typedef struct
1230 {
1231   __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
1232   __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
1233   __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
1234   __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
1235   __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
1236   __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
1237   __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
1238   __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
1239   __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
1240   __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
1241   __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
1242   __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
1243   __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
1244   __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
1245   __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
1246   __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
1247   uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
1248   __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
1249   uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
1250   __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
1251 } SDIO_TypeDef;
1252 
1253 /**
1254   * @brief Serial Peripheral Interface
1255   */
1256 
1257 typedef struct
1258 {
1259   __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
1260   uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
1261   __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
1262   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
1263   __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
1264   uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
1265   __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
1266   uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
1267   __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
1268   uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
1269   __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
1270   uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
1271   __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
1272   uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
1273   __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
1274   uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
1275   __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
1276   uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
1277 } SPI_TypeDef;
1278 
1279 /**
1280   * @brief TIM
1281   */
1282 
1283 typedef struct
1284 {
1285   __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
1286   uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
1287   __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
1288   uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
1289   __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
1290   uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
1291   __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
1292   uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
1293   __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
1294   uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
1295   __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
1296   uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
1297   __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1298   uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
1299   __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1300   uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
1301   __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
1302   uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
1303   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
1304   __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
1305   uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
1306   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
1307   __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
1308   uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
1309   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
1310   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
1311   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
1312   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
1313   __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
1314   uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
1315   __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
1316   uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
1317   __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
1318   uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
1319   __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
1320   uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
1321 } TIM_TypeDef;
1322 
1323 /**
1324   * @brief Universal Synchronous Asynchronous Receiver Transmitter
1325   */
1326 
1327 typedef struct
1328 {
1329   __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
1330   uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
1331   __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
1332   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
1333   __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
1334   uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
1335   __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
1336   uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
1337   __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
1338   uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
1339   __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
1340   uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
1341   __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
1342   uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
1343 } USART_TypeDef;
1344 
1345 /**
1346   * @brief Window WATCHDOG
1347   */
1348 
1349 typedef struct
1350 {
1351   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
1352   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
1353   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
1354 } WWDG_TypeDef;
1355 
1356 /**
1357   * @brief Crypto Processor
1358   */
1359 
1360 typedef struct
1361 {
1362   __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
1363   __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
1364   __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
1365   __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
1366   __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
1367   __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
1368   __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
1369   __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
1370   __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
1371   __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
1372   __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
1373   __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
1374   __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
1375   __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
1376   __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
1377   __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
1378   __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
1379   __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
1380   __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
1381   __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
1382   __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
1383   __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
1384   __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
1385   __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
1386   __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
1387   __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
1388   __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
1389   __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
1390   __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
1391   __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
1392   __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
1393   __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
1394   __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
1395   __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
1396   __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
1397   __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
1398 } CRYP_TypeDef;
1399 
1400 /**
1401   * @brief HASH
1402   */
1403 
1404 typedef struct
1405 {
1406   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
1407   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
1408   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
1409   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
1410   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
1411   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
1412        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
1413   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
1414 } HASH_TypeDef;
1415 
1416 /**
1417   * @brief HASH_DIGEST
1418   */
1419 
1420 typedef struct
1421 {
1422   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
1423 } HASH_DIGEST_TypeDef;
1424 
1425 /**
1426   * @brief RNG
1427   */
1428 
1429 typedef struct
1430 {
1431   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
1432   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
1433   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
1434 } RNG_TypeDef;
1435 
1436 /**
1437   * @}
1438   */
1439 
1440 /** @addtogroup Peripheral_memory_map
1441   * @{
1442   */
1443 #define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
1444 #define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
1445 #define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
1446 #define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
1447 #define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */
1448 #define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
1449 #define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
1450 
1451 #if defined (STM32F40_41xxx)
1452 #define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
1453 #endif /* STM32F40_41xxx */
1454 
1455 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
1456 #define FMC_R_BASE            ((uint32_t)0xA0000000) /*!< FMC registers base address                                                 */
1457 #endif /* STM32F427_437xx ||  STM32F429_439xx */
1458 
1459 #define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */
1460 #define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
1461 #define SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
1462 #define SRAM3_BB_BASE         ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region                              */
1463 #define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
1464 #define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
1465 
1466 /* Legacy defines */
1467 #define SRAM_BASE             SRAM1_BASE
1468 #define SRAM_BB_BASE          SRAM1_BB_BASE
1469 
1470 
1471 /*!< Peripheral memory map */
1472 #define APB1PERIPH_BASE       PERIPH_BASE
1473 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
1474 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
1475 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
1476 
1477 /*!< APB1 peripherals */
1478 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
1479 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
1480 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
1481 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
1482 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
1483 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
1484 #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
1485 #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
1486 #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
1487 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
1488 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
1489 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
1490 #define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
1491 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
1492 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
1493 #define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
1494 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
1495 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
1496 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
1497 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
1498 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
1499 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
1500 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
1501 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
1502 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
1503 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
1504 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
1505 #define UART7_BASE            (APB1PERIPH_BASE + 0x7800)
1506 #define UART8_BASE            (APB1PERIPH_BASE + 0x7C00)
1507 
1508 /*!< APB2 peripherals */
1509 #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
1510 #define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
1511 #define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
1512 #define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
1513 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
1514 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
1515 #define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
1516 #define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
1517 #define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
1518 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
1519 #define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)
1520 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
1521 #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
1522 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
1523 #define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
1524 #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
1525 #define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
1526 #define SPI6_BASE             (APB2PERIPH_BASE + 0x5400)
1527 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5800)
1528 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
1529 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
1530 #define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
1531 #define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
1532 #define LTDC_Layer2_BASE      (LTDC_BASE + 0x104)
1533 
1534 /*!< AHB1 peripherals */
1535 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
1536 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
1537 #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
1538 #define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
1539 #define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
1540 #define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
1541 #define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
1542 #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
1543 #define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
1544 #define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)
1545 #define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)
1546 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
1547 #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
1548 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
1549 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
1550 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
1551 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
1552 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
1553 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
1554 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
1555 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
1556 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
1557 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
1558 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
1559 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
1560 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
1561 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
1562 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
1563 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
1564 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
1565 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
1566 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
1567 #define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
1568 #define ETH_MAC_BASE          (ETH_BASE)
1569 #define ETH_MMC_BASE          (ETH_BASE + 0x0100)
1570 #define ETH_PTP_BASE          (ETH_BASE + 0x0700)
1571 #define ETH_DMA_BASE          (ETH_BASE + 0x1000)
1572 #define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000)
1573 
1574 /*!< AHB2 peripherals */
1575 #define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
1576 #define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
1577 #define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
1578 #define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710)
1579 #define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
1580 
1581 #if defined (STM32F40_41xxx)
1582 /*!< FSMC Bankx registers base address */
1583 #define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
1584 #define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
1585 #define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
1586 #define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
1587 #define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
1588 #endif /* STM32F40_41xxx */
1589 
1590 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
1591 /*!< FMC Bankx registers base address */
1592 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)
1593 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)
1594 #define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060)
1595 #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080)
1596 #define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0)
1597 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)
1598 #endif /* STM32F427_437xx ||  STM32F429_439xx */
1599 
1600 /* Debug MCU registers base address */
1601 #define DBGMCU_BASE           ((uint32_t )0xE0042000)
1602 
1603 /**
1604   * @}
1605   */
1606 
1607 /** @addtogroup Peripheral_declaration
1608   * @{
1609   */
1610 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1611 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1612 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1613 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1614 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1615 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1616 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
1617 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
1618 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
1619 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1620 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1621 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1622 #define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
1623 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1624 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1625 #define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
1626 #define USART2              ((USART_TypeDef *) USART2_BASE)
1627 #define USART3              ((USART_TypeDef *) USART3_BASE)
1628 #define UART4               ((USART_TypeDef *) UART4_BASE)
1629 #define UART5               ((USART_TypeDef *) UART5_BASE)
1630 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1631 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1632 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1633 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1634 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1635 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1636 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
1637 #define UART7               ((USART_TypeDef *) UART7_BASE)
1638 #define UART8               ((USART_TypeDef *) UART8_BASE)
1639 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1640 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1641 #define USART1              ((USART_TypeDef *) USART1_BASE)
1642 #define USART6              ((USART_TypeDef *) USART6_BASE)
1643 #define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
1644 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1645 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1646 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1647 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
1648 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1649 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1650 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1651 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1652 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
1653 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
1654 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
1655 #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
1656 #define SPI6                ((SPI_TypeDef *) SPI6_BASE)
1657 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1658 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1659 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1660 #define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
1661 #define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1662 #define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1663 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1664 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1665 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1666 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1667 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1668 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1669 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1670 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1671 #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
1672 #define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
1673 #define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
1674 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1675 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1676 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1677 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1678 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1679 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1680 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1681 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1682 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1683 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1684 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1685 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1686 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1687 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1688 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1689 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1690 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1691 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1692 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1693 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1694 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1695 #define ETH                 ((ETH_TypeDef *) ETH_BASE)
1696 #define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
1697 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
1698 #define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
1699 #define HASH                ((HASH_TypeDef *) HASH_BASE)
1700 #define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1701 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1702 
1703 #if defined (STM32F40_41xxx)
1704 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1705 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1706 #define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1707 #define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1708 #define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1709 #endif /* STM32F40_41xxx */
1710 
1711 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
1712 #define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1713 #define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1714 #define FMC_Bank2           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
1715 #define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1716 #define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1717 #define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1718 #endif /* STM32F427_437xx ||  STM32F429_439xx */
1719 
1720 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1721 
1722 /**
1723   * @}
1724   */
1725 
1726 /** @addtogroup Exported_constants
1727   * @{
1728   */
1729 
1730   /** @addtogroup Peripheral_Registers_Bits_Definition
1731   * @{
1732   */
1733 
1734 /******************************************************************************/
1735 /*                         Peripheral Registers_Bits_Definition               */
1736 /******************************************************************************/
1737 
1738 /******************************************************************************/
1739 /*                                                                            */
1740 /*                        Analog to Digital Converter                         */
1741 /*                                                                            */
1742 /******************************************************************************/
1743 /********************  Bit definition for ADC_SR register  ********************/
1744 #define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag               */
1745 #define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion                  */
1746 #define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */
1747 #define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag        */
1748 #define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag         */
1749 #define  ADC_SR_OVR                          ((uint8_t)0x20)               /*!<Overrun flag                       */
1750 
1751 /*******************  Bit definition for ADC_CR1 register  ********************/
1752 #define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1753 #define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
1754 #define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
1755 #define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
1756 #define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
1757 #define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
1758 #define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC                              */
1759 #define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable                     */
1760 #define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels                */
1761 #define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode                                             */
1762 #define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode  */
1763 #define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion                   */
1764 #define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels                */
1765 #define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels               */
1766 #define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count)  */
1767 #define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
1768 #define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
1769 #define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
1770 #define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels           */
1771 #define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels            */
1772 #define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution)                            */
1773 #define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
1774 #define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
1775 #define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable                              */
1776 
1777 /*******************  Bit definition for ADC_CR2 register  ********************/
1778 #define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF             */
1779 #define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion              */
1780 #define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode          */
1781 #define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
1782 #define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection        */
1783 #define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment                     */
1784 #define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1785 #define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
1786 #define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
1787 #define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
1788 #define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
1789 #define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1790 #define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
1791 #define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
1792 #define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
1793 #define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1794 #define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
1795 #define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
1796 #define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
1797 #define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
1798 #define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1799 #define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
1800 #define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
1801 #define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
1802 
1803 /******************  Bit definition for ADC_SMPR1 register  *******************/
1804 #define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1805 #define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
1806 #define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
1807 #define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
1808 #define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1809 #define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
1810 #define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
1811 #define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
1812 #define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1813 #define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
1814 #define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
1815 #define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
1816 #define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1817 #define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
1818 #define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
1819 #define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
1820 #define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1821 #define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
1822 #define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
1823 #define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
1824 #define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1825 #define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
1826 #define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
1827 #define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
1828 #define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1829 #define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
1830 #define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
1831 #define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
1832 #define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1833 #define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
1834 #define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
1835 #define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
1836 #define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1837 #define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
1838 #define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
1839 #define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
1840 
1841 /******************  Bit definition for ADC_SMPR2 register  *******************/
1842 #define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1843 #define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
1844 #define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
1845 #define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
1846 #define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1847 #define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
1848 #define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
1849 #define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
1850 #define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1851 #define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
1852 #define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
1853 #define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
1854 #define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1855 #define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
1856 #define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
1857 #define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
1858 #define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1859 #define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
1860 #define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
1861 #define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
1862 #define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1863 #define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
1864 #define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
1865 #define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
1866 #define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1867 #define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
1868 #define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
1869 #define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
1870 #define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1871 #define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
1872 #define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
1873 #define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
1874 #define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1875 #define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
1876 #define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
1877 #define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
1878 #define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1879 #define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
1880 #define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
1881 #define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
1882 
1883 /******************  Bit definition for ADC_JOFR1 register  *******************/
1884 #define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */
1885 
1886 /******************  Bit definition for ADC_JOFR2 register  *******************/
1887 #define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */
1888 
1889 /******************  Bit definition for ADC_JOFR3 register  *******************/
1890 #define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */
1891 
1892 /******************  Bit definition for ADC_JOFR4 register  *******************/
1893 #define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */
1894 
1895 /*******************  Bit definition for ADC_HTR register  ********************/
1896 #define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */
1897 
1898 /*******************  Bit definition for ADC_LTR register  ********************/
1899 #define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */
1900 
1901 /*******************  Bit definition for ADC_SQR1 register  *******************/
1902 #define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1903 #define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
1904 #define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
1905 #define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
1906 #define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
1907 #define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
1908 #define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1909 #define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
1910 #define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
1911 #define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
1912 #define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
1913 #define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
1914 #define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1915 #define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
1916 #define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
1917 #define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
1918 #define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
1919 #define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
1920 #define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1921 #define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
1922 #define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
1923 #define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
1924 #define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
1925 #define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
1926 #define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
1927 #define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
1928 #define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
1929 #define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
1930 #define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
1931 
1932 /*******************  Bit definition for ADC_SQR2 register  *******************/
1933 #define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1934 #define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
1935 #define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
1936 #define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
1937 #define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
1938 #define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
1939 #define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1940 #define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
1941 #define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
1942 #define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
1943 #define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
1944 #define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
1945 #define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1946 #define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
1947 #define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
1948 #define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
1949 #define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
1950 #define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
1951 #define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1952 #define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
1953 #define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
1954 #define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
1955 #define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
1956 #define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
1957 #define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1958 #define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
1959 #define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
1960 #define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
1961 #define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
1962 #define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
1963 #define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1964 #define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
1965 #define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
1966 #define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
1967 #define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
1968 #define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
1969 
1970 /*******************  Bit definition for ADC_SQR3 register  *******************/
1971 #define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1972 #define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
1973 #define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
1974 #define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
1975 #define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
1976 #define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
1977 #define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1978 #define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
1979 #define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
1980 #define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
1981 #define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
1982 #define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
1983 #define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1984 #define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
1985 #define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
1986 #define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
1987 #define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
1988 #define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
1989 #define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1990 #define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
1991 #define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
1992 #define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
1993 #define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
1994 #define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
1995 #define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1996 #define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
1997 #define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
1998 #define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
1999 #define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
2000 #define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
2001 #define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
2002 #define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
2003 #define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
2004 #define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
2005 #define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
2006 #define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
2007 
2008 /*******************  Bit definition for ADC_JSQR register  *******************/
2009 #define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
2010 #define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
2011 #define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
2012 #define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
2013 #define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
2014 #define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
2015 #define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
2016 #define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
2017 #define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
2018 #define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
2019 #define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
2020 #define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
2021 #define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
2022 #define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
2023 #define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
2024 #define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
2025 #define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
2026 #define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
2027 #define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
2028 #define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
2029 #define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
2030 #define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
2031 #define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
2032 #define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
2033 #define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
2034 #define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
2035 #define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
2036 
2037 /*******************  Bit definition for ADC_JDR1 register  *******************/
2038 #define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
2039 
2040 /*******************  Bit definition for ADC_JDR2 register  *******************/
2041 #define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
2042 
2043 /*******************  Bit definition for ADC_JDR3 register  *******************/
2044 #define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
2045 
2046 /*******************  Bit definition for ADC_JDR4 register  *******************/
2047 #define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
2048 
2049 /********************  Bit definition for ADC_DR register  ********************/
2050 #define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
2051 #define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
2052 
2053 /*******************  Bit definition for ADC_CSR register  ********************/
2054 #define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
2055 #define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
2056 #define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
2057 #define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
2058 #define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
2059 #define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
2060 #define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
2061 #define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
2062 #define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
2063 #define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
2064 #define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
2065 #define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
2066 #define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
2067 #define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
2068 #define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
2069 #define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
2070 #define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
2071 #define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
2072 
2073 /*******************  Bit definition for ADC_CCR register  ********************/
2074 #define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
2075 #define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
2076 #define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
2077 #define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
2078 #define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
2079 #define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
2080 #define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
2081 #define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
2082 #define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
2083 #define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
2084 #define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
2085 #define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
2086 #define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
2087 #define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
2088 #define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
2089 #define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */
2090 #define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
2091 #define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
2092 #define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
2093 #define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
2094 
2095 /*******************  Bit definition for ADC_CDR register  ********************/
2096 #define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
2097 #define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
2098 
2099 /******************************************************************************/
2100 /*                                                                            */
2101 /*                         Controller Area Network                            */
2102 /*                                                                            */
2103 /******************************************************************************/
2104 /*!<CAN control and status registers */
2105 /*******************  Bit definition for CAN_MCR register  ********************/
2106 #define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
2107 #define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
2108 #define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
2109 #define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
2110 #define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
2111 #define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
2112 #define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
2113 #define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
2114 #define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
2115 
2116 /*******************  Bit definition for CAN_MSR register  ********************/
2117 #define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
2118 #define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
2119 #define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
2120 #define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
2121 #define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
2122 #define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
2123 #define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
2124 #define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
2125 #define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
2126 
2127 /*******************  Bit definition for CAN_TSR register  ********************/
2128 #define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
2129 #define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
2130 #define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
2131 #define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
2132 #define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
2133 #define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
2134 #define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
2135 #define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
2136 #define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
2137 #define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
2138 #define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
2139 #define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
2140 #define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
2141 #define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
2142 #define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
2143 #define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
2144 
2145 #define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
2146 #define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
2147 #define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
2148 #define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
2149 
2150 #define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
2151 #define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
2152 #define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
2153 #define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
2154 
2155 /*******************  Bit definition for CAN_RF0R register  *******************/
2156 #define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
2157 #define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
2158 #define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
2159 #define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
2160 
2161 /*******************  Bit definition for CAN_RF1R register  *******************/
2162 #define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
2163 #define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
2164 #define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
2165 #define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
2166 
2167 /********************  Bit definition for CAN_IER register  *******************/
2168 #define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
2169 #define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
2170 #define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
2171 #define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
2172 #define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
2173 #define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
2174 #define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
2175 #define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
2176 #define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
2177 #define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
2178 #define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
2179 #define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
2180 #define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
2181 #define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
2182 
2183 /********************  Bit definition for CAN_ESR register  *******************/
2184 #define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
2185 #define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
2186 #define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
2187 
2188 #define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
2189 #define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
2190 #define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
2191 #define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
2192 
2193 #define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
2194 #define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
2195 
2196 /*******************  Bit definition for CAN_BTR register  ********************/
2197 #define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
2198 #define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
2199 #define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
2200 #define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
2201 #define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
2202 #define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
2203 
2204 /*!<Mailbox registers */
2205 /******************  Bit definition for CAN_TI0R register  ********************/
2206 #define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
2207 #define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
2208 #define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
2209 #define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
2210 #define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
2211 
2212 /******************  Bit definition for CAN_TDT0R register  *******************/
2213 #define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
2214 #define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
2215 #define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
2216 
2217 /******************  Bit definition for CAN_TDL0R register  *******************/
2218 #define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
2219 #define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
2220 #define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
2221 #define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
2222 
2223 /******************  Bit definition for CAN_TDH0R register  *******************/
2224 #define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
2225 #define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
2226 #define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
2227 #define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
2228 
2229 /*******************  Bit definition for CAN_TI1R register  *******************/
2230 #define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
2231 #define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
2232 #define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
2233 #define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
2234 #define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
2235 
2236 /*******************  Bit definition for CAN_TDT1R register  ******************/
2237 #define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
2238 #define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
2239 #define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
2240 
2241 /*******************  Bit definition for CAN_TDL1R register  ******************/
2242 #define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
2243 #define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
2244 #define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
2245 #define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
2246 
2247 /*******************  Bit definition for CAN_TDH1R register  ******************/
2248 #define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
2249 #define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
2250 #define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
2251 #define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
2252 
2253 /*******************  Bit definition for CAN_TI2R register  *******************/
2254 #define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
2255 #define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
2256 #define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
2257 #define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
2258 #define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
2259 
2260 /*******************  Bit definition for CAN_TDT2R register  ******************/
2261 #define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
2262 #define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
2263 #define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
2264 
2265 /*******************  Bit definition for CAN_TDL2R register  ******************/
2266 #define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
2267 #define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
2268 #define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
2269 #define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
2270 
2271 /*******************  Bit definition for CAN_TDH2R register  ******************/
2272 #define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
2273 #define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
2274 #define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
2275 #define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
2276 
2277 /*******************  Bit definition for CAN_RI0R register  *******************/
2278 #define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
2279 #define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
2280 #define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
2281 #define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
2282 
2283 /*******************  Bit definition for CAN_RDT0R register  ******************/
2284 #define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
2285 #define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
2286 #define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
2287 
2288 /*******************  Bit definition for CAN_RDL0R register  ******************/
2289 #define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
2290 #define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
2291 #define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
2292 #define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
2293 
2294 /*******************  Bit definition for CAN_RDH0R register  ******************/
2295 #define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
2296 #define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
2297 #define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
2298 #define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
2299 
2300 /*******************  Bit definition for CAN_RI1R register  *******************/
2301 #define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
2302 #define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
2303 #define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
2304 #define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
2305 
2306 /*******************  Bit definition for CAN_RDT1R register  ******************/
2307 #define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
2308 #define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
2309 #define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
2310 
2311 /*******************  Bit definition for CAN_RDL1R register  ******************/
2312 #define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
2313 #define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
2314 #define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
2315 #define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
2316 
2317 /*******************  Bit definition for CAN_RDH1R register  ******************/
2318 #define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
2319 #define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
2320 #define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
2321 #define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
2322 
2323 /*!<CAN filter registers */
2324 /*******************  Bit definition for CAN_FMR register  ********************/
2325 #define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
2326 
2327 /*******************  Bit definition for CAN_FM1R register  *******************/
2328 #define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
2329 #define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
2330 #define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
2331 #define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
2332 #define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
2333 #define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
2334 #define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
2335 #define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
2336 #define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
2337 #define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
2338 #define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
2339 #define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
2340 #define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
2341 #define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
2342 #define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
2343 
2344 /*******************  Bit definition for CAN_FS1R register  *******************/
2345 #define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
2346 #define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
2347 #define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
2348 #define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
2349 #define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
2350 #define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
2351 #define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
2352 #define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
2353 #define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
2354 #define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
2355 #define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
2356 #define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
2357 #define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
2358 #define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
2359 #define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
2360 
2361 /******************  Bit definition for CAN_FFA1R register  *******************/
2362 #define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
2363 #define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
2364 #define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
2365 #define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
2366 #define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
2367 #define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
2368 #define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
2369 #define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
2370 #define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
2371 #define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
2372 #define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
2373 #define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
2374 #define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
2375 #define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
2376 #define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
2377 
2378 /*******************  Bit definition for CAN_FA1R register  *******************/
2379 #define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
2380 #define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
2381 #define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
2382 #define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
2383 #define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
2384 #define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
2385 #define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
2386 #define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
2387 #define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
2388 #define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
2389 #define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
2390 #define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
2391 #define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
2392 #define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
2393 #define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
2394 
2395 /*******************  Bit definition for CAN_F0R1 register  *******************/
2396 #define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2397 #define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2398 #define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2399 #define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2400 #define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2401 #define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2402 #define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2403 #define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2404 #define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2405 #define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2406 #define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2407 #define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2408 #define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2409 #define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2410 #define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2411 #define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2412 #define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2413 #define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2414 #define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2415 #define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2416 #define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2417 #define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2418 #define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2419 #define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2420 #define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2421 #define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2422 #define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2423 #define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2424 #define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2425 #define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2426 #define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2427 #define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2428 
2429 /*******************  Bit definition for CAN_F1R1 register  *******************/
2430 #define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2431 #define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2432 #define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2433 #define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2434 #define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2435 #define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2436 #define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2437 #define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2438 #define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2439 #define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2440 #define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2441 #define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2442 #define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2443 #define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2444 #define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2445 #define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2446 #define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2447 #define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2448 #define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2449 #define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2450 #define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2451 #define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2452 #define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2453 #define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2454 #define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2455 #define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2456 #define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2457 #define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2458 #define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2459 #define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2460 #define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2461 #define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2462 
2463 /*******************  Bit definition for CAN_F2R1 register  *******************/
2464 #define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2465 #define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2466 #define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2467 #define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2468 #define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2469 #define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2470 #define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2471 #define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2472 #define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2473 #define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2474 #define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2475 #define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2476 #define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2477 #define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2478 #define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2479 #define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2480 #define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2481 #define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2482 #define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2483 #define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2484 #define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2485 #define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2486 #define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2487 #define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2488 #define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2489 #define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2490 #define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2491 #define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2492 #define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2493 #define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2494 #define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2495 #define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2496 
2497 /*******************  Bit definition for CAN_F3R1 register  *******************/
2498 #define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2499 #define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2500 #define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2501 #define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2502 #define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2503 #define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2504 #define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2505 #define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2506 #define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2507 #define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2508 #define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2509 #define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2510 #define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2511 #define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2512 #define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2513 #define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2514 #define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2515 #define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2516 #define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2517 #define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2518 #define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2519 #define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2520 #define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2521 #define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2522 #define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2523 #define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2524 #define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2525 #define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2526 #define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2527 #define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2528 #define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2529 #define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2530 
2531 /*******************  Bit definition for CAN_F4R1 register  *******************/
2532 #define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2533 #define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2534 #define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2535 #define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2536 #define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2537 #define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2538 #define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2539 #define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2540 #define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2541 #define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2542 #define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2543 #define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2544 #define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2545 #define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2546 #define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2547 #define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2548 #define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2549 #define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2550 #define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2551 #define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2552 #define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2553 #define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2554 #define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2555 #define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2556 #define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2557 #define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2558 #define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2559 #define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2560 #define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2561 #define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2562 #define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2563 #define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2564 
2565 /*******************  Bit definition for CAN_F5R1 register  *******************/
2566 #define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2567 #define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2568 #define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2569 #define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2570 #define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2571 #define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2572 #define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2573 #define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2574 #define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2575 #define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2576 #define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2577 #define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2578 #define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2579 #define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2580 #define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2581 #define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2582 #define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2583 #define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2584 #define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2585 #define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2586 #define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2587 #define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2588 #define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2589 #define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2590 #define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2591 #define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2592 #define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2593 #define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2594 #define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2595 #define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2596 #define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2597 #define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2598 
2599 /*******************  Bit definition for CAN_F6R1 register  *******************/
2600 #define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2601 #define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2602 #define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2603 #define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2604 #define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2605 #define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2606 #define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2607 #define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2608 #define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2609 #define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2610 #define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2611 #define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2612 #define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2613 #define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2614 #define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2615 #define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2616 #define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2617 #define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2618 #define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2619 #define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2620 #define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2621 #define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2622 #define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2623 #define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2624 #define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2625 #define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2626 #define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2627 #define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2628 #define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2629 #define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2630 #define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2631 #define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2632 
2633 /*******************  Bit definition for CAN_F7R1 register  *******************/
2634 #define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2635 #define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2636 #define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2637 #define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2638 #define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2639 #define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2640 #define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2641 #define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2642 #define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2643 #define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2644 #define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2645 #define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2646 #define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2647 #define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2648 #define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2649 #define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2650 #define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2651 #define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2652 #define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2653 #define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2654 #define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2655 #define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2656 #define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2657 #define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2658 #define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2659 #define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2660 #define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2661 #define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2662 #define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2663 #define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2664 #define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2665 #define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2666 
2667 /*******************  Bit definition for CAN_F8R1 register  *******************/
2668 #define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2669 #define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2670 #define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2671 #define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2672 #define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2673 #define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2674 #define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2675 #define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2676 #define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2677 #define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2678 #define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2679 #define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2680 #define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2681 #define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2682 #define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2683 #define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2684 #define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2685 #define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2686 #define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2687 #define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2688 #define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2689 #define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2690 #define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2691 #define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2692 #define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2693 #define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2694 #define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2695 #define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2696 #define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2697 #define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2698 #define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2699 #define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2700 
2701 /*******************  Bit definition for CAN_F9R1 register  *******************/
2702 #define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2703 #define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2704 #define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2705 #define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2706 #define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2707 #define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2708 #define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2709 #define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2710 #define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2711 #define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2712 #define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2713 #define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2714 #define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2715 #define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2716 #define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2717 #define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2718 #define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2719 #define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2720 #define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2721 #define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2722 #define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2723 #define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2724 #define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2725 #define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2726 #define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2727 #define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2728 #define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2729 #define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2730 #define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2731 #define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2732 #define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2733 #define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2734 
2735 /*******************  Bit definition for CAN_F10R1 register  ******************/
2736 #define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2737 #define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2738 #define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2739 #define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2740 #define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2741 #define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2742 #define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2743 #define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2744 #define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2745 #define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2746 #define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2747 #define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2748 #define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2749 #define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2750 #define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2751 #define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2752 #define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2753 #define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2754 #define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2755 #define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2756 #define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2757 #define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2758 #define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2759 #define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2760 #define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2761 #define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2762 #define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2763 #define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2764 #define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2765 #define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2766 #define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2767 #define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2768 
2769 /*******************  Bit definition for CAN_F11R1 register  ******************/
2770 #define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2771 #define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2772 #define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2773 #define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2774 #define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2775 #define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2776 #define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2777 #define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2778 #define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2779 #define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2780 #define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2781 #define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2782 #define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2783 #define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2784 #define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2785 #define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2786 #define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2787 #define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2788 #define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2789 #define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2790 #define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2791 #define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2792 #define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2793 #define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2794 #define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2795 #define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2796 #define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2797 #define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2798 #define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2799 #define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2800 #define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2801 #define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2802 
2803 /*******************  Bit definition for CAN_F12R1 register  ******************/
2804 #define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2805 #define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2806 #define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2807 #define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2808 #define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2809 #define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2810 #define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2811 #define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2812 #define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2813 #define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2814 #define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2815 #define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2816 #define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2817 #define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2818 #define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2819 #define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2820 #define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2821 #define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2822 #define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2823 #define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2824 #define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2825 #define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2826 #define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2827 #define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2828 #define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2829 #define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2830 #define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2831 #define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2832 #define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2833 #define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2834 #define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2835 #define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2836 
2837 /*******************  Bit definition for CAN_F13R1 register  ******************/
2838 #define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2839 #define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2840 #define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2841 #define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2842 #define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2843 #define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2844 #define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2845 #define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2846 #define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2847 #define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2848 #define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2849 #define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2850 #define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2851 #define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2852 #define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2853 #define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2854 #define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2855 #define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2856 #define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2857 #define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2858 #define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2859 #define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2860 #define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2861 #define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2862 #define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2863 #define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2864 #define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2865 #define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2866 #define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2867 #define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2868 #define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2869 #define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2870 
2871 /*******************  Bit definition for CAN_F0R2 register  *******************/
2872 #define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2873 #define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2874 #define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2875 #define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2876 #define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2877 #define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2878 #define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2879 #define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2880 #define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2881 #define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2882 #define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2883 #define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2884 #define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2885 #define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2886 #define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2887 #define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2888 #define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2889 #define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2890 #define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2891 #define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2892 #define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2893 #define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2894 #define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2895 #define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2896 #define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2897 #define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2898 #define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2899 #define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2900 #define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2901 #define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2902 #define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2903 #define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2904 
2905 /*******************  Bit definition for CAN_F1R2 register  *******************/
2906 #define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2907 #define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2908 #define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2909 #define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2910 #define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2911 #define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2912 #define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2913 #define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2914 #define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2915 #define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2916 #define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2917 #define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2918 #define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2919 #define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2920 #define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2921 #define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2922 #define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2923 #define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2924 #define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2925 #define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2926 #define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2927 #define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2928 #define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2929 #define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2930 #define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2931 #define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2932 #define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2933 #define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2934 #define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2935 #define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2936 #define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2937 #define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2938 
2939 /*******************  Bit definition for CAN_F2R2 register  *******************/
2940 #define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2941 #define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2942 #define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2943 #define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2944 #define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2945 #define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2946 #define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2947 #define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2948 #define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2949 #define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2950 #define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2951 #define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2952 #define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2953 #define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2954 #define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2955 #define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2956 #define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2957 #define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2958 #define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2959 #define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2960 #define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2961 #define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2962 #define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2963 #define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2964 #define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2965 #define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
2966 #define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
2967 #define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
2968 #define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
2969 #define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
2970 #define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
2971 #define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
2972 
2973 /*******************  Bit definition for CAN_F3R2 register  *******************/
2974 #define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
2975 #define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
2976 #define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
2977 #define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
2978 #define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
2979 #define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
2980 #define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
2981 #define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
2982 #define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
2983 #define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
2984 #define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
2985 #define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
2986 #define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
2987 #define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
2988 #define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
2989 #define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
2990 #define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
2991 #define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
2992 #define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
2993 #define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
2994 #define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
2995 #define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
2996 #define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
2997 #define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
2998 #define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
2999 #define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3000 #define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3001 #define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3002 #define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3003 #define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3004 #define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3005 #define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3006 
3007 /*******************  Bit definition for CAN_F4R2 register  *******************/
3008 #define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3009 #define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3010 #define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3011 #define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3012 #define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3013 #define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3014 #define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3015 #define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3016 #define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3017 #define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3018 #define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3019 #define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3020 #define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3021 #define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3022 #define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3023 #define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3024 #define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3025 #define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3026 #define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3027 #define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3028 #define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3029 #define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3030 #define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3031 #define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3032 #define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3033 #define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3034 #define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3035 #define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3036 #define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3037 #define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3038 #define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3039 #define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3040 
3041 /*******************  Bit definition for CAN_F5R2 register  *******************/
3042 #define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3043 #define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3044 #define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3045 #define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3046 #define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3047 #define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3048 #define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3049 #define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3050 #define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3051 #define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3052 #define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3053 #define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3054 #define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3055 #define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3056 #define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3057 #define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3058 #define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3059 #define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3060 #define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3061 #define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3062 #define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3063 #define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3064 #define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3065 #define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3066 #define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3067 #define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3068 #define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3069 #define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3070 #define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3071 #define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3072 #define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3073 #define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3074 
3075 /*******************  Bit definition for CAN_F6R2 register  *******************/
3076 #define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3077 #define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3078 #define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3079 #define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3080 #define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3081 #define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3082 #define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3083 #define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3084 #define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3085 #define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3086 #define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3087 #define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3088 #define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3089 #define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3090 #define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3091 #define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3092 #define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3093 #define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3094 #define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3095 #define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3096 #define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3097 #define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3098 #define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3099 #define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3100 #define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3101 #define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3102 #define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3103 #define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3104 #define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3105 #define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3106 #define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3107 #define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3108 
3109 /*******************  Bit definition for CAN_F7R2 register  *******************/
3110 #define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3111 #define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3112 #define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3113 #define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3114 #define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3115 #define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3116 #define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3117 #define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3118 #define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3119 #define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3120 #define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3121 #define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3122 #define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3123 #define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3124 #define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3125 #define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3126 #define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3127 #define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3128 #define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3129 #define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3130 #define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3131 #define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3132 #define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3133 #define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3134 #define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3135 #define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3136 #define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3137 #define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3138 #define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3139 #define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3140 #define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3141 #define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3142 
3143 /*******************  Bit definition for CAN_F8R2 register  *******************/
3144 #define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3145 #define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3146 #define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3147 #define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3148 #define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3149 #define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3150 #define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3151 #define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3152 #define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3153 #define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3154 #define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3155 #define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3156 #define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3157 #define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3158 #define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3159 #define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3160 #define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3161 #define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3162 #define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3163 #define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3164 #define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3165 #define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3166 #define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3167 #define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3168 #define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3169 #define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3170 #define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3171 #define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3172 #define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3173 #define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3174 #define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3175 #define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3176 
3177 /*******************  Bit definition for CAN_F9R2 register  *******************/
3178 #define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3179 #define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3180 #define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3181 #define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3182 #define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3183 #define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3184 #define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3185 #define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3186 #define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3187 #define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3188 #define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3189 #define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3190 #define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3191 #define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3192 #define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3193 #define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3194 #define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3195 #define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3196 #define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3197 #define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3198 #define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3199 #define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3200 #define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3201 #define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3202 #define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3203 #define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3204 #define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3205 #define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3206 #define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3207 #define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3208 #define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3209 #define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3210 
3211 /*******************  Bit definition for CAN_F10R2 register  ******************/
3212 #define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3213 #define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3214 #define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3215 #define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3216 #define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3217 #define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3218 #define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3219 #define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3220 #define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3221 #define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3222 #define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3223 #define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3224 #define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3225 #define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3226 #define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3227 #define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3228 #define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3229 #define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3230 #define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3231 #define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3232 #define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3233 #define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3234 #define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3235 #define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3236 #define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3237 #define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3238 #define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3239 #define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3240 #define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3241 #define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3242 #define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3243 #define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3244 
3245 /*******************  Bit definition for CAN_F11R2 register  ******************/
3246 #define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3247 #define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3248 #define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3249 #define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3250 #define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3251 #define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3252 #define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3253 #define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3254 #define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3255 #define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3256 #define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3257 #define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3258 #define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3259 #define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3260 #define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3261 #define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3262 #define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3263 #define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3264 #define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3265 #define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3266 #define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3267 #define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3268 #define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3269 #define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3270 #define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3271 #define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3272 #define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3273 #define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3274 #define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3275 #define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3276 #define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3277 #define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3278 
3279 /*******************  Bit definition for CAN_F12R2 register  ******************/
3280 #define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3281 #define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3282 #define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3283 #define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3284 #define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3285 #define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3286 #define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3287 #define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3288 #define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3289 #define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3290 #define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3291 #define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3292 #define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3293 #define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3294 #define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3295 #define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3296 #define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3297 #define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3298 #define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3299 #define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3300 #define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3301 #define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3302 #define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3303 #define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3304 #define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3305 #define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3306 #define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3307 #define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3308 #define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3309 #define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3310 #define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3311 #define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3312 
3313 /*******************  Bit definition for CAN_F13R2 register  ******************/
3314 #define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
3315 #define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
3316 #define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
3317 #define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
3318 #define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
3319 #define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
3320 #define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
3321 #define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
3322 #define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
3323 #define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
3324 #define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
3325 #define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
3326 #define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
3327 #define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
3328 #define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
3329 #define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
3330 #define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
3331 #define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
3332 #define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
3333 #define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
3334 #define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
3335 #define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
3336 #define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
3337 #define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
3338 #define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
3339 #define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
3340 #define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
3341 #define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
3342 #define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
3343 #define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
3344 #define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
3345 #define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
3346 
3347 /******************************************************************************/
3348 /*                                                                            */
3349 /*                          CRC calculation unit                              */
3350 /*                                                                            */
3351 /******************************************************************************/
3352 /*******************  Bit definition for CRC_DR register  *********************/
3353 #define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
3354 
3355 
3356 /*******************  Bit definition for CRC_IDR register  ********************/
3357 #define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
3358 
3359 
3360 /********************  Bit definition for CRC_CR register  ********************/
3361 #define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
3362 
3363 /******************************************************************************/
3364 /*                                                                            */
3365 /*                            Crypto Processor                                */
3366 /*                                                                            */
3367 /******************************************************************************/
3368 /******************* Bits definition for CRYP_CR register  ********************/
3369 #define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)
3370 
3371 #define CRYP_CR_ALGOMODE                     ((uint32_t)0x00080038)
3372 #define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)
3373 #define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)
3374 #define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)
3375 #define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)
3376 #define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)
3377 #define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)
3378 #define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)
3379 #define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)
3380 #define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)
3381 #define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)
3382 #define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)
3383 
3384 #define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)
3385 #define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)
3386 #define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)
3387 #define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)
3388 #define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)
3389 #define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)
3390 #define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)
3391 #define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)
3392 
3393 #define CRYP_CR_GCM_CCMPH                    ((uint32_t)0x00030000)
3394 #define CRYP_CR_GCM_CCMPH_0                  ((uint32_t)0x00010000)
3395 #define CRYP_CR_GCM_CCMPH_1                  ((uint32_t)0x00020000)
3396 #define CRYP_CR_ALGOMODE_3                   ((uint32_t)0x00080000)
3397 
3398 /****************** Bits definition for CRYP_SR register  *********************/
3399 #define CRYP_SR_IFEM                         ((uint32_t)0x00000001)
3400 #define CRYP_SR_IFNF                         ((uint32_t)0x00000002)
3401 #define CRYP_SR_OFNE                         ((uint32_t)0x00000004)
3402 #define CRYP_SR_OFFU                         ((uint32_t)0x00000008)
3403 #define CRYP_SR_BUSY                         ((uint32_t)0x00000010)
3404 /****************** Bits definition for CRYP_DMACR register  ******************/
3405 #define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)
3406 #define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)
3407 /*****************  Bits definition for CRYP_IMSCR register  ******************/
3408 #define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)
3409 #define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)
3410 /****************** Bits definition for CRYP_RISR register  *******************/
3411 #define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)
3412 #define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)
3413 /****************** Bits definition for CRYP_MISR register  *******************/
3414 #define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)
3415 #define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)
3416 
3417 /******************************************************************************/
3418 /*                                                                            */
3419 /*                      Digital to Analog Converter                           */
3420 /*                                                                            */
3421 /******************************************************************************/
3422 /********************  Bit definition for DAC_CR register  ********************/
3423 #define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
3424 #define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
3425 #define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
3426 
3427 #define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
3428 #define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
3429 #define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
3430 #define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
3431 
3432 #define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3433 #define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
3434 #define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
3435 
3436 #define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3437 #define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
3438 #define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
3439 #define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
3440 #define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
3441 
3442 #define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
3443 #define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
3444 #define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
3445 #define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
3446 
3447 #define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3448 #define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
3449 #define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
3450 #define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
3451 
3452 #define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3453 #define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
3454 #define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
3455 
3456 #define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3457 #define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
3458 #define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
3459 #define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
3460 #define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
3461 
3462 #define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
3463 
3464 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
3465 #define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
3466 #define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
3467 
3468 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
3469 #define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
3470 
3471 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
3472 #define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
3473 
3474 /******************  Bit definition for DAC_DHR8R1 register  ******************/
3475 #define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
3476 
3477 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
3478 #define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
3479 
3480 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
3481 #define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
3482 
3483 /******************  Bit definition for DAC_DHR8R2 register  ******************/
3484 #define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
3485 
3486 /*****************  Bit definition for DAC_DHR12RD register  ******************/
3487 #define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
3488 #define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
3489 
3490 /*****************  Bit definition for DAC_DHR12LD register  ******************/
3491 #define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
3492 #define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
3493 
3494 /******************  Bit definition for DAC_DHR8RD register  ******************/
3495 #define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
3496 #define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
3497 
3498 /*******************  Bit definition for DAC_DOR1 register  *******************/
3499 #define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
3500 
3501 /*******************  Bit definition for DAC_DOR2 register  *******************/
3502 #define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
3503 
3504 /********************  Bit definition for DAC_SR register  ********************/
3505 #define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
3506 #define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
3507 
3508 /******************************************************************************/
3509 /*                                                                            */
3510 /*                                 Debug MCU                                  */
3511 /*                                                                            */
3512 /******************************************************************************/
3513 
3514 /******************************************************************************/
3515 /*                                                                            */
3516 /*                                    DCMI                                    */
3517 /*                                                                            */
3518 /******************************************************************************/
3519 /********************  Bits definition for DCMI_CR register  ******************/
3520 #define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
3521 #define DCMI_CR_CM                           ((uint32_t)0x00000002)
3522 #define DCMI_CR_CROP                         ((uint32_t)0x00000004)
3523 #define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
3524 #define DCMI_CR_ESS                          ((uint32_t)0x00000010)
3525 #define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
3526 #define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
3527 #define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
3528 #define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
3529 #define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
3530 #define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
3531 #define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
3532 #define DCMI_CR_CRE                          ((uint32_t)0x00001000)
3533 #define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
3534 
3535 /********************  Bits definition for DCMI_SR register  ******************/
3536 #define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
3537 #define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
3538 #define DCMI_SR_FNE                          ((uint32_t)0x00000004)
3539 
3540 /********************  Bits definition for DCMI_RISR register  ****************/
3541 #define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
3542 #define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
3543 #define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
3544 #define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
3545 #define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
3546 
3547 /********************  Bits definition for DCMI_IER register  *****************/
3548 #define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
3549 #define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
3550 #define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
3551 #define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
3552 #define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
3553 
3554 /********************  Bits definition for DCMI_MISR register  ****************/
3555 #define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
3556 #define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
3557 #define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
3558 #define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
3559 #define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
3560 
3561 /********************  Bits definition for DCMI_ICR register  *****************/
3562 #define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
3563 #define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
3564 #define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
3565 #define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
3566 #define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
3567 
3568 /******************************************************************************/
3569 /*                                                                            */
3570 /*                             DMA Controller                                 */
3571 /*                                                                            */
3572 /******************************************************************************/
3573 /********************  Bits definition for DMA_SxCR register  *****************/
3574 #define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
3575 #define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
3576 #define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
3577 #define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000)
3578 #define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
3579 #define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
3580 #define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
3581 #define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
3582 #define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
3583 #define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
3584 #define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
3585 #define DMA_SxCR_CT                          ((uint32_t)0x00080000)
3586 #define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
3587 #define DMA_SxCR_PL                          ((uint32_t)0x00030000)
3588 #define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
3589 #define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
3590 #define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
3591 #define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
3592 #define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
3593 #define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
3594 #define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
3595 #define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
3596 #define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
3597 #define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
3598 #define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
3599 #define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
3600 #define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
3601 #define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
3602 #define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
3603 #define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
3604 #define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
3605 #define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
3606 #define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
3607 #define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
3608 #define DMA_SxCR_EN                          ((uint32_t)0x00000001)
3609 
3610 /********************  Bits definition for DMA_SxCNDTR register  **************/
3611 #define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
3612 #define DMA_SxNDT_0                          ((uint32_t)0x00000001)
3613 #define DMA_SxNDT_1                          ((uint32_t)0x00000002)
3614 #define DMA_SxNDT_2                          ((uint32_t)0x00000004)
3615 #define DMA_SxNDT_3                          ((uint32_t)0x00000008)
3616 #define DMA_SxNDT_4                          ((uint32_t)0x00000010)
3617 #define DMA_SxNDT_5                          ((uint32_t)0x00000020)
3618 #define DMA_SxNDT_6                          ((uint32_t)0x00000040)
3619 #define DMA_SxNDT_7                          ((uint32_t)0x00000080)
3620 #define DMA_SxNDT_8                          ((uint32_t)0x00000100)
3621 #define DMA_SxNDT_9                          ((uint32_t)0x00000200)
3622 #define DMA_SxNDT_10                         ((uint32_t)0x00000400)
3623 #define DMA_SxNDT_11                         ((uint32_t)0x00000800)
3624 #define DMA_SxNDT_12                         ((uint32_t)0x00001000)
3625 #define DMA_SxNDT_13                         ((uint32_t)0x00002000)
3626 #define DMA_SxNDT_14                         ((uint32_t)0x00004000)
3627 #define DMA_SxNDT_15                         ((uint32_t)0x00008000)
3628 
3629 /********************  Bits definition for DMA_SxFCR register  ****************/
3630 #define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
3631 #define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
3632 #define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
3633 #define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
3634 #define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
3635 #define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
3636 #define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
3637 #define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
3638 #define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
3639 
3640 /********************  Bits definition for DMA_LISR register  *****************/
3641 #define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
3642 #define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
3643 #define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
3644 #define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
3645 #define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
3646 #define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
3647 #define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
3648 #define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
3649 #define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
3650 #define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
3651 #define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
3652 #define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
3653 #define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
3654 #define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
3655 #define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
3656 #define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
3657 #define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
3658 #define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
3659 #define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
3660 #define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
3661 
3662 /********************  Bits definition for DMA_HISR register  *****************/
3663 #define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
3664 #define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
3665 #define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
3666 #define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
3667 #define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
3668 #define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
3669 #define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
3670 #define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
3671 #define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
3672 #define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
3673 #define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
3674 #define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
3675 #define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
3676 #define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
3677 #define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
3678 #define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
3679 #define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
3680 #define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
3681 #define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
3682 #define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
3683 
3684 /********************  Bits definition for DMA_LIFCR register  ****************/
3685 #define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
3686 #define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
3687 #define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
3688 #define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
3689 #define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
3690 #define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
3691 #define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
3692 #define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
3693 #define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
3694 #define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
3695 #define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
3696 #define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
3697 #define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
3698 #define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
3699 #define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
3700 #define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
3701 #define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
3702 #define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
3703 #define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
3704 #define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
3705 
3706 /********************  Bits definition for DMA_HIFCR  register  ****************/
3707 #define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
3708 #define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
3709 #define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
3710 #define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
3711 #define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
3712 #define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
3713 #define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
3714 #define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
3715 #define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
3716 #define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
3717 #define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
3718 #define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
3719 #define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
3720 #define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
3721 #define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
3722 #define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
3723 #define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
3724 #define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
3725 #define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
3726 #define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
3727 
3728 /******************************************************************************/
3729 /*                                                                            */
3730 /*                         AHB Master DMA2D Controller (DMA2D)                */
3731 /*                                                                            */
3732 /******************************************************************************/
3733 
3734 /********************  Bit definition for DMA2D_CR register  ******************/
3735 
3736 #define DMA2D_CR_START                     ((uint32_t)0x00000001)               /*!< Start transfer */
3737 #define DMA2D_CR_SUSP                      ((uint32_t)0x00000002)               /*!< Suspend transfer */
3738 #define DMA2D_CR_ABORT                     ((uint32_t)0x00000004)               /*!< Abort transfer */
3739 #define DMA2D_CR_TEIE                      ((uint32_t)0x00000100)               /*!< Transfer Error Interrupt Enable */
3740 #define DMA2D_CR_TCIE                      ((uint32_t)0x00000200)               /*!< Transfer Complete Interrupt Enable */
3741 #define DMA2D_CR_TWIE                      ((uint32_t)0x00000400)               /*!< Transfer Watermark Interrupt Enable */
3742 #define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800)               /*!< CLUT Access Error Interrupt Enable */
3743 #define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000)               /*!< CLUT Transfer Complete Interrupt Enable */
3744 #define DMA2D_CR_CEIE                      ((uint32_t)0x00002000)               /*!< Configuration Error Interrupt Enable */
3745 #define DMA2D_CR_MODE                      ((uint32_t)0x00030000)               /*!< DMA2D Mode */
3746 
3747 /********************  Bit definition for DMA2D_ISR register  *****************/
3748 
3749 #define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001)               /*!< Transfer Error Interrupt Flag */
3750 #define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002)               /*!< Transfer Complete Interrupt Flag */
3751 #define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004)               /*!< Transfer Watermark Interrupt Flag */
3752 #define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008)               /*!< CLUT Access Error Interrupt Flag */
3753 #define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010)               /*!< CLUT Transfer Complete Interrupt Flag */
3754 #define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020)               /*!< Configuration Error Interrupt Flag */
3755 
3756 /********************  Bit definition for DMA2D_IFSR register  ****************/
3757 
3758 #define DMA2D_IFSR_CTEIF                   ((uint32_t)0x00000001)               /*!< Clears Transfer Error Interrupt Flag */
3759 #define DMA2D_IFSR_CTCIF                   ((uint32_t)0x00000002)               /*!< Clears Transfer Complete Interrupt Flag */
3760 #define DMA2D_IFSR_CTWIF                   ((uint32_t)0x00000004)               /*!< Clears Transfer Watermark Interrupt Flag */
3761 #define DMA2D_IFSR_CCAEIF                  ((uint32_t)0x00000008)               /*!< Clears CLUT Access Error Interrupt Flag */
3762 #define DMA2D_IFSR_CCTCIF                  ((uint32_t)0x00000010)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
3763 #define DMA2D_IFSR_CCEIF                   ((uint32_t)0x00000020)               /*!< Clears Configuration Error Interrupt Flag */
3764 
3765 /********************  Bit definition for DMA2D_FGMAR register  ***************/
3766 
3767 #define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
3768 
3769 /********************  Bit definition for DMA2D_FGOR register  ****************/
3770 
3771 #define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
3772 
3773 /********************  Bit definition for DMA2D_BGMAR register  ***************/
3774 
3775 #define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
3776 
3777 /********************  Bit definition for DMA2D_BGOR register  ****************/
3778 
3779 #define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
3780 
3781 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
3782 
3783 #define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
3784 #define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
3785 #define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
3786 #define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
3787 #define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha mode */
3788 #define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
3789 
3790 /********************  Bit definition for DMA2D_FGCOLR register  **************/
3791 
3792 #define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
3793 #define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
3794 #define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */
3795 
3796 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
3797 
3798 #define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
3799 #define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
3800 #define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
3801 #define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
3802 #define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha Mode */
3803 #define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
3804 
3805 /********************  Bit definition for DMA2D_BGCOLR register  **************/
3806 
3807 #define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
3808 #define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
3809 #define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */
3810 
3811 /********************  Bit definition for DMA2D_FGCMAR register  **************/
3812 
3813 #define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
3814 
3815 /********************  Bit definition for DMA2D_BGCMAR register  **************/
3816 
3817 #define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
3818 
3819 /********************  Bit definition for DMA2D_OPFCCR register  **************/
3820 
3821 #define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)               /*!< Color mode */
3822 
3823 /********************  Bit definition for DMA2D_OCOLR register  ***************/
3824 
3825 /*!<Mode_ARGB8888/RGB888 */
3826 
3827 #define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FF)               /*!< BLUE Value */
3828 #define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00)               /*!< GREEN Value  */
3829 #define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000)               /*!< Red Value */
3830 #define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000)               /*!< Alpha Channel Value */
3831 
3832 /*!<Mode_RGB565 */
3833 #define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
3834 #define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0)               /*!< GREEN Value  */
3835 #define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800)               /*!< Red Value */
3836 
3837 /*!<Mode_ARGB1555 */
3838 #define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
3839 #define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0)               /*!< GREEN Value  */
3840 #define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00)               /*!< Red Value */
3841 #define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000)               /*!< Alpha Channel Value */
3842 
3843 /*!<Mode_ARGB4444 */
3844 #define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000F)               /*!< BLUE Value */
3845 #define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0)               /*!< GREEN Value  */
3846 #define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00)               /*!< Red Value */
3847 #define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000)               /*!< Alpha Channel Value */
3848 
3849 /********************  Bit definition for DMA2D_OMAR register  ****************/
3850 
3851 #define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
3852 
3853 /********************  Bit definition for DMA2D_OOR register  *****************/
3854 
3855 #define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)               /*!< Line Offset */
3856 
3857 /********************  Bit definition for DMA2D_NLR register  *****************/
3858 
3859 #define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)               /*!< Number of Lines */
3860 #define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)               /*!< Pixel per Lines */
3861 
3862 /********************  Bit definition for DMA2D_LWR register  *****************/
3863 
3864 #define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFF)               /*!< Line Watermark */
3865 
3866 /********************  Bit definition for DMA2D_AMTCR register  ***************/
3867 
3868 #define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001)               /*!< Enable */
3869 #define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00)               /*!< Dead Time */
3870 
3871 
3872 
3873 /********************  Bit definition for DMA2D_FGCLUT register  **************/
3874 
3875 /********************  Bit definition for DMA2D_BGCLUT register  **************/
3876 
3877 
3878 /******************************************************************************/
3879 /*                                                                            */
3880 /*                    External Interrupt/Event Controller                     */
3881 /*                                                                            */
3882 /******************************************************************************/
3883 /*******************  Bit definition for EXTI_IMR register  *******************/
3884 #define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
3885 #define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
3886 #define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
3887 #define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
3888 #define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
3889 #define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
3890 #define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
3891 #define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
3892 #define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
3893 #define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
3894 #define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
3895 #define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
3896 #define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
3897 #define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
3898 #define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
3899 #define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
3900 #define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
3901 #define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
3902 #define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
3903 #define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
3904 
3905 /*******************  Bit definition for EXTI_EMR register  *******************/
3906 #define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
3907 #define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
3908 #define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
3909 #define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
3910 #define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
3911 #define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
3912 #define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
3913 #define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
3914 #define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
3915 #define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
3916 #define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
3917 #define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
3918 #define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
3919 #define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
3920 #define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
3921 #define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
3922 #define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
3923 #define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
3924 #define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
3925 #define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
3926 
3927 /******************  Bit definition for EXTI_RTSR register  *******************/
3928 #define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
3929 #define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
3930 #define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
3931 #define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
3932 #define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
3933 #define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
3934 #define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
3935 #define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
3936 #define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
3937 #define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
3938 #define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
3939 #define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
3940 #define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
3941 #define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
3942 #define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
3943 #define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
3944 #define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
3945 #define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
3946 #define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
3947 #define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
3948 
3949 /******************  Bit definition for EXTI_FTSR register  *******************/
3950 #define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
3951 #define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
3952 #define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
3953 #define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
3954 #define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
3955 #define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
3956 #define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
3957 #define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
3958 #define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
3959 #define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
3960 #define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
3961 #define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
3962 #define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
3963 #define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
3964 #define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
3965 #define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
3966 #define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
3967 #define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
3968 #define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
3969 #define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
3970 
3971 /******************  Bit definition for EXTI_SWIER register  ******************/
3972 #define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
3973 #define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
3974 #define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
3975 #define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
3976 #define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
3977 #define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
3978 #define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
3979 #define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
3980 #define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
3981 #define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
3982 #define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
3983 #define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
3984 #define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
3985 #define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
3986 #define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
3987 #define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
3988 #define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
3989 #define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
3990 #define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
3991 #define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
3992 
3993 /*******************  Bit definition for EXTI_PR register  ********************/
3994 #define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
3995 #define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
3996 #define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
3997 #define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
3998 #define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
3999 #define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
4000 #define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
4001 #define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
4002 #define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
4003 #define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
4004 #define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
4005 #define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
4006 #define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
4007 #define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
4008 #define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
4009 #define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
4010 #define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
4011 #define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
4012 #define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
4013 #define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
4014 
4015 /******************************************************************************/
4016 /*                                                                            */
4017 /*                                    FLASH                                   */
4018 /*                                                                            */
4019 /******************************************************************************/
4020 /*******************  Bits definition for FLASH_ACR register  *****************/
4021 #define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
4022 #define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
4023 #define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
4024 #define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
4025 #define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
4026 #define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
4027 #define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
4028 #define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
4029 #define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
4030 #define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008)
4031 #define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009)
4032 #define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000A)
4033 #define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000B)
4034 #define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000C)
4035 #define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000D)
4036 #define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000E)
4037 #define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000F)
4038 
4039 #define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
4040 #define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
4041 #define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
4042 #define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
4043 #define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
4044 #define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
4045 #define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
4046 
4047 /*******************  Bits definition for FLASH_SR register  ******************/
4048 #define FLASH_SR_EOP                         ((uint32_t)0x00000001)
4049 #define FLASH_SR_SOP                         ((uint32_t)0x00000002)
4050 #define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
4051 #define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
4052 #define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
4053 #define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
4054 #define FLASH_SR_BSY                         ((uint32_t)0x00010000)
4055 
4056 /*******************  Bits definition for FLASH_CR register  ******************/
4057 #define FLASH_CR_PG                          ((uint32_t)0x00000001)
4058 #define FLASH_CR_SER                         ((uint32_t)0x00000002)
4059 #define FLASH_CR_MER                         ((uint32_t)0x00000004)
4060 #define FLASH_CR_MER1                        FLASH_CR_MER
4061 #define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
4062 #define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
4063 #define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
4064 #define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
4065 #define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
4066 #define FLASH_CR_SNB_4                       ((uint32_t)0x00000040)
4067 #define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
4068 #define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
4069 #define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
4070 #define FLASH_CR_MER2                        ((uint32_t)0x00008000)
4071 #define FLASH_CR_STRT                        ((uint32_t)0x00010000)
4072 #define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
4073 #define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
4074 
4075 /*******************  Bits definition for FLASH_OPTCR register  ***************/
4076 #define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
4077 #define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
4078 #define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
4079 #define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
4080 #define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
4081 #define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010)
4082 
4083 #define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
4084 #define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
4085 #define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
4086 #define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
4087 #define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
4088 #define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
4089 #define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
4090 #define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
4091 #define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
4092 #define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
4093 #define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
4094 #define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
4095 #define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
4096 #define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
4097 #define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
4098 #define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
4099 #define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
4100 #define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
4101 #define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
4102 #define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
4103 #define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
4104 #define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
4105 #define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
4106 #define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
4107 #define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
4108 
4109 #define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000)
4110 #define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000)
4111 
4112 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
4113 #define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
4114 #define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
4115 #define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
4116 #define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
4117 #define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
4118 #define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
4119 #define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
4120 #define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
4121 #define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
4122 #define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
4123 #define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
4124 #define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
4125 #define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
4126 
4127 #if defined (STM32F40_41xxx)
4128 /******************************************************************************/
4129 /*                                                                            */
4130 /*                       Flexible Static Memory Controller                    */
4131 /*                                                                            */
4132 /******************************************************************************/
4133 /******************  Bit definition for FSMC_BCR1 register  *******************/
4134 #define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
4135 #define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
4136 
4137 #define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
4138 #define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
4139 #define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
4140 
4141 #define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
4142 #define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4143 #define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4144 
4145 #define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
4146 #define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
4147 #define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
4148 #define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
4149 #define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
4150 #define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
4151 #define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
4152 #define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
4153 #define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
4154 #define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
4155 
4156 /******************  Bit definition for FSMC_BCR2 register  *******************/
4157 #define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                */
4158 #define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
4159 
4160 #define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
4161 #define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
4162 #define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
4163 
4164 #define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
4165 #define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4166 #define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4167 
4168 #define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
4169 #define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
4170 #define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
4171 #define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
4172 #define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
4173 #define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
4174 #define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
4175 #define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
4176 #define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
4177 #define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
4178 
4179 /******************  Bit definition for FSMC_BCR3 register  *******************/
4180 #define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
4181 #define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
4182 
4183 #define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
4184 #define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
4185 #define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
4186 
4187 #define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
4188 #define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4189 #define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4190 
4191 #define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
4192 #define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
4193 #define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
4194 #define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
4195 #define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
4196 #define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
4197 #define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
4198 #define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
4199 #define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
4200 #define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
4201 
4202 /******************  Bit definition for FSMC_BCR4 register  *******************/
4203 #define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
4204 #define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
4205 
4206 #define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
4207 #define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
4208 #define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
4209 
4210 #define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
4211 #define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4212 #define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4213 
4214 #define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
4215 #define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
4216 #define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
4217 #define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
4218 #define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
4219 #define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
4220 #define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
4221 #define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
4222 #define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
4223 #define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
4224 
4225 /******************  Bit definition for FSMC_BTR1 register  ******************/
4226 #define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
4227 #define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
4228 #define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
4229 #define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
4230 #define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
4231 
4232 #define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4233 #define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
4234 #define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
4235 #define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
4236 #define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
4237 
4238 #define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
4239 #define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
4240 #define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
4241 #define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
4242 #define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
4243 
4244 #define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4245 #define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
4246 #define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
4247 #define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
4248 #define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
4249 
4250 #define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4251 #define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
4252 #define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
4253 #define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
4254 #define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
4255 
4256 #define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
4257 #define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
4258 #define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
4259 #define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
4260 #define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
4261 
4262 #define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
4263 #define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
4264 #define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
4265 
4266 /******************  Bit definition for FSMC_BTR2 register  *******************/
4267 #define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
4268 #define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
4269 #define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
4270 #define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
4271 #define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
4272 
4273 #define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4274 #define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
4275 #define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
4276 #define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
4277 #define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
4278 
4279 #define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
4280 #define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
4281 #define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
4282 #define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
4283 #define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
4284 
4285 #define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4286 #define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
4287 #define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
4288 #define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
4289 #define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
4290 
4291 #define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4292 #define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
4293 #define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
4294 #define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
4295 #define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
4296 
4297 #define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
4298 #define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
4299 #define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
4300 #define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
4301 #define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
4302 
4303 #define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
4304 #define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
4305 #define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
4306 
4307 /*******************  Bit definition for FSMC_BTR3 register  *******************/
4308 #define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
4309 #define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
4310 #define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
4311 #define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
4312 #define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
4313 
4314 #define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4315 #define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
4316 #define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
4317 #define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
4318 #define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
4319 
4320 #define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
4321 #define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
4322 #define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
4323 #define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
4324 #define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
4325 
4326 #define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4327 #define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
4328 #define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
4329 #define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
4330 #define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
4331 
4332 #define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4333 #define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
4334 #define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
4335 #define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
4336 #define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
4337 
4338 #define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
4339 #define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
4340 #define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
4341 #define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
4342 #define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
4343 
4344 #define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
4345 #define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
4346 #define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
4347 
4348 /******************  Bit definition for FSMC_BTR4 register  *******************/
4349 #define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
4350 #define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
4351 #define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
4352 #define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
4353 #define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
4354 
4355 #define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4356 #define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
4357 #define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
4358 #define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
4359 #define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
4360 
4361 #define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
4362 #define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
4363 #define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
4364 #define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
4365 #define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
4366 
4367 #define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4368 #define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
4369 #define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
4370 #define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
4371 #define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
4372 
4373 #define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4374 #define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
4375 #define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
4376 #define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
4377 #define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
4378 
4379 #define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
4380 #define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
4381 #define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
4382 #define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
4383 #define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
4384 
4385 #define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
4386 #define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
4387 #define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
4388 
4389 /******************  Bit definition for FSMC_BWTR1 register  ******************/
4390 #define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
4391 #define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
4392 #define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
4393 #define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
4394 #define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
4395 
4396 #define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4397 #define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
4398 #define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
4399 #define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
4400 #define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
4401 
4402 #define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
4403 #define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
4404 #define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
4405 #define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
4406 #define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
4407 
4408 #define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4409 #define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
4410 #define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
4411 #define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
4412 #define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
4413 
4414 #define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
4415 #define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
4416 #define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
4417 #define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
4418 #define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
4419 
4420 #define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
4421 #define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
4422 #define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
4423 
4424 /******************  Bit definition for FSMC_BWTR2 register  ******************/
4425 #define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
4426 #define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
4427 #define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
4428 #define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
4429 #define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
4430 
4431 #define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4432 #define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
4433 #define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
4434 #define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
4435 #define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
4436 
4437 #define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
4438 #define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
4439 #define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
4440 #define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
4441 #define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
4442 
4443 #define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4444 #define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
4445 #define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
4446 #define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
4447 #define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
4448 
4449 #define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
4450 #define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
4451 #define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
4452 #define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
4453 #define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
4454 
4455 #define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
4456 #define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
4457 #define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
4458 
4459 /******************  Bit definition for FSMC_BWTR3 register  ******************/
4460 #define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
4461 #define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
4462 #define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
4463 #define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
4464 #define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
4465 
4466 #define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4467 #define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
4468 #define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
4469 #define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
4470 #define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
4471 
4472 #define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
4473 #define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
4474 #define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
4475 #define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
4476 #define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
4477 
4478 #define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4479 #define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
4480 #define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
4481 #define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
4482 #define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
4483 
4484 #define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
4485 #define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
4486 #define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
4487 #define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
4488 #define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
4489 
4490 #define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
4491 #define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
4492 #define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
4493 
4494 /******************  Bit definition for FSMC_BWTR4 register  ******************/
4495 #define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
4496 #define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
4497 #define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
4498 #define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
4499 #define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
4500 
4501 #define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4502 #define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
4503 #define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
4504 #define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
4505 #define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
4506 
4507 #define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
4508 #define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
4509 #define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
4510 #define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
4511 #define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
4512 
4513 #define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4514 #define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
4515 #define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
4516 #define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
4517 #define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
4518 
4519 #define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
4520 #define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
4521 #define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
4522 #define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
4523 #define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
4524 
4525 #define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
4526 #define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
4527 #define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
4528 
4529 /******************  Bit definition for FSMC_PCR2 register  *******************/
4530 #define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
4531 #define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
4532 #define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
4533 
4534 #define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
4535 #define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4536 #define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4537 
4538 #define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
4539 
4540 #define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
4541 #define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
4542 #define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
4543 #define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
4544 #define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
4545 
4546 #define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
4547 #define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
4548 #define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
4549 #define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
4550 #define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
4551 
4552 #define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
4553 #define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
4554 #define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
4555 #define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
4556 
4557 /******************  Bit definition for FSMC_PCR3 register  *******************/
4558 #define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
4559 #define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
4560 #define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
4561 
4562 #define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
4563 #define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4564 #define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4565 
4566 #define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
4567 
4568 #define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
4569 #define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
4570 #define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
4571 #define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
4572 #define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
4573 
4574 #define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
4575 #define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
4576 #define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
4577 #define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
4578 #define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
4579 
4580 #define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
4581 #define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
4582 #define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
4583 #define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
4584 
4585 /******************  Bit definition for FSMC_PCR4 register  *******************/
4586 #define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
4587 #define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
4588 #define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
4589 
4590 #define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
4591 #define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4592 #define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4593 
4594 #define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
4595 
4596 #define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
4597 #define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
4598 #define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
4599 #define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
4600 #define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
4601 
4602 #define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
4603 #define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
4604 #define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
4605 #define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
4606 #define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
4607 
4608 #define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
4609 #define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
4610 #define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
4611 #define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
4612 
4613 /*******************  Bit definition for FSMC_SR2 register  *******************/
4614 #define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
4615 #define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
4616 #define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
4617 #define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
4618 #define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
4619 #define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
4620 #define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
4621 
4622 /*******************  Bit definition for FSMC_SR3 register  *******************/
4623 #define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
4624 #define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
4625 #define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
4626 #define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
4627 #define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
4628 #define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
4629 #define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
4630 
4631 /*******************  Bit definition for FSMC_SR4 register  *******************/
4632 #define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                 */
4633 #define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                       */
4634 #define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status                */
4635 #define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit   */
4636 #define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit         */
4637 #define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit  */
4638 #define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
4639 
4640 /******************  Bit definition for FSMC_PMEM2 register  ******************/
4641 #define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
4642 #define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
4643 #define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
4644 #define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
4645 #define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
4646 #define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
4647 #define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
4648 #define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
4649 #define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
4650 
4651 #define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
4652 #define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
4653 #define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
4654 #define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
4655 #define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
4656 #define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
4657 #define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
4658 #define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
4659 #define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
4660 
4661 #define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
4662 #define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
4663 #define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
4664 #define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
4665 #define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
4666 #define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
4667 #define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
4668 #define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
4669 #define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
4670 
4671 #define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
4672 #define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
4673 #define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
4674 #define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
4675 #define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
4676 #define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
4677 #define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
4678 #define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
4679 #define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
4680 
4681 /******************  Bit definition for FSMC_PMEM3 register  ******************/
4682 #define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4683 #define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
4684 #define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
4685 #define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
4686 #define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
4687 #define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
4688 #define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
4689 #define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
4690 #define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
4691 
4692 #define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4693 #define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
4694 #define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
4695 #define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
4696 #define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
4697 #define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
4698 #define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
4699 #define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
4700 #define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
4701 
4702 #define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4703 #define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
4704 #define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
4705 #define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
4706 #define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
4707 #define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
4708 #define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
4709 #define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
4710 #define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
4711 
4712 #define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4713 #define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
4714 #define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
4715 #define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
4716 #define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
4717 #define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
4718 #define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
4719 #define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
4720 #define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
4721 
4722 /******************  Bit definition for FSMC_PMEM4 register  ******************/
4723 #define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
4724 #define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
4725 #define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
4726 #define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
4727 #define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
4728 #define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
4729 #define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
4730 #define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
4731 #define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
4732 
4733 #define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
4734 #define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
4735 #define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
4736 #define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
4737 #define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
4738 #define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
4739 #define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
4740 #define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
4741 #define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
4742 
4743 #define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
4744 #define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
4745 #define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
4746 #define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
4747 #define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
4748 #define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
4749 #define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
4750 #define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
4751 #define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
4752 
4753 #define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
4754 #define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
4755 #define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
4756 #define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
4757 #define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
4758 #define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
4759 #define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
4760 #define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
4761 #define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
4762 
4763 /******************  Bit definition for FSMC_PATT2 register  ******************/
4764 #define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
4765 #define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
4766 #define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
4767 #define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
4768 #define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
4769 #define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
4770 #define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
4771 #define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
4772 #define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
4773 
4774 #define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
4775 #define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
4776 #define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
4777 #define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
4778 #define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
4779 #define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
4780 #define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
4781 #define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
4782 #define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
4783 
4784 #define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
4785 #define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
4786 #define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
4787 #define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
4788 #define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
4789 #define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
4790 #define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
4791 #define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
4792 #define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
4793 
4794 #define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
4795 #define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
4796 #define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
4797 #define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
4798 #define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
4799 #define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
4800 #define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
4801 #define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
4802 #define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
4803 
4804 /******************  Bit definition for FSMC_PATT3 register  ******************/
4805 #define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4806 #define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
4807 #define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
4808 #define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
4809 #define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
4810 #define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
4811 #define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
4812 #define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
4813 #define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
4814 
4815 #define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4816 #define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
4817 #define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
4818 #define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
4819 #define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
4820 #define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
4821 #define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
4822 #define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
4823 #define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
4824 
4825 #define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4826 #define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
4827 #define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
4828 #define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
4829 #define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
4830 #define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
4831 #define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
4832 #define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
4833 #define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
4834 
4835 #define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4836 #define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
4837 #define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
4838 #define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
4839 #define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
4840 #define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
4841 #define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
4842 #define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
4843 #define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
4844 
4845 /******************  Bit definition for FSMC_PATT4 register  ******************/
4846 #define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4847 #define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
4848 #define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
4849 #define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
4850 #define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
4851 #define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
4852 #define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
4853 #define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
4854 #define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
4855 
4856 #define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4857 #define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
4858 #define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
4859 #define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
4860 #define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
4861 #define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
4862 #define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
4863 #define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
4864 #define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
4865 
4866 #define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4867 #define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
4868 #define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
4869 #define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
4870 #define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
4871 #define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
4872 #define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
4873 #define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
4874 #define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
4875 
4876 #define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4877 #define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
4878 #define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
4879 #define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
4880 #define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
4881 #define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
4882 #define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
4883 #define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
4884 #define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
4885 
4886 /******************  Bit definition for FSMC_PIO4 register  *******************/
4887 #define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
4888 #define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
4889 #define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
4890 #define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
4891 #define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
4892 #define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
4893 #define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
4894 #define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
4895 #define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
4896 
4897 #define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
4898 #define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
4899 #define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
4900 #define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
4901 #define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
4902 #define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
4903 #define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
4904 #define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
4905 #define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
4906 
4907 #define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
4908 #define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
4909 #define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
4910 #define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
4911 #define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
4912 #define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
4913 #define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
4914 #define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
4915 #define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
4916 
4917 #define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4918 #define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
4919 #define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
4920 #define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
4921 #define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
4922 #define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
4923 #define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
4924 #define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
4925 #define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
4926 
4927 /******************  Bit definition for FSMC_ECCR2 register  ******************/
4928 #define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
4929 
4930 /******************  Bit definition for FSMC_ECCR3 register  ******************/
4931 #define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
4932 #endif /* STM32F40_41xxx */
4933 
4934 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
4935 /******************************************************************************/
4936 /*                                                                            */
4937 /*                          Flexible Memory Controller                        */
4938 /*                                                                            */
4939 /******************************************************************************/
4940 /******************  Bit definition for FMC_BCR1 register  *******************/
4941 #define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
4942 #define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
4943 
4944 #define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
4945 #define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
4946 #define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
4947 
4948 #define  FMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
4949 #define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4950 #define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4951 
4952 #define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
4953 #define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
4954 #define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
4955 #define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
4956 #define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
4957 #define  FMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
4958 #define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
4959 #define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
4960 #define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
4961 #define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
4962 #define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000)        /*!<Continous clock enable     */
4963 
4964 /******************  Bit definition for FMC_BCR2 register  *******************/
4965 #define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
4966 #define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
4967 
4968 #define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
4969 #define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
4970 #define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
4971 
4972 #define  FMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
4973 #define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4974 #define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4975 
4976 #define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
4977 #define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
4978 #define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
4979 #define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
4980 #define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
4981 #define  FMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
4982 #define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
4983 #define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
4984 #define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
4985 #define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
4986 
4987 /******************  Bit definition for FMC_BCR3 register  *******************/
4988 #define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
4989 #define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
4990 
4991 #define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
4992 #define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
4993 #define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
4994 
4995 #define  FMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
4996 #define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
4997 #define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
4998 
4999 #define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
5000 #define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
5001 #define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
5002 #define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
5003 #define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
5004 #define  FMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
5005 #define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
5006 #define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
5007 #define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
5008 #define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
5009 
5010 /******************  Bit definition for FMC_BCR4 register  *******************/
5011 #define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
5012 #define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
5013 
5014 #define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
5015 #define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
5016 #define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
5017 
5018 #define  FMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
5019 #define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
5020 #define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
5021 
5022 #define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
5023 #define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
5024 #define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
5025 #define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
5026 #define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
5027 #define  FMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
5028 #define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
5029 #define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
5030 #define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
5031 #define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
5032 
5033 /******************  Bit definition for FMC_BTR1 register  ******************/
5034 #define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5035 #define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
5036 #define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
5037 #define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
5038 #define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
5039 
5040 #define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
5041 #define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
5042 #define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
5043 #define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
5044 #define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
5045 
5046 #define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
5047 #define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
5048 #define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
5049 #define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
5050 #define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
5051 #define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
5052 #define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
5053 #define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
5054 #define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
5055 
5056 #define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5057 #define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
5058 #define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
5059 #define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
5060 #define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
5061 
5062 #define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5063 #define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
5064 #define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
5065 #define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
5066 #define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
5067 
5068 #define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
5069 #define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
5070 #define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
5071 #define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
5072 #define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
5073 
5074 #define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
5075 #define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
5076 #define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
5077 
5078 /******************  Bit definition for FMC_BTR2 register  *******************/
5079 #define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5080 #define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
5081 #define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
5082 #define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
5083 #define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
5084 
5085 #define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5086 #define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
5087 #define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
5088 #define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
5089 #define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
5090 
5091 #define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
5092 #define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
5093 #define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
5094 #define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
5095 #define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
5096 #define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
5097 #define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
5098 #define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
5099 #define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
5100 
5101 #define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5102 #define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
5103 #define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
5104 #define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
5105 #define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
5106 
5107 #define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5108 #define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
5109 #define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
5110 #define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
5111 #define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
5112 
5113 #define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
5114 #define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
5115 #define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
5116 #define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
5117 #define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
5118 
5119 #define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
5120 #define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
5121 #define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
5122 
5123 /*******************  Bit definition for FMC_BTR3 register  *******************/
5124 #define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5125 #define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
5126 #define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
5127 #define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
5128 #define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
5129 
5130 #define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5131 #define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
5132 #define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
5133 #define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
5134 #define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
5135 
5136 #define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
5137 #define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
5138 #define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
5139 #define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
5140 #define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
5141 #define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
5142 #define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
5143 #define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
5144 #define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
5145 
5146 #define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5147 #define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
5148 #define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
5149 #define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
5150 #define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
5151 
5152 #define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5153 #define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
5154 #define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
5155 #define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
5156 #define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
5157 
5158 #define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
5159 #define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
5160 #define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
5161 #define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
5162 #define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
5163 
5164 #define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
5165 #define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
5166 #define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
5167 
5168 /******************  Bit definition for FMC_BTR4 register  *******************/
5169 #define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5170 #define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
5171 #define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
5172 #define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
5173 #define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
5174 
5175 #define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5176 #define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
5177 #define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
5178 #define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
5179 #define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
5180 
5181 #define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
5182 #define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
5183 #define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
5184 #define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
5185 #define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
5186 #define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
5187 #define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
5188 #define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
5189 #define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
5190 
5191 #define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5192 #define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
5193 #define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
5194 #define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
5195 #define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
5196 
5197 #define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5198 #define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
5199 #define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
5200 #define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
5201 #define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
5202 
5203 #define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
5204 #define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
5205 #define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
5206 #define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
5207 #define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
5208 
5209 #define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
5210 #define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
5211 #define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
5212 
5213 /******************  Bit definition for FMC_BWTR1 register  ******************/
5214 #define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5215 #define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
5216 #define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
5217 #define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
5218 #define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
5219 
5220 #define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5221 #define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
5222 #define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
5223 #define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
5224 #define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
5225 
5226 #define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
5227 #define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
5228 #define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
5229 #define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
5230 #define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
5231 #define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
5232 #define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
5233 #define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
5234 #define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
5235 
5236 #define  FMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5237 #define  FMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
5238 #define  FMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
5239 #define  FMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
5240 #define  FMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
5241 
5242 #define  FMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
5243 #define  FMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
5244 #define  FMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
5245 #define  FMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
5246 #define  FMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
5247 
5248 #define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
5249 #define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
5250 #define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
5251 
5252 /******************  Bit definition for FMC_BWTR2 register  ******************/
5253 #define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5254 #define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
5255 #define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
5256 #define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
5257 #define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
5258 
5259 #define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5260 #define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
5261 #define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
5262 #define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
5263 #define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
5264 
5265 #define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
5266 #define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
5267 #define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
5268 #define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
5269 #define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
5270 #define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
5271 #define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
5272 #define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
5273 #define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
5274 
5275 #define  FMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5276 #define  FMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
5277 #define  FMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
5278 #define  FMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
5279 #define  FMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
5280 
5281 #define  FMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
5282 #define  FMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
5283 #define  FMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
5284 #define  FMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
5285 #define  FMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
5286 
5287 #define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
5288 #define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
5289 #define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
5290 
5291 /******************  Bit definition for FMC_BWTR3 register  ******************/
5292 #define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5293 #define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
5294 #define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
5295 #define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
5296 #define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
5297 
5298 #define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5299 #define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
5300 #define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
5301 #define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
5302 #define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
5303 
5304 #define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
5305 #define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
5306 #define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
5307 #define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
5308 #define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
5309 #define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
5310 #define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
5311 #define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
5312 #define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
5313 
5314 #define  FMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5315 #define  FMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
5316 #define  FMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
5317 #define  FMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
5318 #define  FMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
5319 
5320 #define  FMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
5321 #define  FMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
5322 #define  FMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
5323 #define  FMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
5324 #define  FMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
5325 
5326 #define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
5327 #define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
5328 #define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
5329 
5330 /******************  Bit definition for FMC_BWTR4 register  ******************/
5331 #define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5332 #define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
5333 #define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
5334 #define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
5335 #define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
5336 
5337 #define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5338 #define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
5339 #define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
5340 #define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
5341 #define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
5342 
5343 #define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
5344 #define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
5345 #define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
5346 #define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
5347 #define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
5348 #define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
5349 #define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
5350 #define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
5351 #define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
5352 
5353 #define  FMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5354 #define  FMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
5355 #define  FMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
5356 #define  FMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
5357 #define  FMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
5358 
5359 #define  FMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
5360 #define  FMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
5361 #define  FMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
5362 #define  FMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
5363 #define  FMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
5364 
5365 #define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
5366 #define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
5367 #define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
5368 
5369 /******************  Bit definition for FMC_PCR2 register  *******************/
5370 #define  FMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
5371 #define  FMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
5372 #define  FMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
5373 
5374 #define  FMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
5375 #define  FMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
5376 #define  FMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
5377 
5378 #define  FMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
5379 
5380 #define  FMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
5381 #define  FMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
5382 #define  FMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
5383 #define  FMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
5384 #define  FMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
5385 
5386 #define  FMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
5387 #define  FMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
5388 #define  FMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
5389 #define  FMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
5390 #define  FMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
5391 
5392 #define  FMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size)           */
5393 #define  FMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
5394 #define  FMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
5395 #define  FMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
5396 
5397 /******************  Bit definition for FMC_PCR3 register  *******************/
5398 #define  FMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
5399 #define  FMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
5400 #define  FMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
5401 
5402 #define  FMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
5403 #define  FMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
5404 #define  FMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
5405 
5406 #define  FMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
5407 
5408 #define  FMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
5409 #define  FMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
5410 #define  FMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
5411 #define  FMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
5412 #define  FMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
5413 
5414 #define  FMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
5415 #define  FMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
5416 #define  FMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
5417 #define  FMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
5418 #define  FMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
5419 
5420 #define  FMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
5421 #define  FMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
5422 #define  FMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
5423 #define  FMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
5424 
5425 /******************  Bit definition for FMC_PCR4 register  *******************/
5426 #define  FMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
5427 #define  FMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
5428 #define  FMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
5429 
5430 #define  FMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
5431 #define  FMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
5432 #define  FMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
5433 
5434 #define  FMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
5435 
5436 #define  FMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
5437 #define  FMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
5438 #define  FMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
5439 #define  FMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
5440 #define  FMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
5441 
5442 #define  FMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
5443 #define  FMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
5444 #define  FMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
5445 #define  FMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
5446 #define  FMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
5447 
5448 #define  FMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
5449 #define  FMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
5450 #define  FMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
5451 #define  FMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
5452 
5453 /*******************  Bit definition for FMC_SR2 register  *******************/
5454 #define  FMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
5455 #define  FMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
5456 #define  FMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
5457 #define  FMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
5458 #define  FMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
5459 #define  FMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
5460 #define  FMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
5461 
5462 /*******************  Bit definition for FMC_SR3 register  *******************/
5463 #define  FMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
5464 #define  FMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
5465 #define  FMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
5466 #define  FMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
5467 #define  FMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
5468 #define  FMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
5469 #define  FMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
5470 
5471 /*******************  Bit definition for FMC_SR4 register  *******************/
5472 #define  FMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
5473 #define  FMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
5474 #define  FMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
5475 #define  FMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
5476 #define  FMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
5477 #define  FMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
5478 #define  FMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
5479 
5480 /******************  Bit definition for FMC_PMEM2 register  ******************/
5481 #define  FMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
5482 #define  FMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
5483 #define  FMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
5484 #define  FMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
5485 #define  FMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
5486 #define  FMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
5487 #define  FMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
5488 #define  FMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
5489 #define  FMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
5490 
5491 #define  FMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
5492 #define  FMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
5493 #define  FMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
5494 #define  FMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
5495 #define  FMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
5496 #define  FMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
5497 #define  FMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
5498 #define  FMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
5499 #define  FMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
5500 
5501 #define  FMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
5502 #define  FMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
5503 #define  FMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
5504 #define  FMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
5505 #define  FMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
5506 #define  FMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
5507 #define  FMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
5508 #define  FMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
5509 #define  FMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
5510 
5511 #define  FMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
5512 #define  FMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
5513 #define  FMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
5514 #define  FMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
5515 #define  FMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
5516 #define  FMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
5517 #define  FMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
5518 #define  FMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
5519 #define  FMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
5520 
5521 /******************  Bit definition for FMC_PMEM3 register  ******************/
5522 #define  FMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
5523 #define  FMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
5524 #define  FMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
5525 #define  FMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
5526 #define  FMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
5527 #define  FMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
5528 #define  FMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
5529 #define  FMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
5530 #define  FMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
5531 
5532 #define  FMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
5533 #define  FMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
5534 #define  FMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
5535 #define  FMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
5536 #define  FMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
5537 #define  FMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
5538 #define  FMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
5539 #define  FMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
5540 #define  FMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
5541 
5542 #define  FMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
5543 #define  FMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
5544 #define  FMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
5545 #define  FMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
5546 #define  FMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
5547 #define  FMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
5548 #define  FMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
5549 #define  FMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
5550 #define  FMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
5551 
5552 #define  FMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
5553 #define  FMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
5554 #define  FMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
5555 #define  FMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
5556 #define  FMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
5557 #define  FMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
5558 #define  FMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
5559 #define  FMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
5560 #define  FMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
5561 
5562 /******************  Bit definition for FMC_PMEM4 register  ******************/
5563 #define  FMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
5564 #define  FMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
5565 #define  FMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
5566 #define  FMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
5567 #define  FMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
5568 #define  FMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
5569 #define  FMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
5570 #define  FMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
5571 #define  FMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
5572 
5573 #define  FMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
5574 #define  FMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
5575 #define  FMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
5576 #define  FMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
5577 #define  FMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
5578 #define  FMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
5579 #define  FMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
5580 #define  FMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
5581 #define  FMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
5582 
5583 #define  FMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
5584 #define  FMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
5585 #define  FMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
5586 #define  FMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
5587 #define  FMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
5588 #define  FMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
5589 #define  FMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
5590 #define  FMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
5591 #define  FMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
5592 
5593 #define  FMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
5594 #define  FMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
5595 #define  FMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
5596 #define  FMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
5597 #define  FMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
5598 #define  FMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
5599 #define  FMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
5600 #define  FMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
5601 #define  FMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
5602 
5603 /******************  Bit definition for FMC_PATT2 register  ******************/
5604 #define  FMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
5605 #define  FMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
5606 #define  FMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
5607 #define  FMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
5608 #define  FMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
5609 #define  FMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
5610 #define  FMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
5611 #define  FMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
5612 #define  FMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
5613 
5614 #define  FMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
5615 #define  FMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
5616 #define  FMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
5617 #define  FMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
5618 #define  FMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
5619 #define  FMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
5620 #define  FMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
5621 #define  FMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
5622 #define  FMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
5623 
5624 #define  FMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
5625 #define  FMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
5626 #define  FMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
5627 #define  FMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
5628 #define  FMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
5629 #define  FMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
5630 #define  FMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
5631 #define  FMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
5632 #define  FMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
5633 
5634 #define  FMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
5635 #define  FMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
5636 #define  FMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
5637 #define  FMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
5638 #define  FMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
5639 #define  FMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
5640 #define  FMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
5641 #define  FMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
5642 #define  FMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
5643 
5644 /******************  Bit definition for FMC_PATT3 register  ******************/
5645 #define  FMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
5646 #define  FMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
5647 #define  FMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
5648 #define  FMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
5649 #define  FMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
5650 #define  FMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
5651 #define  FMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
5652 #define  FMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
5653 #define  FMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
5654 
5655 #define  FMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
5656 #define  FMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
5657 #define  FMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
5658 #define  FMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
5659 #define  FMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
5660 #define  FMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
5661 #define  FMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
5662 #define  FMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
5663 #define  FMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
5664 
5665 #define  FMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
5666 #define  FMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
5667 #define  FMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
5668 #define  FMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
5669 #define  FMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
5670 #define  FMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
5671 #define  FMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
5672 #define  FMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
5673 #define  FMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
5674 
5675 #define  FMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
5676 #define  FMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
5677 #define  FMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
5678 #define  FMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
5679 #define  FMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
5680 #define  FMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
5681 #define  FMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
5682 #define  FMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
5683 #define  FMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
5684 
5685 /******************  Bit definition for FMC_PATT4 register  ******************/
5686 #define  FMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
5687 #define  FMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
5688 #define  FMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
5689 #define  FMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
5690 #define  FMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
5691 #define  FMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
5692 #define  FMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
5693 #define  FMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
5694 #define  FMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
5695 
5696 #define  FMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
5697 #define  FMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
5698 #define  FMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
5699 #define  FMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
5700 #define  FMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
5701 #define  FMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
5702 #define  FMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
5703 #define  FMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
5704 #define  FMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
5705 
5706 #define  FMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
5707 #define  FMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
5708 #define  FMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
5709 #define  FMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
5710 #define  FMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
5711 #define  FMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
5712 #define  FMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
5713 #define  FMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
5714 #define  FMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
5715 
5716 #define  FMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
5717 #define  FMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
5718 #define  FMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
5719 #define  FMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
5720 #define  FMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
5721 #define  FMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
5722 #define  FMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
5723 #define  FMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
5724 #define  FMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
5725 
5726 /******************  Bit definition for FMC_PIO4 register  *******************/
5727 #define  FMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
5728 #define  FMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
5729 #define  FMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
5730 #define  FMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
5731 #define  FMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
5732 #define  FMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
5733 #define  FMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
5734 #define  FMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
5735 #define  FMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
5736 
5737 #define  FMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
5738 #define  FMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
5739 #define  FMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
5740 #define  FMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
5741 #define  FMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
5742 #define  FMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
5743 #define  FMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
5744 #define  FMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
5745 #define  FMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
5746 
5747 #define  FMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
5748 #define  FMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
5749 #define  FMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
5750 #define  FMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
5751 #define  FMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
5752 #define  FMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
5753 #define  FMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
5754 #define  FMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
5755 #define  FMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
5756 
5757 #define  FMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
5758 #define  FMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
5759 #define  FMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
5760 #define  FMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
5761 #define  FMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
5762 #define  FMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
5763 #define  FMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
5764 #define  FMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
5765 #define  FMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
5766 
5767 /******************  Bit definition for FMC_ECCR2 register  ******************/
5768 #define  FMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
5769 
5770 /******************  Bit definition for FMC_ECCR3 register  ******************/
5771 #define  FMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
5772 
5773 /******************  Bit definition for FMC_SDCR1 register  ******************/
5774 #define  FMC_SDCR1_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
5775 #define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
5776 #define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
5777 
5778 #define  FMC_SDCR1_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
5779 #define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
5780 #define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
5781 
5782 #define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
5783 #define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
5784 #define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
5785 
5786 #define  FMC_SDCR1_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
5787 
5788 #define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
5789 #define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
5790 #define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
5791 
5792 #define  FMC_SDCR1_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
5793 
5794 #define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDRAM clock configuration */
5795 #define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
5796 #define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
5797 
5798 #define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
5799 
5800 #define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000)        /*!<Write protection */
5801 #define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
5802 #define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
5803 
5804 /******************  Bit definition for FMC_SDCR2 register  ******************/
5805 #define  FMC_SDCR2_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
5806 #define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
5807 #define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
5808 
5809 #define  FMC_SDCR2_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
5810 #define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
5811 #define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
5812 
5813 #define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
5814 #define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
5815 #define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
5816 
5817 #define  FMC_SDCR2_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
5818 
5819 #define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
5820 #define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
5821 #define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
5822 
5823 #define  FMC_SDCR2_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
5824 
5825 #define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
5826 #define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
5827 #define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
5828 
5829 #define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
5830 
5831 #define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000)        /*!<RPIPE[1:0](Read pipe) */
5832 #define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
5833 #define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
5834 
5835 /******************  Bit definition for FMC_SDTR1 register  ******************/
5836 #define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
5837 #define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
5838 #define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
5839 #define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
5840 #define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
5841 
5842 #define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
5843 #define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
5844 #define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
5845 #define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
5846 #define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
5847 
5848 #define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
5849 #define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
5850 #define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
5851 #define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
5852 #define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
5853 
5854 #define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
5855 #define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
5856 #define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
5857 #define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
5858 
5859 #define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
5860 #define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
5861 #define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
5862 #define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
5863 
5864 #define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
5865 #define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
5866 #define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
5867 #define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
5868 
5869 #define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
5870 #define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
5871 #define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
5872 #define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
5873 
5874 /******************  Bit definition for FMC_SDTR2 register  ******************/
5875 #define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
5876 #define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
5877 #define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
5878 #define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
5879 #define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
5880 
5881 #define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
5882 #define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
5883 #define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
5884 #define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
5885 #define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
5886 
5887 #define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
5888 #define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
5889 #define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
5890 #define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
5891 #define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
5892 
5893 #define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
5894 #define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
5895 #define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
5896 #define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
5897 
5898 #define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
5899 #define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
5900 #define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
5901 #define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
5902 
5903 #define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
5904 #define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
5905 #define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
5906 #define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
5907 
5908 #define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
5909 #define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
5910 #define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
5911 #define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
5912 
5913 /******************  Bit definition for FMC_SDCMR register  ******************/
5914 #define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007)        /*!<MODE[2:0] bits (Command mode) */
5915 #define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
5916 #define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
5917 #define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000003)        /*!<Bit 2 */
5918 
5919 #define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008)        /*!<Command target 2 */
5920 
5921 #define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010)        /*!<Command target 1 */
5922 
5923 #define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
5924 #define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020)        /*!<Bit 0 */
5925 #define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040)        /*!<Bit 1 */
5926 #define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080)        /*!<Bit 2 */
5927 #define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100)        /*!<Bit 3 */
5928 
5929 #define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00)        /*!<MRD[12:0] bits (Mode register definition) */
5930 
5931 /******************  Bit definition for FMC_SDRTR register  ******************/
5932 #define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001)        /*!<Clear refresh error flag */
5933 
5934 #define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFE)        /*!<COUNT[12:0] bits (Refresh timer count) */
5935 
5936 #define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000)        /*!<RES interupt enable */
5937 
5938 /******************  Bit definition for FMC_SDSR register  ******************/
5939 #define  FMC_SDSR_RE                        ((uint32_t)0x00000001)        /*!<Refresh error flag */
5940 
5941 #define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
5942 #define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002)        /*!<Bit 0 */
5943 #define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004)        /*!<Bit 1 */
5944 
5945 #define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
5946 #define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008)        /*!<Bit 0 */
5947 #define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010)        /*!<Bit 1 */
5948 
5949 #define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020)        /*!<Busy status */
5950 
5951 #endif /* STM32F427_437xx ||  STM32F429_439xx */
5952 
5953 /******************************************************************************/
5954 /*                                                                            */
5955 /*                            General Purpose I/O                             */
5956 /*                                                                            */
5957 /******************************************************************************/
5958 /******************  Bits definition for GPIO_MODER register  *****************/
5959 #define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
5960 #define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
5961 #define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
5962 
5963 #define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
5964 #define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
5965 #define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
5966 
5967 #define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
5968 #define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
5969 #define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
5970 
5971 #define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
5972 #define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
5973 #define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
5974 
5975 #define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
5976 #define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
5977 #define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
5978 
5979 #define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
5980 #define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
5981 #define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
5982 
5983 #define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
5984 #define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
5985 #define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
5986 
5987 #define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
5988 #define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
5989 #define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
5990 
5991 #define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
5992 #define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
5993 #define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
5994 
5995 #define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
5996 #define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
5997 #define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
5998 
5999 #define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
6000 #define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
6001 #define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
6002 
6003 #define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
6004 #define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
6005 #define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
6006 
6007 #define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
6008 #define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
6009 #define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
6010 
6011 #define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
6012 #define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
6013 #define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
6014 
6015 #define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
6016 #define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
6017 #define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
6018 
6019 #define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
6020 #define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
6021 #define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
6022 
6023 /******************  Bits definition for GPIO_OTYPER register  ****************/
6024 #define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
6025 #define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
6026 #define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
6027 #define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
6028 #define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
6029 #define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
6030 #define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
6031 #define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
6032 #define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
6033 #define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
6034 #define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
6035 #define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
6036 #define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
6037 #define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
6038 #define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
6039 #define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
6040 
6041 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
6042 #define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
6043 #define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
6044 #define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
6045 
6046 #define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
6047 #define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
6048 #define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
6049 
6050 #define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
6051 #define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
6052 #define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
6053 
6054 #define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
6055 #define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
6056 #define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
6057 
6058 #define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
6059 #define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
6060 #define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
6061 
6062 #define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
6063 #define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
6064 #define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
6065 
6066 #define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
6067 #define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
6068 #define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
6069 
6070 #define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
6071 #define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
6072 #define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
6073 
6074 #define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
6075 #define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
6076 #define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
6077 
6078 #define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
6079 #define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
6080 #define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
6081 
6082 #define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
6083 #define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
6084 #define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
6085 
6086 #define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
6087 #define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
6088 #define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
6089 
6090 #define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
6091 #define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
6092 #define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
6093 
6094 #define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
6095 #define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
6096 #define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
6097 
6098 #define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
6099 #define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
6100 #define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
6101 
6102 #define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
6103 #define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
6104 #define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
6105 
6106 /******************  Bits definition for GPIO_PUPDR register  *****************/
6107 #define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
6108 #define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
6109 #define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
6110 
6111 #define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
6112 #define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
6113 #define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
6114 
6115 #define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
6116 #define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
6117 #define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
6118 
6119 #define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
6120 #define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
6121 #define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
6122 
6123 #define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
6124 #define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
6125 #define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
6126 
6127 #define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
6128 #define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
6129 #define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
6130 
6131 #define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
6132 #define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
6133 #define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
6134 
6135 #define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
6136 #define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
6137 #define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
6138 
6139 #define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
6140 #define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
6141 #define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
6142 
6143 #define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
6144 #define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
6145 #define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
6146 
6147 #define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
6148 #define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
6149 #define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
6150 
6151 #define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
6152 #define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
6153 #define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
6154 
6155 #define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
6156 #define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
6157 #define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
6158 
6159 #define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
6160 #define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
6161 #define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
6162 
6163 #define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
6164 #define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
6165 #define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
6166 
6167 #define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
6168 #define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
6169 #define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
6170 
6171 /******************  Bits definition for GPIO_IDR register  *******************/
6172 #define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
6173 #define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
6174 #define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
6175 #define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
6176 #define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
6177 #define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
6178 #define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
6179 #define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
6180 #define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
6181 #define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
6182 #define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
6183 #define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
6184 #define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
6185 #define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
6186 #define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
6187 #define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
6188 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
6189 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
6190 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
6191 #define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
6192 #define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
6193 #define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
6194 #define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
6195 #define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
6196 #define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
6197 #define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
6198 #define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
6199 #define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
6200 #define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
6201 #define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
6202 #define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
6203 #define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
6204 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
6205 
6206 /******************  Bits definition for GPIO_ODR register  *******************/
6207 #define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
6208 #define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
6209 #define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
6210 #define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
6211 #define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
6212 #define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
6213 #define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
6214 #define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
6215 #define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
6216 #define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
6217 #define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
6218 #define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
6219 #define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
6220 #define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
6221 #define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
6222 #define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
6223 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6224 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
6225 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
6226 #define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
6227 #define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
6228 #define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
6229 #define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
6230 #define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
6231 #define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
6232 #define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
6233 #define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
6234 #define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
6235 #define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
6236 #define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
6237 #define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
6238 #define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
6239 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
6240 
6241 /******************  Bits definition for GPIO_BSRR register  ******************/
6242 #define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
6243 #define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
6244 #define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
6245 #define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
6246 #define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
6247 #define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
6248 #define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
6249 #define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
6250 #define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
6251 #define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
6252 #define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
6253 #define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
6254 #define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
6255 #define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
6256 #define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
6257 #define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
6258 #define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
6259 #define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
6260 #define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
6261 #define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
6262 #define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
6263 #define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
6264 #define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
6265 #define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
6266 #define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
6267 #define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
6268 #define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
6269 #define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
6270 #define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
6271 #define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
6272 #define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
6273 #define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
6274 
6275 /******************************************************************************/
6276 /*                                                                            */
6277 /*                                    HASH                                    */
6278 /*                                                                            */
6279 /******************************************************************************/
6280 /******************  Bits definition for HASH_CR register  ********************/
6281 #define HASH_CR_INIT                         ((uint32_t)0x00000004)
6282 #define HASH_CR_DMAE                         ((uint32_t)0x00000008)
6283 #define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)
6284 #define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)
6285 #define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)
6286 #define HASH_CR_MODE                         ((uint32_t)0x00000040)
6287 #define HASH_CR_ALGO                         ((uint32_t)0x00040080)
6288 #define HASH_CR_ALGO_0                       ((uint32_t)0x00000080)
6289 #define HASH_CR_ALGO_1                       ((uint32_t)0x00040000)
6290 #define HASH_CR_NBW                          ((uint32_t)0x00000F00)
6291 #define HASH_CR_NBW_0                        ((uint32_t)0x00000100)
6292 #define HASH_CR_NBW_1                        ((uint32_t)0x00000200)
6293 #define HASH_CR_NBW_2                        ((uint32_t)0x00000400)
6294 #define HASH_CR_NBW_3                        ((uint32_t)0x00000800)
6295 #define HASH_CR_DINNE                        ((uint32_t)0x00001000)
6296 #define HASH_CR_MDMAT                        ((uint32_t)0x00002000)
6297 #define HASH_CR_LKEY                         ((uint32_t)0x00010000)
6298 
6299 /******************  Bits definition for HASH_STR register  *******************/
6300 #define HASH_STR_NBW                         ((uint32_t)0x0000001F)
6301 #define HASH_STR_NBW_0                       ((uint32_t)0x00000001)
6302 #define HASH_STR_NBW_1                       ((uint32_t)0x00000002)
6303 #define HASH_STR_NBW_2                       ((uint32_t)0x00000004)
6304 #define HASH_STR_NBW_3                       ((uint32_t)0x00000008)
6305 #define HASH_STR_NBW_4                       ((uint32_t)0x00000010)
6306 #define HASH_STR_DCAL                        ((uint32_t)0x00000100)
6307 
6308 /******************  Bits definition for HASH_IMR register  *******************/
6309 #define HASH_IMR_DINIM                       ((uint32_t)0x00000001)
6310 #define HASH_IMR_DCIM                        ((uint32_t)0x00000002)
6311 
6312 /******************  Bits definition for HASH_SR register  ********************/
6313 #define HASH_SR_DINIS                        ((uint32_t)0x00000001)
6314 #define HASH_SR_DCIS                         ((uint32_t)0x00000002)
6315 #define HASH_SR_DMAS                         ((uint32_t)0x00000004)
6316 #define HASH_SR_BUSY                         ((uint32_t)0x00000008)
6317 
6318 /******************************************************************************/
6319 /*                                                                            */
6320 /*                      Inter-integrated Circuit Interface                    */
6321 /*                                                                            */
6322 /******************************************************************************/
6323 /*******************  Bit definition for I2C_CR1 register  ********************/
6324 #define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!<Peripheral Enable                             */
6325 #define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!<SMBus Mode                                    */
6326 #define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!<SMBus Type                                    */
6327 #define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!<ARP Enable                                    */
6328 #define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!<PEC Enable                                    */
6329 #define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!<General Call Enable                           */
6330 #define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!<Clock Stretching Disable (Slave mode)         */
6331 #define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!<Start Generation                              */
6332 #define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!<Stop Generation                               */
6333 #define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!<Acknowledge Enable                            */
6334 #define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!<Acknowledge/PEC Position (for data reception) */
6335 #define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!<Packet Error Checking                         */
6336 #define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!<SMBus Alert                                   */
6337 #define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!<Software Reset                                */
6338 
6339 /*******************  Bit definition for I2C_CR2 register  ********************/
6340 #define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
6341 #define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
6342 #define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
6343 #define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
6344 #define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
6345 #define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
6346 #define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
6347 
6348 #define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!<Error Interrupt Enable  */
6349 #define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!<Event Interrupt Enable  */
6350 #define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!<Buffer Interrupt Enable */
6351 #define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!<DMA Requests Enable     */
6352 #define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!<DMA Last Transfer       */
6353 
6354 /*******************  Bit definition for I2C_OAR1 register  *******************/
6355 #define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!<Interface Address */
6356 #define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!<Interface Address */
6357 
6358 #define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!<Bit 0 */
6359 #define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!<Bit 1 */
6360 #define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!<Bit 2 */
6361 #define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!<Bit 3 */
6362 #define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!<Bit 4 */
6363 #define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!<Bit 5 */
6364 #define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!<Bit 6 */
6365 #define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!<Bit 7 */
6366 #define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!<Bit 8 */
6367 #define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!<Bit 9 */
6368 
6369 #define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!<Addressing Mode (Slave mode) */
6370 
6371 /*******************  Bit definition for I2C_OAR2 register  *******************/
6372 #define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!<Dual addressing mode enable */
6373 #define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!<Interface address           */
6374 
6375 /********************  Bit definition for I2C_DR register  ********************/
6376 #define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!<8-bit Data Register         */
6377 
6378 /*******************  Bit definition for I2C_SR1 register  ********************/
6379 #define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!<Start Bit (Master mode)                         */
6380 #define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!<Address sent (master mode)/matched (slave mode) */
6381 #define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!<Byte Transfer Finished                          */
6382 #define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!<10-bit header sent (Master mode)                */
6383 #define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!<Stop detection (Slave mode)                     */
6384 #define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!<Data Register not Empty (receivers)             */
6385 #define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!<Data Register Empty (transmitters)              */
6386 #define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!<Bus Error                                       */
6387 #define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!<Arbitration Lost (master mode)                  */
6388 #define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!<Acknowledge Failure                             */
6389 #define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!<Overrun/Underrun                                */
6390 #define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!<PEC Error in reception                          */
6391 #define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!<Timeout or Tlow Error                           */
6392 #define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!<SMBus Alert                                     */
6393 
6394 /*******************  Bit definition for I2C_SR2 register  ********************/
6395 #define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!<Master/Slave                              */
6396 #define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!<Bus Busy                                  */
6397 #define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!<Transmitter/Receiver                      */
6398 #define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!<General Call Address (Slave mode)         */
6399 #define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!<SMBus Device Default Address (Slave mode) */
6400 #define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!<SMBus Host Header (Slave mode)            */
6401 #define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!<Dual Flag (Slave mode)                    */
6402 #define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!<Packet Error Checking Register            */
6403 
6404 /*******************  Bit definition for I2C_CCR register  ********************/
6405 #define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!<Clock Control Register in Fast/Standard mode (Master mode) */
6406 #define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!<Fast Mode Duty Cycle                                       */
6407 #define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!<I2C Master Mode Selection                                  */
6408 
6409 /******************  Bit definition for I2C_TRISE register  *******************/
6410 #define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
6411 
6412 /******************  Bit definition for I2C_FLTR register  *******************/
6413 #define  I2C_FLTR_DNF                     ((uint8_t)0x0F)                  /*!<Digital Noise Filter */
6414 #define  I2C_FLTR_ANOFF                   ((uint8_t)0x10)                  /*!<Analog Noise Filter OFF */
6415 
6416 /******************************************************************************/
6417 /*                                                                            */
6418 /*                           Independent WATCHDOG                             */
6419 /*                                                                            */
6420 /******************************************************************************/
6421 /*******************  Bit definition for IWDG_KR register  ********************/
6422 #define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
6423 
6424 /*******************  Bit definition for IWDG_PR register  ********************/
6425 #define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
6426 #define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
6427 #define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
6428 #define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
6429 
6430 /*******************  Bit definition for IWDG_RLR register  *******************/
6431 #define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value        */
6432 
6433 /*******************  Bit definition for IWDG_SR register  ********************/
6434 #define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update      */
6435 #define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
6436 
6437 /******************************************************************************/
6438 /*                                                                            */
6439 /*                      LCD-TFT Display Controller (LTDC)                     */
6440 /*                                                                            */
6441 /******************************************************************************/
6442 
6443 /********************  Bit definition for LTDC_SSCR register  *****************/
6444 
6445 #define LTDC_SSCR_VSH                       ((uint32_t)0x000007FF)              /*!< Vertical Synchronization Height */
6446 #define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000)              /*!< Horizontal Synchronization Width */
6447 
6448 /********************  Bit definition for LTDC_BPCR register  *****************/
6449 
6450 #define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FF)              /*!< Accumulated Vertical Back Porch */
6451 #define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000)              /*!< Accumulated Horizontal Back Porch */
6452 
6453 /********************  Bit definition for LTDC_AWCR register  *****************/
6454 
6455 #define LTDC_AWCR_AAH                       ((uint32_t)0x000007FF)              /*!< Accumulated Active heigh */
6456 #define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000)              /*!< Accumulated Active Width */
6457 
6458 /********************  Bit definition for LTDC_TWCR register  *****************/
6459 
6460 #define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FF)              /*!< Total Heigh */
6461 #define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000)              /*!< Total Width */
6462 
6463 /********************  Bit definition for LTDC_GCR register  ******************/
6464 
6465 #define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001)              /*!< LCD-TFT controller enable bit */
6466 #define LTDC_GCR_DBW                        ((uint32_t)0x00000070)              /*!< Dither Blue Width */
6467 #define LTDC_GCR_DGW                        ((uint32_t)0x00000700)              /*!< Dither Green Width */
6468 #define LTDC_GCR_DRW                        ((uint32_t)0x00007000)              /*!< Dither Red Width */
6469 #define LTDC_GCR_DTEN                       ((uint32_t)0x00010000)              /*!< Dither Enable */
6470 #define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000)              /*!< Pixel Clock Polarity */
6471 #define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000)              /*!< Data Enable Polarity */
6472 #define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000)              /*!< Vertical Synchronization Polarity */
6473 #define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000)              /*!< Horizontal Synchronization Polarity */
6474 
6475 /********************  Bit definition for LTDC_SRCR register  *****************/
6476 
6477 #define LTDC_SRCR_IMR                      ((uint32_t)0x00000001)               /*!< Immediate Reload */
6478 #define LTDC_SRCR_VBR                      ((uint32_t)0x00000002)               /*!< Vertical Blanking Reload */
6479 
6480 /********************  Bit definition for LTDC_BCCR register  *****************/
6481 
6482 #define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FF)              /*!< Background Blue value */
6483 #define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00)              /*!< Background Green value */
6484 #define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000)              /*!< Background Red value */
6485 
6486 /********************  Bit definition for LTDC_IER register  ******************/
6487 
6488 #define LTDC_IER_LIE                        ((uint32_t)0x00000001)              /*!< Line Interrupt Enable */
6489 #define LTDC_IER_FUIE                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Enable */
6490 #define LTDC_IER_TERRIE                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Enable */
6491 #define LTDC_IER_RRIE                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt enable */
6492 
6493 /********************  Bit definition for LTDC_ISR register  ******************/
6494 
6495 #define LTDC_ISR_LIF                        ((uint32_t)0x00000001)              /*!< Line Interrupt Flag */
6496 #define LTDC_ISR_FUIF                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Flag */
6497 #define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Flag */
6498 #define LTDC_ISR_RRIF                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt Flag */
6499 
6500 /********************  Bit definition for LTDC_ICR register  ******************/
6501 
6502 #define LTDC_ICR_CLIF                       ((uint32_t)0x00000001)              /*!< Clears the Line Interrupt Flag */
6503 #define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002)              /*!< Clears the FIFO Underrun Interrupt Flag */
6504 #define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004)              /*!< Clears the Transfer Error Interrupt Flag */
6505 #define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008)              /*!< Clears Register Reload interrupt Flag */
6506 
6507 /********************  Bit definition for LTDC_LIPCR register  ****************/
6508 
6509 #define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FF)              /*!< Line Interrupt Position */
6510 
6511 /********************  Bit definition for LTDC_CPSR register  *****************/
6512 
6513 #define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFF)              /*!< Current Y Position */
6514 #define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000)              /*!< Current X Position */
6515 
6516 /********************  Bit definition for LTDC_CDSR register  *****************/
6517 
6518 #define LTDC_CDSR_VDES                      ((uint32_t)0x00000001)              /*!< Vertical Data Enable Status */
6519 #define LTDC_CDSR_HDES                      ((uint32_t)0x00000002)              /*!< Horizontal Data Enable Status */
6520 #define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004)              /*!< Vertical Synchronization Status */
6521 #define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008)              /*!< Horizontal Synchronization Status */
6522 
6523 /********************  Bit definition for LTDC_LxCR register  *****************/
6524 
6525 #define LTDC_LxCR_LEN                       ((uint32_t)0x00000001)              /*!< Layer Enable */
6526 #define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002)              /*!< Color Keying Enable */
6527 #define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010)              /*!< Color Lockup Table Enable */
6528 
6529 /********************  Bit definition for LTDC_LxWHPCR register  **************/
6530 
6531 #define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Horizontal Start Position */
6532 #define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Horizontal Stop Position */
6533 
6534 /********************  Bit definition for LTDC_LxWVPCR register  **************/
6535 
6536 #define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Vertical Start Position */
6537 #define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Vertical Stop Position */
6538 
6539 /********************  Bit definition for LTDC_LxCKCR register  ***************/
6540 
6541 #define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FF)              /*!< Color Key Blue value */
6542 #define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00)              /*!< Color Key Green value */
6543 #define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000)              /*!< Color Key Red value */
6544 
6545 /********************  Bit definition for LTDC_LxPFCR register  ***************/
6546 
6547 #define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007)              /*!< Pixel Format */
6548 
6549 /********************  Bit definition for LTDC_LxCACR register  ***************/
6550 
6551 #define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FF)              /*!< Constant Alpha */
6552 
6553 /********************  Bit definition for LTDC_LxDCCR register  ***************/
6554 
6555 #define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FF)              /*!< Default Color Blue */
6556 #define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00)              /*!< Default Color Green */
6557 #define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000)              /*!< Default Color Red */
6558 #define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000)              /*!< Default Color Alpha */
6559 
6560 /********************  Bit definition for LTDC_LxBFCR register  ***************/
6561 
6562 #define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007)              /*!< Blending Factor 2 */
6563 #define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700)              /*!< Blending Factor 1 */
6564 
6565 /********************  Bit definition for LTDC_LxCFBAR register  **************/
6566 
6567 #define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFF)              /*!< Color Frame Buffer Start Address */
6568 
6569 /********************  Bit definition for LTDC_LxCFBLR register  **************/
6570 
6571 #define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFF)              /*!< Color Frame Buffer Line Length */
6572 #define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000)              /*!< Color Frame Buffer Pitch in bytes */
6573 
6574 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
6575 
6576 #define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FF)              /*!< Frame Buffer Line Number */
6577 
6578 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
6579 
6580 #define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FF)              /*!< Blue value */
6581 #define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00)              /*!< Green value */
6582 #define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value */
6583 #define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
6584 
6585 /******************************************************************************/
6586 /*                                                                            */
6587 /*                             Power Control                                  */
6588 /*                                                                            */
6589 /******************************************************************************/
6590 /********************  Bit definition for PWR_CR register  ********************/
6591 #define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
6592 #define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
6593 #define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
6594 #define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
6595 #define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
6596 
6597 #define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
6598 #define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
6599 #define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
6600 #define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
6601 
6602 /*!< PVD level configuration */
6603 #define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
6604 #define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
6605 #define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
6606 #define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
6607 #define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
6608 #define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
6609 #define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
6610 #define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
6611 
6612 #define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
6613 #define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
6614 #define  PWR_CR_LPUDS                        ((uint32_t)0x00000400)     /*!< Low-Power Regulator in Stop under-drive mode               */
6615 #define  PWR_CR_MRUDS                        ((uint32_t)0x00000800)     /*!< Main regulator in Stop under-drive mode                    */
6616 #define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400)     /*!< Low-power regulator Low Voltage in Deep Sleep mode         */
6617 #define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800)     /*!< Main regulator Low Voltage in Deep Sleep mode              */
6618 
6619 #define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit */
6620 
6621 #define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
6622 #define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
6623 #define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
6624 
6625 #define  PWR_CR_ODEN                         ((uint32_t)0x00010000)     /*!< Over Drive enable                   */
6626 #define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000)     /*!< Over Drive switch enabled           */
6627 #define  PWR_CR_UDEN                         ((uint32_t)0x000C0000)     /*!< Under Drive enable in stop mode     */
6628 #define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000)     /*!< Bit 0                               */
6629 #define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000)     /*!< Bit 1                               */
6630 
6631 #define  PWR_CR_FMSSR                        ((uint32_t)0x00100000)     /*!< Flash Memory Sleep System Run        */
6632 #define  PWR_CR_FISSR                        ((uint32_t)0x00200000)     /*!< Flash Interface Stop while System Run */
6633 
6634 /* Legacy define */
6635 #define  PWR_CR_PMODE                        PWR_CR_VOS
6636 
6637 /*******************  Bit definition for PWR_CSR register  ********************/
6638 #define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
6639 #define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
6640 #define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
6641 #define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
6642 #define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
6643 #define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
6644 #define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
6645 #define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000)     /*!< Over Drive generator ready                       */
6646 #define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000)     /*!< Over Drive Switch ready                          */
6647 #define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000)     /*!< Under Drive ready                                */
6648 
6649 /* Legacy define */
6650 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
6651 
6652 /******************************************************************************/
6653 /*                                                                            */
6654 /*                         Reset and Clock Control                            */
6655 /*                                                                            */
6656 /******************************************************************************/
6657 /********************  Bit definition for RCC_CR register  ********************/
6658 #define  RCC_CR_HSION                        ((uint32_t)0x00000001)
6659 #define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
6660 
6661 #define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
6662 #define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
6663 #define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
6664 #define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
6665 #define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
6666 #define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
6667 
6668 #define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
6669 #define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
6670 #define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
6671 #define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
6672 #define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
6673 #define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
6674 #define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
6675 #define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
6676 #define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
6677 
6678 #define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
6679 #define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
6680 #define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
6681 #define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
6682 #define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
6683 #define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
6684 #define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
6685 #define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
6686 #define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000)
6687 #define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000)
6688 
6689 /********************  Bit definition for RCC_PLLCFGR register  ***************/
6690 #define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
6691 #define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
6692 #define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
6693 #define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
6694 #define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
6695 #define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
6696 #define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
6697 
6698 #define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
6699 #define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
6700 #define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
6701 #define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
6702 #define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
6703 #define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
6704 #define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
6705 #define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
6706 #define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
6707 #define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
6708 
6709 #define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
6710 #define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
6711 #define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
6712 
6713 #define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
6714 #define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
6715 #define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
6716 
6717 #define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
6718 #define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
6719 #define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
6720 #define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
6721 #define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
6722 
6723 /********************  Bit definition for RCC_CFGR register  ******************/
6724 /*!< SW configuration */
6725 #define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
6726 #define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
6727 #define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
6728 
6729 #define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
6730 #define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
6731 #define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
6732 
6733 /*!< SWS configuration */
6734 #define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
6735 #define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
6736 #define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
6737 
6738 #define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
6739 #define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
6740 #define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
6741 
6742 /*!< HPRE configuration */
6743 #define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
6744 #define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
6745 #define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
6746 #define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
6747 #define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
6748 
6749 #define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
6750 #define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
6751 #define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
6752 #define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
6753 #define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
6754 #define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
6755 #define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
6756 #define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
6757 #define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
6758 
6759 /*!< PPRE1 configuration */
6760 #define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
6761 #define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
6762 #define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
6763 #define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
6764 
6765 #define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
6766 #define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
6767 #define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
6768 #define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
6769 #define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
6770 
6771 /*!< PPRE2 configuration */
6772 #define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
6773 #define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
6774 #define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
6775 #define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
6776 
6777 #define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
6778 #define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
6779 #define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
6780 #define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
6781 #define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
6782 
6783 /*!< RTCPRE configuration */
6784 #define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
6785 #define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
6786 #define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
6787 #define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
6788 #define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
6789 #define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
6790 
6791 /*!< MCO1 configuration */
6792 #define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
6793 #define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
6794 #define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
6795 
6796 #define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
6797 
6798 #define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
6799 #define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
6800 #define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
6801 #define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
6802 
6803 #define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
6804 #define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
6805 #define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
6806 #define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
6807 
6808 #define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
6809 #define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
6810 #define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
6811 
6812 /********************  Bit definition for RCC_CIR register  *******************/
6813 #define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
6814 #define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
6815 #define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
6816 #define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
6817 #define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
6818 #define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
6819 #define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040)
6820 #define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
6821 #define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
6822 #define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
6823 #define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
6824 #define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
6825 #define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
6826 #define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
6827 #define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000)
6828 #define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
6829 #define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
6830 #define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
6831 #define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
6832 #define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
6833 #define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
6834 #define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000)
6835 #define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
6836 
6837 /********************  Bit definition for RCC_AHB1RSTR register  **************/
6838 #define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
6839 #define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
6840 #define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
6841 #define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
6842 #define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
6843 #define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
6844 #define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
6845 #define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
6846 #define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
6847 #define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200)
6848 #define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400)
6849 #define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
6850 #define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
6851 #define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
6852 #define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000)
6853 #define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
6854 #define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)
6855 
6856 /********************  Bit definition for RCC_AHB2RSTR register  **************/
6857 #define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
6858 #define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)
6859 #define  RCC_AHB2RSTR_HASHRST                ((uint32_t)0x00000020)
6860  /* maintained for legacy purpose */
6861  #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
6862 #define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
6863 #define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
6864 
6865 /********************  Bit definition for RCC_AHB3RSTR register  **************/
6866 #if defined(STM32F40_41xxx)
6867 #define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)
6868 #endif /* STM32F40_41xxx */
6869 
6870 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
6871 #define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001)
6872 #endif /* STM32F427_437xx ||  STM32F429_439xx */
6873 /********************  Bit definition for RCC_APB1RSTR register  **************/
6874 #define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
6875 #define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
6876 #define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
6877 #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
6878 #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
6879 #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
6880 #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
6881 #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
6882 #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
6883 #define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
6884 #define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
6885 #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
6886 #define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
6887 #define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
6888 #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
6889 #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
6890 #define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
6891 #define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
6892 #define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
6893 #define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
6894 #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
6895 #define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
6896 #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
6897 #define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000)
6898 #define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000)
6899 
6900 /********************  Bit definition for RCC_APB2RSTR register  **************/
6901 #define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
6902 #define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
6903 #define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
6904 #define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
6905 #define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
6906 #define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
6907 #define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
6908 #define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
6909 #define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
6910 #define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
6911 #define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
6912 #define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
6913 #define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
6914 #define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000)
6915 #define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000)
6916 #define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000)
6917 
6918 /* Old SPI1RST bit definition, maintained for legacy purpose */
6919 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
6920 
6921 /********************  Bit definition for RCC_AHB1ENR register  ***************/
6922 #define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
6923 #define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
6924 #define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
6925 #define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
6926 #define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
6927 #define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
6928 #define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
6929 #define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
6930 #define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
6931 #define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200)
6932 #define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400)
6933 #define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
6934 #define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
6935 #define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
6936 #define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
6937 #define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
6938 #define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000)
6939 #define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
6940 #define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
6941 #define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
6942 #define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
6943 #define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
6944 #define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
6945 
6946 /********************  Bit definition for RCC_AHB2ENR register  ***************/
6947 #define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
6948 #define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)
6949 #define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)
6950 #define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
6951 #define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
6952 
6953 /********************  Bit definition for RCC_AHB3ENR register  ***************/
6954 
6955 #if defined(STM32F40_41xxx)
6956 #define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)
6957 #endif /* STM32F40_41xxx */
6958 
6959 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
6960 #define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001)
6961 #endif /* STM32F427_437xx ||  STM32F429_439xx */
6962 
6963 /********************  Bit definition for RCC_APB1ENR register  ***************/
6964 #define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
6965 #define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
6966 #define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
6967 #define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
6968 #define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
6969 #define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
6970 #define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
6971 #define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
6972 #define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
6973 #define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
6974 #define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
6975 #define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
6976 #define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
6977 #define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
6978 #define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
6979 #define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
6980 #define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
6981 #define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
6982 #define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
6983 #define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
6984 #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
6985 #define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
6986 #define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
6987 #define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000)
6988 #define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000)
6989 
6990 /********************  Bit definition for RCC_APB2ENR register  ***************/
6991 #define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
6992 #define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
6993 #define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
6994 #define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
6995 #define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
6996 #define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
6997 #define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
6998 #define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
6999 #define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
7000 #define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
7001 #define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
7002 #define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
7003 #define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
7004 #define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
7005 #define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
7006 #define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)
7007 #define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000)
7008 #define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000)
7009 
7010 /********************  Bit definition for RCC_AHB1LPENR register  *************/
7011 #define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
7012 #define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
7013 #define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
7014 #define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
7015 #define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
7016 #define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
7017 #define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
7018 #define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
7019 #define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
7020 #define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200)
7021 #define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400)
7022 #define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
7023 #define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
7024 #define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
7025 #define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
7026 #define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
7027 #define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)
7028 #define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
7029 #define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
7030 #define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000)
7031 #define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
7032 #define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
7033 #define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
7034 #define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
7035 #define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
7036 #define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
7037 
7038 /********************  Bit definition for RCC_AHB2LPENR register  *************/
7039 #define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
7040 #define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)
7041 #define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)
7042 #define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
7043 #define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
7044 
7045 /********************  Bit definition for RCC_AHB3LPENR register  *************/
7046 #if defined(STM32F40_41xxx)
7047 #define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)
7048 #endif /* STM32F40_41xxx */
7049 
7050 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
7051 #define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001)
7052 #endif /* STM32F427_437xx ||  STM32F429_439xx */
7053 
7054 /********************  Bit definition for RCC_APB1LPENR register  *************/
7055 #define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
7056 #define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
7057 #define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
7058 #define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
7059 #define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
7060 #define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
7061 #define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
7062 #define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
7063 #define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
7064 #define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
7065 #define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
7066 #define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
7067 #define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
7068 #define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
7069 #define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
7070 #define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
7071 #define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
7072 #define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
7073 #define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
7074 #define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
7075 #define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
7076 #define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
7077 #define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
7078 #define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000)
7079 #define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000)
7080 
7081 /********************  Bit definition for RCC_APB2LPENR register  *************/
7082 #define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
7083 #define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
7084 #define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
7085 #define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
7086 #define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
7087 #define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)
7088 #define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
7089 #define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
7090 #define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
7091 #define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
7092 #define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
7093 #define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
7094 #define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
7095 #define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
7096 #define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
7097 #define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000)
7098 #define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000)
7099 #define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000)
7100 
7101 /********************  Bit definition for RCC_BDCR register  ******************/
7102 #define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
7103 #define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
7104 #define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
7105 #define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008)
7106 
7107 #define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
7108 #define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
7109 #define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
7110 
7111 #define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
7112 #define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
7113 
7114 /********************  Bit definition for RCC_CSR register  *******************/
7115 #define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
7116 #define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
7117 #define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
7118 #define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
7119 #define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
7120 #define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
7121 #define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
7122 #define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
7123 #define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
7124 #define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
7125 
7126 /********************  Bit definition for RCC_SSCGR register  *****************/
7127 #define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
7128 #define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
7129 #define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
7130 #define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
7131 
7132 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
7133 #define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003F)
7134 #define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001)
7135 #define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002)
7136 #define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004)
7137 #define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008)
7138 #define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010)
7139 #define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020)
7140 
7141 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
7142 #define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
7143 #define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000)
7144 #define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
7145 
7146 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
7147 #define  RCC_PLLSAICFGR_PLLI2SN              ((uint32_t)0x00007FC0)
7148 #define  RCC_PLLSAICFGR_PLLI2SQ              ((uint32_t)0x0F000000)
7149 #define  RCC_PLLSAICFGR_PLLI2SR              ((uint32_t)0x70000000)
7150 
7151 /********************  Bit definition for RCC_DCKCFGR register  ***************/
7152 #define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001F)
7153 #define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00)
7154 #define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000)
7155 #define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000)
7156 #define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000)
7157 #define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000)
7158 
7159 
7160 /******************************************************************************/
7161 /*                                                                            */
7162 /*                                    RNG                                     */
7163 /*                                                                            */
7164 /******************************************************************************/
7165 /********************  Bits definition for RNG_CR register  *******************/
7166 #define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
7167 #define RNG_CR_IE                            ((uint32_t)0x00000008)
7168 
7169 /********************  Bits definition for RNG_SR register  *******************/
7170 #define RNG_SR_DRDY                          ((uint32_t)0x00000001)
7171 #define RNG_SR_CECS                          ((uint32_t)0x00000002)
7172 #define RNG_SR_SECS                          ((uint32_t)0x00000004)
7173 #define RNG_SR_CEIS                          ((uint32_t)0x00000020)
7174 #define RNG_SR_SEIS                          ((uint32_t)0x00000040)
7175 
7176 /******************************************************************************/
7177 /*                                                                            */
7178 /*                           Real-Time Clock (RTC)                            */
7179 /*                                                                            */
7180 /******************************************************************************/
7181 /********************  Bits definition for RTC_TR register  *******************/
7182 #define RTC_TR_PM                            ((uint32_t)0x00400000)
7183 #define RTC_TR_HT                            ((uint32_t)0x00300000)
7184 #define RTC_TR_HT_0                          ((uint32_t)0x00100000)
7185 #define RTC_TR_HT_1                          ((uint32_t)0x00200000)
7186 #define RTC_TR_HU                            ((uint32_t)0x000F0000)
7187 #define RTC_TR_HU_0                          ((uint32_t)0x00010000)
7188 #define RTC_TR_HU_1                          ((uint32_t)0x00020000)
7189 #define RTC_TR_HU_2                          ((uint32_t)0x00040000)
7190 #define RTC_TR_HU_3                          ((uint32_t)0x00080000)
7191 #define RTC_TR_MNT                           ((uint32_t)0x00007000)
7192 #define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
7193 #define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
7194 #define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
7195 #define RTC_TR_MNU                           ((uint32_t)0x00000F00)
7196 #define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
7197 #define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
7198 #define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
7199 #define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
7200 #define RTC_TR_ST                            ((uint32_t)0x00000070)
7201 #define RTC_TR_ST_0                          ((uint32_t)0x00000010)
7202 #define RTC_TR_ST_1                          ((uint32_t)0x00000020)
7203 #define RTC_TR_ST_2                          ((uint32_t)0x00000040)
7204 #define RTC_TR_SU                            ((uint32_t)0x0000000F)
7205 #define RTC_TR_SU_0                          ((uint32_t)0x00000001)
7206 #define RTC_TR_SU_1                          ((uint32_t)0x00000002)
7207 #define RTC_TR_SU_2                          ((uint32_t)0x00000004)
7208 #define RTC_TR_SU_3                          ((uint32_t)0x00000008)
7209 
7210 /********************  Bits definition for RTC_DR register  *******************/
7211 #define RTC_DR_YT                            ((uint32_t)0x00F00000)
7212 #define RTC_DR_YT_0                          ((uint32_t)0x00100000)
7213 #define RTC_DR_YT_1                          ((uint32_t)0x00200000)
7214 #define RTC_DR_YT_2                          ((uint32_t)0x00400000)
7215 #define RTC_DR_YT_3                          ((uint32_t)0x00800000)
7216 #define RTC_DR_YU                            ((uint32_t)0x000F0000)
7217 #define RTC_DR_YU_0                          ((uint32_t)0x00010000)
7218 #define RTC_DR_YU_1                          ((uint32_t)0x00020000)
7219 #define RTC_DR_YU_2                          ((uint32_t)0x00040000)
7220 #define RTC_DR_YU_3                          ((uint32_t)0x00080000)
7221 #define RTC_DR_WDU                           ((uint32_t)0x0000E000)
7222 #define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
7223 #define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
7224 #define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
7225 #define RTC_DR_MT                            ((uint32_t)0x00001000)
7226 #define RTC_DR_MU                            ((uint32_t)0x00000F00)
7227 #define RTC_DR_MU_0                          ((uint32_t)0x00000100)
7228 #define RTC_DR_MU_1                          ((uint32_t)0x00000200)
7229 #define RTC_DR_MU_2                          ((uint32_t)0x00000400)
7230 #define RTC_DR_MU_3                          ((uint32_t)0x00000800)
7231 #define RTC_DR_DT                            ((uint32_t)0x00000030)
7232 #define RTC_DR_DT_0                          ((uint32_t)0x00000010)
7233 #define RTC_DR_DT_1                          ((uint32_t)0x00000020)
7234 #define RTC_DR_DU                            ((uint32_t)0x0000000F)
7235 #define RTC_DR_DU_0                          ((uint32_t)0x00000001)
7236 #define RTC_DR_DU_1                          ((uint32_t)0x00000002)
7237 #define RTC_DR_DU_2                          ((uint32_t)0x00000004)
7238 #define RTC_DR_DU_3                          ((uint32_t)0x00000008)
7239 
7240 /********************  Bits definition for RTC_CR register  *******************/
7241 #define RTC_CR_COE                           ((uint32_t)0x00800000)
7242 #define RTC_CR_OSEL                          ((uint32_t)0x00600000)
7243 #define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
7244 #define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
7245 #define RTC_CR_POL                           ((uint32_t)0x00100000)
7246 #define RTC_CR_COSEL                         ((uint32_t)0x00080000)
7247 #define RTC_CR_BCK                           ((uint32_t)0x00040000)
7248 #define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
7249 #define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
7250 #define RTC_CR_TSIE                          ((uint32_t)0x00008000)
7251 #define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
7252 #define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
7253 #define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
7254 #define RTC_CR_TSE                           ((uint32_t)0x00000800)
7255 #define RTC_CR_WUTE                          ((uint32_t)0x00000400)
7256 #define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
7257 #define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
7258 #define RTC_CR_DCE                           ((uint32_t)0x00000080)
7259 #define RTC_CR_FMT                           ((uint32_t)0x00000040)
7260 #define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
7261 #define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
7262 #define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
7263 #define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
7264 #define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
7265 #define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
7266 #define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
7267 
7268 /********************  Bits definition for RTC_ISR register  ******************/
7269 #define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
7270 #define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
7271 #define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
7272 #define RTC_ISR_TSF                          ((uint32_t)0x00000800)
7273 #define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
7274 #define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
7275 #define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
7276 #define RTC_ISR_INIT                         ((uint32_t)0x00000080)
7277 #define RTC_ISR_INITF                        ((uint32_t)0x00000040)
7278 #define RTC_ISR_RSF                          ((uint32_t)0x00000020)
7279 #define RTC_ISR_INITS                        ((uint32_t)0x00000010)
7280 #define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
7281 #define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
7282 #define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
7283 #define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
7284 
7285 /********************  Bits definition for RTC_PRER register  *****************/
7286 #define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
7287 #define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)
7288 
7289 /********************  Bits definition for RTC_WUTR register  *****************/
7290 #define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
7291 
7292 /********************  Bits definition for RTC_CALIBR register  ***************/
7293 #define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
7294 #define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
7295 
7296 /********************  Bits definition for RTC_ALRMAR register  ***************/
7297 #define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
7298 #define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
7299 #define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
7300 #define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
7301 #define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
7302 #define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
7303 #define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
7304 #define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
7305 #define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
7306 #define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
7307 #define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
7308 #define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
7309 #define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
7310 #define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
7311 #define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
7312 #define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
7313 #define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
7314 #define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
7315 #define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
7316 #define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
7317 #define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
7318 #define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
7319 #define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
7320 #define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
7321 #define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
7322 #define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
7323 #define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
7324 #define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
7325 #define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
7326 #define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
7327 #define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
7328 #define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
7329 #define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
7330 #define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
7331 #define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
7332 #define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
7333 #define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
7334 #define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
7335 #define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
7336 #define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
7337 
7338 /********************  Bits definition for RTC_ALRMBR register  ***************/
7339 #define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
7340 #define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
7341 #define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
7342 #define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
7343 #define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
7344 #define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
7345 #define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
7346 #define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
7347 #define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
7348 #define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
7349 #define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
7350 #define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
7351 #define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
7352 #define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
7353 #define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
7354 #define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
7355 #define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
7356 #define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
7357 #define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
7358 #define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
7359 #define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
7360 #define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
7361 #define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
7362 #define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
7363 #define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
7364 #define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
7365 #define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
7366 #define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
7367 #define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
7368 #define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
7369 #define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
7370 #define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
7371 #define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
7372 #define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
7373 #define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
7374 #define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
7375 #define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
7376 #define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
7377 #define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
7378 #define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
7379 
7380 /********************  Bits definition for RTC_WPR register  ******************/
7381 #define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
7382 
7383 /********************  Bits definition for RTC_SSR register  ******************/
7384 #define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
7385 
7386 /********************  Bits definition for RTC_SHIFTR register  ***************/
7387 #define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
7388 #define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
7389 
7390 /********************  Bits definition for RTC_TSTR register  *****************/
7391 #define RTC_TSTR_PM                          ((uint32_t)0x00400000)
7392 #define RTC_TSTR_HT                          ((uint32_t)0x00300000)
7393 #define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
7394 #define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
7395 #define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
7396 #define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
7397 #define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
7398 #define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
7399 #define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
7400 #define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
7401 #define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
7402 #define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
7403 #define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
7404 #define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
7405 #define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
7406 #define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
7407 #define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
7408 #define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
7409 #define RTC_TSTR_ST                          ((uint32_t)0x00000070)
7410 #define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
7411 #define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
7412 #define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
7413 #define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
7414 #define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
7415 #define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
7416 #define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
7417 #define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
7418 
7419 /********************  Bits definition for RTC_TSDR register  *****************/
7420 #define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
7421 #define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
7422 #define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
7423 #define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
7424 #define RTC_TSDR_MT                          ((uint32_t)0x00001000)
7425 #define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
7426 #define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
7427 #define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
7428 #define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
7429 #define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
7430 #define RTC_TSDR_DT                          ((uint32_t)0x00000030)
7431 #define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
7432 #define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
7433 #define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
7434 #define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
7435 #define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
7436 #define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
7437 #define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
7438 
7439 /********************  Bits definition for RTC_TSSSR register  ****************/
7440 #define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
7441 
7442 /********************  Bits definition for RTC_CAL register  *****************/
7443 #define RTC_CALR_CALP                        ((uint32_t)0x00008000)
7444 #define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
7445 #define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
7446 #define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
7447 #define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
7448 #define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
7449 #define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
7450 #define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
7451 #define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
7452 #define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
7453 #define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
7454 #define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
7455 #define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
7456 
7457 /********************  Bits definition for RTC_TAFCR register  ****************/
7458 #define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
7459 #define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
7460 #define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
7461 #define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
7462 #define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
7463 #define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
7464 #define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
7465 #define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
7466 #define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
7467 #define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
7468 #define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
7469 #define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
7470 #define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
7471 #define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
7472 #define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
7473 #define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
7474 #define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
7475 #define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
7476 
7477 /********************  Bits definition for RTC_ALRMASSR register  *************/
7478 #define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
7479 #define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
7480 #define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
7481 #define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
7482 #define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
7483 #define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
7484 
7485 /********************  Bits definition for RTC_ALRMBSSR register  *************/
7486 #define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
7487 #define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
7488 #define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
7489 #define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
7490 #define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
7491 #define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
7492 
7493 /********************  Bits definition for RTC_BKP0R register  ****************/
7494 #define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
7495 
7496 /********************  Bits definition for RTC_BKP1R register  ****************/
7497 #define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
7498 
7499 /********************  Bits definition for RTC_BKP2R register  ****************/
7500 #define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
7501 
7502 /********************  Bits definition for RTC_BKP3R register  ****************/
7503 #define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
7504 
7505 /********************  Bits definition for RTC_BKP4R register  ****************/
7506 #define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
7507 
7508 /********************  Bits definition for RTC_BKP5R register  ****************/
7509 #define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
7510 
7511 /********************  Bits definition for RTC_BKP6R register  ****************/
7512 #define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
7513 
7514 /********************  Bits definition for RTC_BKP7R register  ****************/
7515 #define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
7516 
7517 /********************  Bits definition for RTC_BKP8R register  ****************/
7518 #define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
7519 
7520 /********************  Bits definition for RTC_BKP9R register  ****************/
7521 #define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
7522 
7523 /********************  Bits definition for RTC_BKP10R register  ***************/
7524 #define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
7525 
7526 /********************  Bits definition for RTC_BKP11R register  ***************/
7527 #define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
7528 
7529 /********************  Bits definition for RTC_BKP12R register  ***************/
7530 #define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
7531 
7532 /********************  Bits definition for RTC_BKP13R register  ***************/
7533 #define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
7534 
7535 /********************  Bits definition for RTC_BKP14R register  ***************/
7536 #define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
7537 
7538 /********************  Bits definition for RTC_BKP15R register  ***************/
7539 #define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
7540 
7541 /********************  Bits definition for RTC_BKP16R register  ***************/
7542 #define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
7543 
7544 /********************  Bits definition for RTC_BKP17R register  ***************/
7545 #define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
7546 
7547 /********************  Bits definition for RTC_BKP18R register  ***************/
7548 #define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
7549 
7550 /********************  Bits definition for RTC_BKP19R register  ***************/
7551 #define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
7552 
7553 /******************************************************************************/
7554 /*                                                                            */
7555 /*                          Serial Audio Interface                            */
7556 /*                                                                            */
7557 /******************************************************************************/
7558 /********************  Bit definition for SAI_GCR register  *******************/
7559 #define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
7560 #define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
7561 #define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
7562 
7563 #define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
7564 #define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010)        /*!<Bit 0 */
7565 #define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020)        /*!<Bit 1 */
7566 
7567 /*******************  Bit definition for SAI_xCR1 register  *******************/
7568 #define  SAI_xCR1_MODE                    ((uint32_t)0x00000003)        /*!<MODE[1:0] bits (Audio Block Mode)           */
7569 #define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
7570 #define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
7571 
7572 #define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000C)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
7573 #define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004)        /*!<Bit 0 */
7574 #define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008)        /*!<Bit 1 */
7575 
7576 #define  SAI_xCR1_DS                      ((uint32_t)0x000000E0)        /*!<DS[1:0] bits (Data Size) */
7577 #define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020)        /*!<Bit 0 */
7578 #define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040)        /*!<Bit 1 */
7579 #define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080)        /*!<Bit 2 */
7580 
7581 #define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100)        /*!<LSB First Configuration  */
7582 #define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200)        /*!<ClocK STRobing edge      */
7583 
7584 #define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00)        /*!<SYNCEN[1:0](SYNChronization ENable) */
7585 #define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400)        /*!<Bit 0 */
7586 #define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800)        /*!<Bit 1 */
7587 
7588 #define  SAI_xCR1_MONO                    ((uint32_t)0x00001000)        /*!<Mono mode                  */
7589 #define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000)        /*!<Output Drive               */
7590 #define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000)        /*!<Audio Block enable         */
7591 #define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000)        /*!<DMA enable                 */
7592 #define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000)        /*!<No Divider Configuration   */
7593 
7594 #define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00780000)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
7595 #define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00080000)        /*!<Bit 0  */
7596 #define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00100000)        /*!<Bit 1  */
7597 #define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00200000)        /*!<Bit 2  */
7598 #define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00400000)        /*!<Bit 3  */
7599 
7600 /*******************  Bit definition for SAI_xCR2 register  *******************/
7601 #define  SAI_xCR2_FTH                     ((uint32_t)0x00000003)        /*!<FTH[1:0](Fifo THreshold)  */
7602 #define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
7603 #define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
7604 
7605 #define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008)        /*!<Fifo FLUSH                       */
7606 #define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010)        /*!<TRIState Management on data line */
7607 #define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020)        /*!<Mute mode                        */
7608 #define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040)        /*!<Muate value                      */
7609 
7610 #define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80)       /*!<MUTECNT[5:0] (MUTE counter) */
7611 #define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080)        /*!<Bit 0 */
7612 #define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100)        /*!<Bit 1 */
7613 #define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200)        /*!<Bit 2 */
7614 #define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400)        /*!<Bit 3 */
7615 #define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
7616 #define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
7617 
7618 #define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
7619 
7620 #define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
7621 #define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
7622 #define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000)        /*!<Bit 1 */
7623 
7624 /******************  Bit definition for SAI_xFRCR register  *******************/
7625 #define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FF)        /*!<FRL[1:0](Frame length)  */
7626 #define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
7627 #define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
7628 #define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
7629 #define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
7630 #define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
7631 #define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
7632 #define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
7633 #define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
7634 
7635 #define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00)        /*!<FRL[1:0] (Frame synchronization active level length)  */
7636 #define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100)        /*!<Bit 0 */
7637 #define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200)        /*!<Bit 1 */
7638 #define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400)        /*!<Bit 2 */
7639 #define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800)        /*!<Bit 3 */
7640 #define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000)        /*!<Bit 4 */
7641 #define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000)        /*!<Bit 5 */
7642 #define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000)        /*!<Bit 6 */
7643 
7644 #define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000)        /*!< Frame Synchronization Definition */
7645 #define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000)        /*!<Frame Synchronization POLarity    */
7646 #define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000)        /*!<Frame Synchronization OFFset      */
7647 
7648 /******************  Bit definition for SAI_xSLOTR register  *******************/
7649 #define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001F)        /*!<FRL[4:0](First Bit Offset)  */
7650 #define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001)        /*!<Bit 0 */
7651 #define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002)        /*!<Bit 1 */
7652 #define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004)        /*!<Bit 2 */
7653 #define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008)        /*!<Bit 3 */
7654 #define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010)        /*!<Bit 4 */
7655 
7656 #define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0)        /*!<SLOTSZ[1:0] (Slot size)  */
7657 #define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040)        /*!<Bit 0 */
7658 #define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080)        /*!<Bit 1 */
7659 
7660 #define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
7661 #define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100)        /*!<Bit 0 */
7662 #define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200)        /*!<Bit 1 */
7663 #define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400)        /*!<Bit 2 */
7664 #define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800)        /*!<Bit 3 */
7665 
7666 #define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000)        /*!<SLOTEN[15:0] (Slot Enable)  */
7667 
7668 /*******************  Bit definition for SAI_xIMR register  *******************/
7669 #define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001)        /*!<Overrun underrun interrupt enable                              */
7670 #define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002)        /*!<Mute detection interrupt enable                                */
7671 #define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004)        /*!<Wrong Clock Configuration interrupt enable                     */
7672 #define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008)        /*!<FIFO request interrupt enable                                  */
7673 #define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010)        /*!<Codec not ready interrupt enable                               */
7674 #define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020)        /*!<Anticipated frame synchronization detection interrupt enable   */
7675 #define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040)        /*!<Late frame synchronization detection interrupt enable          */
7676 
7677 /********************  Bit definition for SAI_xSR register  *******************/
7678 #define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001)         /*!<Overrun underrun                               */
7679 #define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002)         /*!<Mute detection                                 */
7680 #define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004)         /*!<Wrong Clock Configuration                      */
7681 #define  SAI_xSR_FREQ                     ((uint32_t)0x00000008)         /*!<FIFO request                                   */
7682 #define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010)         /*!<Codec not ready                                */
7683 #define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020)         /*!<Anticipated frame synchronization detection    */
7684 #define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040)         /*!<Late frame synchronization detection           */
7685 
7686 #define  SAI_xSR_FLVL                     ((uint32_t)0x00070000)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
7687 #define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000)         /*!<Bit 0 */
7688 #define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000)         /*!<Bit 1 */
7689 #define  SAI_xSR_FLVL_2                   ((uint32_t)0x00030000)         /*!<Bit 2 */
7690 
7691 /******************  Bit definition for SAI_xCLRFR register  ******************/
7692 #define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001)        /*!<Clear Overrun underrun                               */
7693 #define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002)        /*!<Clear Mute detection                                 */
7694 #define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004)        /*!<Clear Wrong Clock Configuration                      */
7695 #define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008)        /*!<Clear FIFO request                                   */
7696 #define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010)        /*!<Clear Codec not ready                                */
7697 #define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020)        /*!<Clear Anticipated frame synchronization detection    */
7698 #define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040)        /*!<Clear Late frame synchronization detection           */
7699 
7700 /******************  Bit definition for SAI_xDR register  ******************/
7701 #define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFF)
7702 
7703 /******************************************************************************/
7704 /*                                                                            */
7705 /*                          SD host Interface                                 */
7706 /*                                                                            */
7707 /******************************************************************************/
7708 /******************  Bit definition for SDIO_POWER register  ******************/
7709 #define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
7710 #define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!<Bit 0 */
7711 #define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!<Bit 1 */
7712 
7713 /******************  Bit definition for SDIO_CLKCR register  ******************/
7714 #define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!<Clock divide factor             */
7715 #define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!<Clock enable bit                */
7716 #define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!<Power saving configuration bit  */
7717 #define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!<Clock divider bypass enable bit */
7718 
7719 #define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
7720 #define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!<Bit 0 */
7721 #define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!<Bit 1 */
7722 
7723 #define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
7724 #define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!<HW Flow Control enable          */
7725 
7726 /*******************  Bit definition for SDIO_ARG register  *******************/
7727 #define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
7728 
7729 /*******************  Bit definition for SDIO_CMD register  *******************/
7730 #define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!<Command Index                               */
7731 
7732 #define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
7733 #define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!< Bit 0 */
7734 #define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!< Bit 1 */
7735 
7736 #define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
7737 #define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
7738 #define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
7739 #define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!<SD I/O suspend command                                         */
7740 #define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!<Enable CMD completion                                          */
7741 #define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!<Not Interrupt Enable */
7742 #define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!<CE-ATA command       */
7743 
7744 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
7745 #define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!<Response command index */
7746 
7747 /******************  Bit definition for SDIO_RESP0 register  ******************/
7748 #define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
7749 
7750 /******************  Bit definition for SDIO_RESP1 register  ******************/
7751 #define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
7752 
7753 /******************  Bit definition for SDIO_RESP2 register  ******************/
7754 #define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
7755 
7756 /******************  Bit definition for SDIO_RESP3 register  ******************/
7757 #define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
7758 
7759 /******************  Bit definition for SDIO_RESP4 register  ******************/
7760 #define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
7761 
7762 /******************  Bit definition for SDIO_DTIMER register  *****************/
7763 #define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
7764 
7765 /******************  Bit definition for SDIO_DLEN register  *******************/
7766 #define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
7767 
7768 /******************  Bit definition for SDIO_DCTRL register  ******************/
7769 #define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!<Data transfer enabled bit         */
7770 #define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!<Data transfer direction selection */
7771 #define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!<Data transfer mode selection      */
7772 #define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!<DMA enabled bit                   */
7773 
7774 #define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
7775 #define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!<Bit 0 */
7776 #define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!<Bit 1 */
7777 #define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!<Bit 2 */
7778 #define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!<Bit 3 */
7779 
7780 #define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!<Read wait start         */
7781 #define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!<Read wait stop          */
7782 #define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!<Read wait mode          */
7783 #define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!<SD I/O enable functions */
7784 
7785 /******************  Bit definition for SDIO_DCOUNT register  *****************/
7786 #define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
7787 
7788 /******************  Bit definition for SDIO_STA register  ********************/
7789 #define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
7790 #define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
7791 #define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
7792 #define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
7793 #define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
7794 #define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
7795 #define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
7796 #define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
7797 #define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
7798 #define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
7799 #define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
7800 #define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
7801 #define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
7802 #define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
7803 #define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
7804 #define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
7805 #define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
7806 #define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
7807 #define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
7808 #define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
7809 #define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
7810 #define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
7811 #define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
7812 #define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
7813 
7814 /*******************  Bit definition for SDIO_ICR register  *******************/
7815 #define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
7816 #define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
7817 #define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
7818 #define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
7819 #define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
7820 #define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
7821 #define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
7822 #define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
7823 #define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
7824 #define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
7825 #define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
7826 #define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
7827 #define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
7828 
7829 /******************  Bit definition for SDIO_MASK register  *******************/
7830 #define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
7831 #define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
7832 #define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
7833 #define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
7834 #define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
7835 #define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
7836 #define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
7837 #define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
7838 #define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
7839 #define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
7840 #define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
7841 #define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
7842 #define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
7843 #define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
7844 #define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
7845 #define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
7846 #define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
7847 #define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
7848 #define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
7849 #define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
7850 #define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
7851 #define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
7852 #define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
7853 #define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
7854 
7855 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
7856 #define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
7857 
7858 /******************  Bit definition for SDIO_FIFO register  *******************/
7859 #define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
7860 
7861 /******************************************************************************/
7862 /*                                                                            */
7863 /*                        Serial Peripheral Interface                         */
7864 /*                                                                            */
7865 /******************************************************************************/
7866 /*******************  Bit definition for SPI_CR1 register  ********************/
7867 #define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!<Clock Phase      */
7868 #define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!<Clock Polarity   */
7869 #define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!<Master Selection */
7870 
7871 #define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!<BR[2:0] bits (Baud Rate Control) */
7872 #define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!<Bit 0 */
7873 #define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!<Bit 1 */
7874 #define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!<Bit 2 */
7875 
7876 #define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!<SPI Enable                          */
7877 #define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!<Frame Format                        */
7878 #define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!<Internal slave select               */
7879 #define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!<Software slave management           */
7880 #define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!<Receive only                        */
7881 #define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!<Data Frame Format                   */
7882 #define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!<Transmit CRC next                   */
7883 #define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!<Hardware CRC calculation enable     */
7884 #define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!<Output enable in bidirectional mode */
7885 #define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!<Bidirectional data mode enable      */
7886 
7887 /*******************  Bit definition for SPI_CR2 register  ********************/
7888 #define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!<Rx Buffer DMA Enable                 */
7889 #define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!<Tx Buffer DMA Enable                 */
7890 #define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!<SS Output Enable                     */
7891 #define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!<Error Interrupt Enable               */
7892 #define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!<RX buffer Not Empty Interrupt Enable */
7893 #define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!<Tx buffer Empty Interrupt Enable     */
7894 
7895 /********************  Bit definition for SPI_SR register  ********************/
7896 #define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!<Receive buffer Not Empty */
7897 #define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!<Transmit buffer Empty    */
7898 #define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!<Channel side             */
7899 #define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!<Underrun flag            */
7900 #define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!<CRC Error flag           */
7901 #define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!<Mode fault               */
7902 #define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!<Overrun flag             */
7903 #define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!<Busy flag                */
7904 
7905 /********************  Bit definition for SPI_DR register  ********************/
7906 #define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!<Data Register           */
7907 
7908 /*******************  Bit definition for SPI_CRCPR register  ******************/
7909 #define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!<CRC polynomial register */
7910 
7911 /******************  Bit definition for SPI_RXCRCR register  ******************/
7912 #define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!<Rx CRC Register         */
7913 
7914 /******************  Bit definition for SPI_TXCRCR register  ******************/
7915 #define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!<Tx CRC Register         */
7916 
7917 /******************  Bit definition for SPI_I2SCFGR register  *****************/
7918 #define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
7919 
7920 #define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
7921 #define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
7922 #define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
7923 
7924 #define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity               */
7925 
7926 #define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
7927 #define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
7928 #define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
7929 
7930 #define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization                 */
7931 
7932 #define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
7933 #define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
7934 #define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
7935 
7936 #define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable         */
7937 #define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
7938 
7939 /******************  Bit definition for SPI_I2SPR register  *******************/
7940 #define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler         */
7941 #define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
7942 #define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable   */
7943 
7944 /******************************************************************************/
7945 /*                                                                            */
7946 /*                                 SYSCFG                                     */
7947 /*                                                                            */
7948 /******************************************************************************/
7949 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
7950 #define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
7951 #define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!<Bit 0 */
7952 #define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!<Bit 1 */
7953 #define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004) /*!<Bit 2 */
7954 
7955 #define SYSCFG_MEMRMP_FB_MODE           ((uint32_t)0x00000100) /*!< User Flash Bank mode */
7956 
7957 #define SYSCFG_MEMRMP_SWP_FMC           ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
7958 #define SYSCFG_MEMRMP_SWP_FMC_0         ((uint32_t)0x00000400) /*!<Bit 0 */
7959 #define SYSCFG_MEMRMP_SWP_FMC_1         ((uint32_t)0x00000800) /*!<Bit 1 */
7960 
7961 
7962 /******************  Bit definition for SYSCFG_PMC register  ******************/
7963 #define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
7964 #define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
7965 #define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
7966 #define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit  */
7967 
7968 #define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
7969 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
7970 #define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
7971 
7972 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
7973 #define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!<EXTI 0 configuration */
7974 #define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
7975 #define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
7976 #define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!<EXTI 3 configuration */
7977 /**
7978   * @brief   EXTI0 configuration
7979   */
7980 #define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!<PA[0] pin */
7981 #define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!<PB[0] pin */
7982 #define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!<PC[0] pin */
7983 #define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!<PD[0] pin */
7984 #define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!<PE[0] pin */
7985 #define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!<PF[0] pin */
7986 #define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) /*!<PG[0] pin */
7987 #define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) /*!<PH[0] pin */
7988 #define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) /*!<PI[0] pin */
7989 #define SYSCFG_EXTICR1_EXTI0_PJ         ((uint16_t)0x0009) /*!<PJ[0] pin */
7990 #define SYSCFG_EXTICR1_EXTI0_PK         ((uint16_t)0x000A) /*!<PK[0] pin */
7991 
7992 /**
7993   * @brief   EXTI1 configuration
7994   */
7995 #define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!<PA[1] pin */
7996 #define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!<PB[1] pin */
7997 #define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!<PC[1] pin */
7998 #define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!<PD[1] pin */
7999 #define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!<PE[1] pin */
8000 #define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!<PF[1] pin */
8001 #define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) /*!<PG[1] pin */
8002 #define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) /*!<PH[1] pin */
8003 #define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) /*!<PI[1] pin */
8004 #define SYSCFG_EXTICR1_EXTI1_PJ         ((uint16_t)0x0090) /*!<PJ[1] pin */
8005 #define SYSCFG_EXTICR1_EXTI1_PK         ((uint16_t)0x00A0) /*!<PK[1] pin */
8006 
8007 /**
8008   * @brief   EXTI2 configuration
8009   */
8010 #define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!<PA[2] pin */
8011 #define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!<PB[2] pin */
8012 #define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!<PC[2] pin */
8013 #define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!<PD[2] pin */
8014 #define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!<PE[2] pin */
8015 #define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!<PF[2] pin */
8016 #define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) /*!<PG[2] pin */
8017 #define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) /*!<PH[2] pin */
8018 #define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) /*!<PI[2] pin */
8019 #define SYSCFG_EXTICR1_EXTI2_PJ         ((uint16_t)0x0900) /*!<PJ[2] pin */
8020 #define SYSCFG_EXTICR1_EXTI2_PK         ((uint16_t)0x0A00) /*!<PK[2] pin */
8021 
8022 /**
8023   * @brief   EXTI3 configuration
8024   */
8025 #define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!<PA[3] pin */
8026 #define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!<PB[3] pin */
8027 #define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!<PC[3] pin */
8028 #define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!<PD[3] pin */
8029 #define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!<PE[3] pin */
8030 #define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!<PF[3] pin */
8031 #define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) /*!<PG[3] pin */
8032 #define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) /*!<PH[3] pin */
8033 #define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) /*!<PI[3] pin */
8034 #define SYSCFG_EXTICR1_EXTI3_PJ         ((uint16_t)0x9000) /*!<PJ[3] pin */
8035 #define SYSCFG_EXTICR1_EXTI3_PK         ((uint16_t)0xA000) /*!<PK[3] pin */
8036 
8037 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
8038 #define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!<EXTI 4 configuration */
8039 #define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
8040 #define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
8041 #define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!<EXTI 7 configuration */
8042 /**
8043   * @brief   EXTI4 configuration
8044   */
8045 #define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!<PA[4] pin */
8046 #define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!<PB[4] pin */
8047 #define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!<PC[4] pin */
8048 #define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!<PD[4] pin */
8049 #define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!<PE[4] pin */
8050 #define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!<PF[4] pin */
8051 #define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) /*!<PG[4] pin */
8052 #define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) /*!<PH[4] pin */
8053 #define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) /*!<PI[4] pin */
8054 #define SYSCFG_EXTICR2_EXTI4_PJ         ((uint16_t)0x0009) /*!<PJ[4] pin */
8055 #define SYSCFG_EXTICR2_EXTI4_PK         ((uint16_t)0x000A) /*!<PK[4] pin */
8056 
8057 /**
8058   * @brief   EXTI5 configuration
8059   */
8060 #define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!<PA[5] pin */
8061 #define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!<PB[5] pin */
8062 #define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!<PC[5] pin */
8063 #define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!<PD[5] pin */
8064 #define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!<PE[5] pin */
8065 #define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!<PF[5] pin */
8066 #define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) /*!<PG[5] pin */
8067 #define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) /*!<PH[5] pin */
8068 #define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) /*!<PI[5] pin */
8069 #define SYSCFG_EXTICR2_EXTI5_PJ         ((uint16_t)0x0090) /*!<PJ[5] pin */
8070 #define SYSCFG_EXTICR2_EXTI5_PK         ((uint16_t)0x00A0) /*!<PK[5] pin */
8071 
8072 /**
8073   * @brief   EXTI6 configuration
8074   */
8075 #define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!<PA[6] pin */
8076 #define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!<PB[6] pin */
8077 #define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!<PC[6] pin */
8078 #define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!<PD[6] pin */
8079 #define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!<PE[6] pin */
8080 #define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!<PF[6] pin */
8081 #define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) /*!<PG[6] pin */
8082 #define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) /*!<PH[6] pin */
8083 #define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) /*!<PI[6] pin */
8084 #define SYSCFG_EXTICR2_EXTI6_PJ         ((uint16_t)0x0900) /*!<PJ[6] pin */
8085 #define SYSCFG_EXTICR2_EXTI6_PK         ((uint16_t)0x0A00) /*!<PK[6] pin */
8086 
8087 /**
8088   * @brief   EXTI7 configuration
8089   */
8090 #define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!<PA[7] pin */
8091 #define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!<PB[7] pin */
8092 #define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!<PC[7] pin */
8093 #define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!<PD[7] pin */
8094 #define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!<PE[7] pin */
8095 #define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!<PF[7] pin */
8096 #define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) /*!<PG[7] pin */
8097 #define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) /*!<PH[7] pin */
8098 #define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) /*!<PI[7] pin */
8099 #define SYSCFG_EXTICR2_EXTI7_PJ         ((uint16_t)0x9000) /*!<PJ[7] pin */
8100 #define SYSCFG_EXTICR2_EXTI7_PK         ((uint16_t)0xA000) /*!<PK[7] pin */
8101 
8102 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
8103 #define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!<EXTI 8 configuration */
8104 #define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
8105 #define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
8106 #define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!<EXTI 11 configuration */
8107 
8108 /**
8109   * @brief   EXTI8 configuration
8110   */
8111 #define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!<PA[8] pin */
8112 #define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!<PB[8] pin */
8113 #define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!<PC[8] pin */
8114 #define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!<PD[8] pin */
8115 #define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!<PE[8] pin */
8116 #define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!<PF[8] pin */
8117 #define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) /*!<PG[8] pin */
8118 #define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) /*!<PH[8] pin */
8119 #define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) /*!<PI[8] pin */
8120 #define SYSCFG_EXTICR3_EXTI8_PJ         ((uint16_t)0x0009) /*!<PJ[8] pin */
8121 
8122 /**
8123   * @brief   EXTI9 configuration
8124   */
8125 #define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!<PA[9] pin */
8126 #define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!<PB[9] pin */
8127 #define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!<PC[9] pin */
8128 #define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!<PD[9] pin */
8129 #define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!<PE[9] pin */
8130 #define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!<PF[9] pin */
8131 #define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) /*!<PG[9] pin */
8132 #define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) /*!<PH[9] pin */
8133 #define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) /*!<PI[9] pin */
8134 #define SYSCFG_EXTICR3_EXTI9_PJ         ((uint16_t)0x0090) /*!<PJ[9] pin */
8135 
8136 /**
8137   * @brief   EXTI10 configuration
8138   */
8139 #define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!<PA[10] pin */
8140 #define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!<PB[10] pin */
8141 #define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!<PC[10] pin */
8142 #define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!<PD[10] pin */
8143 #define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!<PE[10] pin */
8144 #define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!<PF[10] pin */
8145 #define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) /*!<PG[10] pin */
8146 #define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) /*!<PH[10] pin */
8147 #define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) /*!<PI[10] pin */
8148 #define SYSCFG_EXTICR3_EXTI10_PJ        ((uint16_t)0x0900) /*!<PJ[10] pin */
8149 
8150 /**
8151   * @brief   EXTI11 configuration
8152   */
8153 #define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!<PA[11] pin */
8154 #define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!<PB[11] pin */
8155 #define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!<PC[11] pin */
8156 #define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!<PD[11] pin */
8157 #define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!<PE[11] pin */
8158 #define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!<PF[11] pin */
8159 #define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) /*!<PG[11] pin */
8160 #define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) /*!<PH[11] pin */
8161 #define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) /*!<PI[11] pin */
8162 #define SYSCFG_EXTICR3_EXTI11_PJ        ((uint16_t)0x9000) /*!<PJ[11] pin */
8163 
8164 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
8165 #define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!<EXTI 12 configuration */
8166 #define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
8167 #define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
8168 #define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!<EXTI 15 configuration */
8169 /**
8170   * @brief   EXTI12 configuration
8171   */
8172 #define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!<PA[12] pin */
8173 #define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!<PB[12] pin */
8174 #define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!<PC[12] pin */
8175 #define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!<PD[12] pin */
8176 #define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!<PE[12] pin */
8177 #define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!<PF[12] pin */
8178 #define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) /*!<PG[12] pin */
8179 #define SYSCFG_EXTICR4_EXTI12_PH        ((uint16_t)0x0007) /*!<PH[12] pin */
8180 #define SYSCFG_EXTICR4_EXTI12_PI        ((uint16_t)0x0008) /*!<PI[12] pin */
8181 #define SYSCFG_EXTICR4_EXTI12_PJ        ((uint16_t)0x0009) /*!<PJ[12] pin */
8182 
8183 /**
8184   * @brief   EXTI13 configuration
8185   */
8186 #define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!<PA[13] pin */
8187 #define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!<PB[13] pin */
8188 #define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!<PC[13] pin */
8189 #define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!<PD[13] pin */
8190 #define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!<PE[13] pin */
8191 #define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!<PF[13] pin */
8192 #define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) /*!<PG[13] pin */
8193 #define SYSCFG_EXTICR4_EXTI13_PH        ((uint16_t)0x0070) /*!<PH[13] pin */
8194 #define SYSCFG_EXTICR4_EXTI13_PI        ((uint16_t)0x0008) /*!<PI[13] pin */
8195 #define SYSCFG_EXTICR4_EXTI13_PJ        ((uint16_t)0x0009) /*!<PJ[13] pin */
8196 
8197 /**
8198   * @brief   EXTI14 configuration
8199   */
8200 #define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!<PA[14] pin */
8201 #define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!<PB[14] pin */
8202 #define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!<PC[14] pin */
8203 #define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!<PD[14] pin */
8204 #define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!<PE[14] pin */
8205 #define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!<PF[14] pin */
8206 #define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) /*!<PG[14] pin */
8207 #define SYSCFG_EXTICR4_EXTI14_PH        ((uint16_t)0x0700) /*!<PH[14] pin */
8208 #define SYSCFG_EXTICR4_EXTI14_PI        ((uint16_t)0x0800) /*!<PI[14] pin */
8209 #define SYSCFG_EXTICR4_EXTI14_PJ        ((uint16_t)0x0900) /*!<PJ[14] pin */
8210 
8211 /**
8212   * @brief   EXTI15 configuration
8213   */
8214 #define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!<PA[15] pin */
8215 #define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!<PB[15] pin */
8216 #define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!<PC[15] pin */
8217 #define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!<PD[15] pin */
8218 #define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!<PE[15] pin */
8219 #define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!<PF[15] pin */
8220 #define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) /*!<PG[15] pin */
8221 #define SYSCFG_EXTICR4_EXTI15_PH        ((uint16_t)0x7000) /*!<PH[15] pin */
8222 #define SYSCFG_EXTICR4_EXTI15_PI        ((uint16_t)0x8000) /*!<PI[15] pin */
8223 #define SYSCFG_EXTICR4_EXTI15_PJ        ((uint16_t)0x9000) /*!<PJ[15] pin */
8224 
8225 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
8226 #define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
8227 #define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
8228 
8229 /******************************************************************************/
8230 /*                                                                            */
8231 /*                                    TIM                                     */
8232 /*                                                                            */
8233 /******************************************************************************/
8234 /*******************  Bit definition for TIM_CR1 register  ********************/
8235 #define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable        */
8236 #define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable        */
8237 #define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
8238 #define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode        */
8239 #define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction             */
8240 
8241 #define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
8242 #define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
8243 #define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
8244 
8245 #define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable     */
8246 
8247 #define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
8248 #define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
8249 #define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
8250 
8251 /*******************  Bit definition for TIM_CR2 register  ********************/
8252 #define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
8253 #define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
8254 #define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection            */
8255 
8256 #define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
8257 #define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
8258 #define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
8259 #define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
8260 
8261 #define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
8262 #define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
8263 #define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
8264 #define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
8265 #define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
8266 #define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
8267 #define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
8268 #define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
8269 
8270 /*******************  Bit definition for TIM_SMCR register  *******************/
8271 #define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
8272 #define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
8273 #define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
8274 #define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
8275 
8276 #define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
8277 #define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
8278 #define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
8279 #define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
8280 
8281 #define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode                       */
8282 
8283 #define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
8284 #define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
8285 #define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
8286 #define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
8287 #define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
8288 
8289 #define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
8290 #define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
8291 #define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
8292 
8293 #define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable     */
8294 #define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
8295 
8296 /*******************  Bit definition for TIM_DIER register  *******************/
8297 #define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
8298 #define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
8299 #define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
8300 #define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
8301 #define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
8302 #define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable                 */
8303 #define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable             */
8304 #define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable               */
8305 #define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable            */
8306 #define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
8307 #define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
8308 #define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
8309 #define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
8310 #define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable               */
8311 #define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable           */
8312 
8313 /********************  Bit definition for TIM_SR register  ********************/
8314 #define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag              */
8315 #define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
8316 #define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
8317 #define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
8318 #define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
8319 #define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag                 */
8320 #define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag             */
8321 #define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag               */
8322 #define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
8323 #define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
8324 #define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
8325 #define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
8326 
8327 /*******************  Bit definition for TIM_EGR register  ********************/
8328 #define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation                         */
8329 #define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation              */
8330 #define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation              */
8331 #define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation              */
8332 #define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation              */
8333 #define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
8334 #define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation                        */
8335 #define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation                          */
8336 
8337 /******************  Bit definition for TIM_CCMR1 register  *******************/
8338 #define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
8339 #define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
8340 #define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
8341 
8342 #define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
8343 #define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable              */
8344 
8345 #define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
8346 #define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
8347 #define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
8348 #define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
8349 
8350 #define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
8351 
8352 #define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
8353 #define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
8354 #define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
8355 
8356 #define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
8357 #define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable              */
8358 
8359 #define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
8360 #define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
8361 #define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
8362 #define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
8363 
8364 #define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
8365 
8366 /*----------------------------------------------------------------------------*/
8367 
8368 #define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
8369 #define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
8370 #define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
8371 
8372 #define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
8373 #define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
8374 #define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
8375 #define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
8376 #define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
8377 
8378 #define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
8379 #define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
8380 #define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
8381 
8382 #define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
8383 #define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
8384 #define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
8385 #define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
8386 #define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
8387 
8388 /******************  Bit definition for TIM_CCMR2 register  *******************/
8389 #define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
8390 #define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
8391 #define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
8392 
8393 #define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable           */
8394 #define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable        */
8395 
8396 #define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
8397 #define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
8398 #define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
8399 #define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
8400 
8401 #define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
8402 
8403 #define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
8404 #define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
8405 #define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
8406 
8407 #define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable    */
8408 #define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
8409 
8410 #define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
8411 #define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
8412 #define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
8413 #define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
8414 
8415 #define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
8416 
8417 /*----------------------------------------------------------------------------*/
8418 
8419 #define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
8420 #define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
8421 #define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
8422 
8423 #define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
8424 #define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
8425 #define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
8426 #define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
8427 #define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
8428 
8429 #define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
8430 #define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
8431 #define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
8432 
8433 #define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
8434 #define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
8435 #define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
8436 #define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
8437 #define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
8438 
8439 /*******************  Bit definition for TIM_CCER register  *******************/
8440 #define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
8441 #define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
8442 #define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
8443 #define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
8444 #define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
8445 #define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
8446 #define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
8447 #define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
8448 #define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
8449 #define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
8450 #define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
8451 #define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
8452 #define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
8453 #define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
8454 #define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
8455 
8456 /*******************  Bit definition for TIM_CNT register  ********************/
8457 #define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value            */
8458 
8459 /*******************  Bit definition for TIM_PSC register  ********************/
8460 #define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value          */
8461 
8462 /*******************  Bit definition for TIM_ARR register  ********************/
8463 #define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
8464 
8465 /*******************  Bit definition for TIM_RCR register  ********************/
8466 #define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
8467 
8468 /*******************  Bit definition for TIM_CCR1 register  *******************/
8469 #define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
8470 
8471 /*******************  Bit definition for TIM_CCR2 register  *******************/
8472 #define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
8473 
8474 /*******************  Bit definition for TIM_CCR3 register  *******************/
8475 #define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
8476 
8477 /*******************  Bit definition for TIM_CCR4 register  *******************/
8478 #define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
8479 
8480 /*******************  Bit definition for TIM_BDTR register  *******************/
8481 #define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
8482 #define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
8483 #define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
8484 #define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
8485 #define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
8486 #define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
8487 #define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
8488 #define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
8489 #define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
8490 
8491 #define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
8492 #define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
8493 #define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
8494 
8495 #define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
8496 #define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode  */
8497 #define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable                      */
8498 #define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity                    */
8499 #define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable           */
8500 #define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable                */
8501 
8502 /*******************  Bit definition for TIM_DCR register  ********************/
8503 #define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
8504 #define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
8505 #define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
8506 #define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
8507 #define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
8508 #define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
8509 
8510 #define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
8511 #define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
8512 #define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
8513 #define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
8514 #define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
8515 #define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
8516 
8517 /*******************  Bit definition for TIM_DMAR register  *******************/
8518 #define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses                    */
8519 
8520 /*******************  Bit definition for TIM_OR register  *********************/
8521 #define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
8522 #define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
8523 #define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
8524 #define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
8525 #define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
8526 #define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
8527 
8528 
8529 /******************************************************************************/
8530 /*                                                                            */
8531 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
8532 /*                                                                            */
8533 /******************************************************************************/
8534 /*******************  Bit definition for USART_SR register  *******************/
8535 #define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error                 */
8536 #define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error                */
8537 #define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag             */
8538 #define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error                */
8539 #define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected           */
8540 #define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */
8541 #define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete        */
8542 #define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */
8543 #define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag     */
8544 #define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag                     */
8545 
8546 /*******************  Bit definition for USART_DR register  *******************/
8547 #define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */
8548 
8549 /******************  Bit definition for USART_BRR register  *******************/
8550 #define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */
8551 #define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */
8552 
8553 /******************  Bit definition for USART_CR1 register  *******************/
8554 #define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break                             */
8555 #define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup                        */
8556 #define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable                        */
8557 #define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable                     */
8558 #define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable                  */
8559 #define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable                  */
8560 #define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
8561 #define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable                    */
8562 #define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable                    */
8563 #define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection                       */
8564 #define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable                  */
8565 #define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method                          */
8566 #define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length                            */
8567 #define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable                           */
8568 #define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable         */
8569 
8570 /******************  Bit definition for USART_CR2 register  *******************/
8571 #define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node            */
8572 #define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length           */
8573 #define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
8574 #define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse                 */
8575 #define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase                          */
8576 #define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity                       */
8577 #define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable                         */
8578 
8579 #define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
8580 #define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
8581 #define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
8582 
8583 #define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */
8584 
8585 /******************  Bit definition for USART_CR3 register  *******************/
8586 #define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable      */
8587 #define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable            */
8588 #define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power              */
8589 #define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection       */
8590 #define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable       */
8591 #define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable       */
8592 #define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver         */
8593 #define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter      */
8594 #define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable                  */
8595 #define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable                  */
8596 #define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable        */
8597 #define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */
8598 
8599 /******************  Bit definition for USART_GTPR register  ******************/
8600 #define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
8601 #define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
8602 #define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
8603 #define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
8604 #define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
8605 #define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */
8606 #define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */
8607 #define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */
8608 #define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */
8609 
8610 #define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */
8611 
8612 /******************************************************************************/
8613 /*                                                                            */
8614 /*                            Window WATCHDOG                                 */
8615 /*                                                                            */
8616 /******************************************************************************/
8617 /*******************  Bit definition for WWDG_CR register  ********************/
8618 #define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
8619 #define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
8620 #define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
8621 #define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
8622 #define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
8623 #define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
8624 #define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
8625 #define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
8626 
8627 #define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
8628 
8629 /*******************  Bit definition for WWDG_CFR register  *******************/
8630 #define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
8631 #define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
8632 #define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
8633 #define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
8634 #define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
8635 #define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
8636 #define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
8637 #define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
8638 
8639 #define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
8640 #define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
8641 #define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
8642 
8643 #define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
8644 
8645 /*******************  Bit definition for WWDG_SR register  ********************/
8646 #define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
8647 
8648 
8649 /******************************************************************************/
8650 /*                                                                            */
8651 /*                                DBG                                         */
8652 /*                                                                            */
8653 /******************************************************************************/
8654 /********************  Bit definition for DBGMCU_IDCODE register  *************/
8655 #define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
8656 #define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
8657 
8658 /********************  Bit definition for DBGMCU_CR register  *****************/
8659 #define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
8660 #define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
8661 #define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
8662 #define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
8663 
8664 #define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
8665 #define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
8666 #define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
8667 
8668 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
8669 #define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
8670 #define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
8671 #define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
8672 #define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
8673 #define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
8674 #define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
8675 #define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
8676 #define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
8677 #define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
8678 #define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
8679 #define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
8680 #define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
8681 #define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
8682 #define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
8683 #define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
8684 #define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
8685 #define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
8686 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
8687 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
8688 
8689 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
8690 #define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
8691 #define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
8692 #define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
8693 #define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
8694 #define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
8695 
8696 /******************************************************************************/
8697 /*                                                                            */
8698 /*                Ethernet MAC Registers bits definitions                     */
8699 /*                                                                            */
8700 /******************************************************************************/
8701 /* Bit definition for Ethernet MAC Control Register register */
8702 #define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
8703 #define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
8704 #define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
8705 #define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
8706   #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
8707   #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
8708   #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
8709   #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */
8710   #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
8711   #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
8712   #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */
8713 #define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
8714 #define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
8715 #define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
8716 #define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
8717 #define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
8718 #define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
8719 #define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
8720 #define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
8721 #define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
8722                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
8723   #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
8724   #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
8725   #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
8726   #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */
8727 #define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
8728 #define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
8729 #define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
8730 
8731 /* Bit definition for Ethernet MAC Frame Filter Register */
8732 #define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */
8733 #define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */
8734 #define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */
8735 #define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */
8736 #define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
8737   #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
8738   #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
8739   #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
8740 #define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */
8741 #define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */
8742 #define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */
8743 #define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */
8744 #define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
8745 #define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
8746 
8747 /* Bit definition for Ethernet MAC Hash Table High Register */
8748 #define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
8749 
8750 /* Bit definition for Ethernet MAC Hash Table Low Register */
8751 #define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
8752 
8753 /* Bit definition for Ethernet MAC MII Address Register */
8754 #define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */
8755 #define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */
8756 #define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */
8757   #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
8758   #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
8759   #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
8760   #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
8761   #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
8762 #define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */
8763 #define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */
8764 
8765 /* Bit definition for Ethernet MAC MII Data Register */
8766 #define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
8767 
8768 /* Bit definition for Ethernet MAC Flow Control Register */
8769 #define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
8770 #define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
8771 #define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
8772   #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
8773   #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
8774   #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
8775   #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */
8776 #define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
8777 #define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
8778 #define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
8779 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
8780 
8781 /* Bit definition for Ethernet MAC VLAN Tag Register */
8782 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
8783 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
8784 
8785 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
8786 #define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
8787 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
8788    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
8789 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
8790    Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
8791    Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
8792    Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
8793    Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
8794                               RSVD - Filter1 Command - RSVD - Filter0 Command
8795    Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
8796    Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
8797    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
8798 
8799 /* Bit definition for Ethernet MAC PMT Control and Status Register */
8800 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
8801 #define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
8802 #define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
8803 #define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
8804 #define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
8805 #define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
8806 #define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
8807 
8808 /* Bit definition for Ethernet MAC Status Register */
8809 #define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
8810 #define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
8811 #define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
8812 #define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
8813 #define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
8814 
8815 /* Bit definition for Ethernet MAC Interrupt Mask Register */
8816 #define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
8817 #define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
8818 
8819 /* Bit definition for Ethernet MAC Address0 High Register */
8820 #define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
8821 
8822 /* Bit definition for Ethernet MAC Address0 Low Register */
8823 #define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
8824 
8825 /* Bit definition for Ethernet MAC Address1 High Register */
8826 #define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
8827 #define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
8828 #define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8829   #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
8830   #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
8831   #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
8832   #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
8833   #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
8834   #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */
8835 #define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
8836 
8837 /* Bit definition for Ethernet MAC Address1 Low Register */
8838 #define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
8839 
8840 /* Bit definition for Ethernet MAC Address2 High Register */
8841 #define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
8842 #define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
8843 #define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
8844   #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
8845   #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
8846   #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
8847   #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
8848   #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
8849   #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
8850 #define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
8851 
8852 /* Bit definition for Ethernet MAC Address2 Low Register */
8853 #define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
8854 
8855 /* Bit definition for Ethernet MAC Address3 High Register */
8856 #define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
8857 #define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
8858 #define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
8859   #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
8860   #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
8861   #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
8862   #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
8863   #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
8864   #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
8865 #define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
8866 
8867 /* Bit definition for Ethernet MAC Address3 Low Register */
8868 #define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
8869 
8870 /******************************************************************************/
8871 /*                Ethernet MMC Registers bits definition                      */
8872 /******************************************************************************/
8873 
8874 /* Bit definition for Ethernet MMC Contol Register */
8875 #define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */
8876 #define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */
8877 #define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
8878 #define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
8879 #define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
8880 #define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
8881 
8882 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8883 #define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
8884 #define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
8885 #define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
8886 
8887 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8888 #define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
8889 #define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
8890 #define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
8891 
8892 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8893 #define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8894 #define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8895 #define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8896 
8897 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8898 #define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8899 #define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8900 #define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8901 
8902 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8903 #define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8904 
8905 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8906 #define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8907 
8908 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8909 #define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
8910 
8911 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8912 #define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
8913 
8914 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8915 #define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
8916 
8917 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8918 #define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
8919 
8920 /******************************************************************************/
8921 /*               Ethernet PTP Registers bits definition                       */
8922 /******************************************************************************/
8923 
8924 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8925 #define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
8926 #define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
8927 #define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
8928 #define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
8929 #define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
8930 #define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
8931 #define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
8932 #define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
8933 #define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
8934 
8935 #define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
8936 #define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
8937 #define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
8938 #define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
8939 #define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
8940 #define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
8941 
8942 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8943 #define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
8944 
8945 /* Bit definition for Ethernet PTP Time Stamp High Register */
8946 #define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
8947 
8948 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8949 #define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
8950 #define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
8951 
8952 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8953 #define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
8954 
8955 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8956 #define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
8957 #define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
8958 
8959 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8960 #define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
8961 
8962 /* Bit definition for Ethernet PTP Target Time High Register */
8963 #define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
8964 
8965 /* Bit definition for Ethernet PTP Target Time Low Register */
8966 #define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
8967 
8968 /* Bit definition for Ethernet PTP Time Stamp Status Register */
8969 #define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
8970 #define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
8971 
8972 /******************************************************************************/
8973 /*                 Ethernet DMA Registers bits definition                     */
8974 /******************************************************************************/
8975 
8976 /* Bit definition for Ethernet DMA Bus Mode Register */
8977 #define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
8978 #define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
8979 #define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
8980 #define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
8981   #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8982   #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8983   #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8984   #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8985   #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8986   #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8987   #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8988   #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8989   #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8990   #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8991   #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8992   #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8993 #define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
8994 #define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
8995   #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
8996   #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
8997   #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
8998   #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
8999 #define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
9000   #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
9001   #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
9002   #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
9003   #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
9004   #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
9005   #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
9006   #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
9007   #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
9008   #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
9009   #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
9010   #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
9011   #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
9012 #define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
9013 #define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
9014 #define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
9015 #define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
9016 
9017 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
9018 #define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
9019 
9020 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
9021 #define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
9022 
9023 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
9024 #define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
9025 
9026 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
9027 #define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
9028 
9029 /* Bit definition for Ethernet DMA Status Register */
9030 #define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
9031 #define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
9032 #define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
9033 #define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
9034   /* combination with EBS[2:0] for GetFlagStatus function */
9035   #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
9036   #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
9037   #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
9038 #define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
9039   #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
9040   #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
9041   #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
9042   #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
9043   #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
9044   #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
9045 #define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
9046   #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
9047   #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
9048   #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
9049   #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
9050   #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
9051   #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
9052 #define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
9053 #define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
9054 #define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
9055 #define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
9056 #define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
9057 #define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
9058 #define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
9059 #define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
9060 #define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
9061 #define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
9062 #define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
9063 #define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
9064 #define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
9065 #define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
9066 #define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
9067 
9068 /* Bit definition for Ethernet DMA Operation Mode Register */
9069 #define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
9070 #define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
9071 #define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
9072 #define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
9073 #define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
9074 #define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
9075   #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
9076   #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
9077   #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
9078   #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
9079   #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
9080   #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
9081   #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
9082   #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
9083 #define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
9084 #define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
9085 #define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
9086 #define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
9087   #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
9088   #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
9089   #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
9090   #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
9091 #define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
9092 #define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
9093 
9094 /* Bit definition for Ethernet DMA Interrupt Enable Register */
9095 #define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
9096 #define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
9097 #define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
9098 #define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
9099 #define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
9100 #define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
9101 #define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
9102 #define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
9103 #define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
9104 #define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
9105 #define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
9106 #define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
9107 #define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
9108 #define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
9109 #define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
9110 
9111 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
9112 #define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
9113 #define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
9114 #define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
9115 #define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
9116 
9117 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
9118 #define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
9119 
9120 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
9121 #define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
9122 
9123 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
9124 #define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
9125 
9126 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
9127 #define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
9128 
9129 /**
9130   *
9131   */
9132 
9133  /**
9134   * @}
9135   */
9136 
9137 #ifdef USE_STDPERIPH_DRIVER
9138   #include "stm32f4xx_conf.h"
9139 #endif /* USE_STDPERIPH_DRIVER */
9140 
9141 /** @addtogroup Exported_macro
9142   * @{
9143   */
9144 
9145 #define SET_BIT(REG, BIT)     ((REG) |= (BIT))
9146 
9147 #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
9148 
9149 #define READ_BIT(REG, BIT)    ((REG) & (BIT))
9150 
9151 #define CLEAR_REG(REG)        ((REG) = (0x0))
9152 
9153 #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
9154 
9155 #define READ_REG(REG)         ((REG))
9156 
9157 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
9158 
9159 /**
9160   * @}
9161   */
9162 
9163 #ifdef __cplusplus
9164 }
9165 #endif /* __cplusplus */
9166 
9167 #endif /* __STM32F4xx_H */
9168 
9169 /**
9170   * @}
9171   */
9172 
9173   /**
9174   * @}
9175   */
9176 
9177 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
9178