1 /*
2 * Copyright (c) 2022 HPMicro
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include "board.h"
17 #include <hpm_pllctl_drv.h>
18 #include "hpm_pllctlv2_drv.h"
19 #include <hpm_gpio_drv.h>
20 #include "hpm_pcfg_drv.h"
21 #include <hpm_pllctlv2_drv.h>
22 /**
23 * @brief FLASH configuration option definitions:
24 * option[0]:
25 * [31:16] 0xfcf9 - FLASH configuration option tag
26 * [15:4] 0 - Reserved
27 * [3:0] option words (exclude option[0])
28 * option[1]:
29 * [31:28] Flash probe type
30 * 0 - SFDP SDR / 1 - SFDP DDR
31 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
32 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
33 * 6 - OctaBus DDR (SPI -> OPI DDR)
34 * 8 - Xccela DDR (SPI -> OPI DDR)
35 * 10 - EcoXiP DDR (SPI -> OPI DDR)
36 * [27:24] Command Pads after Power-on Reset
37 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
38 * [23:20] Command Pads after Configuring FLASH
39 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
40 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
41 * 0 - Not needed
42 * 1 - QE bit is at bit 6 in Status Register 1
43 * 2 - QE bit is at bit1 in Status Register 2
44 * 3 - QE bit is at bit7 in Status Register 2
45 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
46 * [15:8] Dummy cycles
47 * 0 - Auto-probed / detected / default value
48 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
49 * [7:4] Misc.
50 * 0 - Not used
51 * 1 - SPI mode
52 * 2 - Internal loopback
53 * 3 - External DQS
54 * [3:0] Frequency option
55 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
56 *
57 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
58 * [31:20] Reserved
59 * [19:16] IO voltage
60 * 0 - 3V / 1 - 1.8V
61 * [15:12] Pin group
62 * 0 - 1st group / 1 - 2nd group
63 * [11:8] Connection selection
64 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
65 * [7:0] Drive Strength
66 * 0 - Default value
67 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
68 * JESD216)
69 * [31:16] reserved
70 * [15:12] Sector Erase Command Option, not required here
71 * [11:8] Sector Size Option, not required here
72 * [7:0] Flash Size Option
73 * 0 - 4MB / 1 - 8MB / 2 - 16MB
74 */
75 #if defined(FLASH_XIP) && FLASH_XIP
76 __attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x00001000, 0x00000001};
77 #endif
78
board_delay_us(uint32_t us)79 void board_delay_us(uint32_t us)
80 {
81 clock_cpu_delay_us(us);
82 }
83
board_delay_ms(uint32_t ms)84 void board_delay_ms(uint32_t ms)
85 {
86 clock_cpu_delay_ms(ms);
87 }
88
board_init_clock(void)89 void board_init_clock(void)
90 {
91 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
92
93 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
94 /* Configure the External OSC ramp-up time: ~9ms */
95 pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
96
97 /* Select clock setting preset1 */
98 sysctl_clock_set_preset(HPM_SYSCTL, 2);
99 }
100
101 /* group0[0] */
102 clock_add_to_group(clock_cpu0, 0);
103 clock_add_to_group(clock_ahb, 0);
104 clock_add_to_group(clock_lmm0, 0);
105 clock_add_to_group(clock_mchtmr0, 0);
106 clock_add_to_group(clock_rom, 0);
107 clock_add_to_group(clock_can0, 0);
108 clock_add_to_group(clock_can1, 0);
109 clock_add_to_group(clock_can2, 0);
110 clock_add_to_group(clock_can3, 0);
111 clock_add_to_group(clock_ptpc, 0);
112 clock_add_to_group(clock_lin0, 0);
113 clock_add_to_group(clock_lin1, 0);
114 clock_add_to_group(clock_lin2, 0);
115 clock_add_to_group(clock_lin3, 0);
116 clock_add_to_group(clock_gptmr0, 0);
117 clock_add_to_group(clock_gptmr1, 0);
118 clock_add_to_group(clock_gptmr2, 0);
119 clock_add_to_group(clock_gptmr3, 0);
120 clock_add_to_group(clock_i2c0, 0);
121 clock_add_to_group(clock_i2c1, 0);
122 clock_add_to_group(clock_i2c2, 0);
123 clock_add_to_group(clock_i2c3, 0);
124 clock_add_to_group(clock_spi0, 0);
125 clock_add_to_group(clock_spi1, 0);
126 clock_add_to_group(clock_spi2, 0);
127 clock_add_to_group(clock_spi3, 0);
128 clock_add_to_group(clock_uart0, 0);
129 clock_add_to_group(clock_uart1, 0);
130 clock_add_to_group(clock_uart2, 0);
131 clock_add_to_group(clock_uart3, 0);
132 clock_add_to_group(clock_uart4, 0);
133 clock_add_to_group(clock_uart5, 0);
134 clock_add_to_group(clock_uart6, 0);
135 /* group0[1] */
136 clock_add_to_group(clock_uart7, 0);
137 clock_add_to_group(clock_watchdog0, 0);
138 clock_add_to_group(clock_watchdog1, 0);
139 clock_add_to_group(clock_mbx0, 0);
140 clock_add_to_group(clock_tsns, 0);
141 clock_add_to_group(clock_crc0, 0);
142 clock_add_to_group(clock_adc0, 0);
143 clock_add_to_group(clock_adc1, 0);
144 clock_add_to_group(clock_dac0, 0);
145 clock_add_to_group(clock_dac1, 0);
146 clock_add_to_group(clock_acmp, 0);
147 clock_add_to_group(clock_opa0, 0);
148 clock_add_to_group(clock_opa1, 0);
149 clock_add_to_group(clock_mot0, 0);
150 clock_add_to_group(clock_rng, 0);
151 clock_add_to_group(clock_sdp, 0);
152 clock_add_to_group(clock_kman, 0);
153 clock_add_to_group(clock_gpio, 0);
154 clock_add_to_group(clock_hdma, 0);
155 clock_add_to_group(clock_xpi0, 0);
156 clock_add_to_group(clock_usb0, 0);
157
158 /* Connect Group0 to CPU0 */
159 clock_connect_group_to_cpu(0, 0);
160
161 /* Bump up DCDC voltage to 1175mv */
162 pcfg_dcdc_set_voltage(HPM_PCFG, 1175);
163
164 /* Configure CPU to 480MHz, AXI/AHB to 160MHz */
165 sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3);
166 /* Configure PLL0 Post Divider */
167 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 960MHz */
168 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 600MHz */
169 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 400MHz */
170 /* Configure PLL0 Frequency to 960MHz */
171 pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 960000000);
172
173 clock_update_core_clock();
174
175 /* Configure mchtmr to 24MHz */
176 clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
177 }
178
board_init_pmp(void)179 void board_init_pmp(void)
180 {
181
182 }
183
board_init(void)184 void board_init(void)
185 {
186 board_init_clock();
187 sysctl_set_cpu_lp_mode(HPM_SYSCTL, HPM_CORE0, cpu_lp_mode_ungate_cpu_clock);
188 board_init_pmp();
189 }
190
board_print_clock_freq(void)191 void board_print_clock_freq(void)
192 {
193 printf("==============================\r\n");
194 printf(" %s clock summary\r\n", "HPM5300EVK");
195 printf("==============================\r\n");
196 printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
197 printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
198 printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
199 printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
200 printf("==============================\r\n");
201 }
202
board_print_banner(void)203 void board_print_banner(void)
204 {
205 const uint8_t banner[] = {"\n\
206 ----------------------------------------------------------------------\r\n\
207 $$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\r\n\
208 $$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\r\n\
209 $$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\r\n\
210 $$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\r\n\
211 $$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\r\n\
212 $$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\r\n\
213 $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\r\n\
214 \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\r\n\
215 ----------------------------------------------------------------------\r\n"};
216 printf("%s", banner);
217 }
218
init_gpio_pins(void)219 void init_gpio_pins(void)
220 {
221 HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = 0;
222 HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
223
224 HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = 0;
225 HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
226 }
227
init_gpio_out_task_pins(void)228 void init_gpio_out_task_pins(void)
229 {
230 HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = 0;
231 HPM_IOC->PAD[IOC_PAD_PA23].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
232
233 HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = 0;
234 HPM_IOC->PAD[IOC_PAD_PA25].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
235
236 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = 0;
237 HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
238 }
239
init_i2c_pins(I2C_Type * ptr)240 void init_i2c_pins(I2C_Type *ptr)
241 {
242 if (ptr == HPM_I2C0) {
243 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
244 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
245 HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
246 HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
247 } else {
248 ;
249 }
250 }
251
init_spi_pins(SPI_Type * ptr)252 void init_spi_pins(SPI_Type *ptr)
253 {
254 if (ptr == HPM_SPI1) {
255 HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_SPI1_CS_1;
256 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_SPI1_CS_0;
257 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
258 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
259 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
260 }
261 }
262
263