1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Rockchip Electronics Co.Ltd
4 * Author:
5 * Algea Cao <algea.cao@rock-chips.com>
6 */
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/extcon.h>
13 #include <linux/hdmi.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/of_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/regmap.h>
20 #include <linux/spinlock.h>
21
22 #include <drm/drm_atomic.h>
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_dsc.h>
26 #include <drm/drm_edid.h>
27 #include <drm/drm_encoder_slave.h>
28 #include <drm/drm_of.h>
29 #include <drm/drm_print.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/drm_scdc_helper.h>
32 #include <drm/bridge/dw_hdmi.h>
33
34 #include <uapi/linux/media-bus-format.h>
35 #include <uapi/linux/videodev2.h>
36
37 #include "dw-hdmi-qp-audio.h"
38 #include "dw-hdmi-qp.h"
39 #include "dw-hdmi-qp-cec.h"
40
41 #include <media/cec-notifier.h>
42
43 #define DDC_CI_ADDR 0x37
44 #define DDC_SEGMENT_ADDR 0x30
45
46 #define HDMI_EDID_LEN 512
47
48 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
49 #define SCDC_MIN_SOURCE_VERSION 0x1
50
51 #define HDMI14_MAX_TMDSCLK 340000000
52 #define HDMI20_MAX_TMDSCLK_KHZ 600000
53
54 static const unsigned int dw_hdmi_cable[] = {
55 EXTCON_DISP_HDMI,
56 EXTCON_NONE,
57 };
58
59 /*
60 * Unless otherwise noted, entries in this table are 100% optimization.
61 * Values can be obtained from hdmi_compute_n() but that function is
62 * slow so we pre-compute values we expect to see.
63 *
64 * All 32k and 48k values are expected to be the same (due to the way
65 * the math works) for any rate that's an exact kHz.
66 */
67 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
68 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
69 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
70 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
71 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
72 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
73 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
74 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
75 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
76 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
77 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
78 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
79 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
80 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
81 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
82 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
83 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
84 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
85 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
86 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
87 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
88 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
89 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
90 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
91 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
92 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
93 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
94 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
95 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
96 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
97 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
98 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
99 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
100 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
101 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
102 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
103 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
104 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
105
106 /* For 297 MHz+ HDMI spec have some other rule for setting N */
107 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
108 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
109
110 /* End of table */
111 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
112 };
113
114 static const struct drm_display_mode dw_hdmi_default_modes[] = {
115 /* 16 - 1920x1080@60Hz 16:9 */
116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
117 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
120 /* 2 - 720x480@60Hz 4:3 */
121 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
122 798, 858, 0, 480, 489, 495, 525, 0,
123 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
125 /* 4 - 1280x720@60Hz 16:9 */
126 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
127 1430, 1650, 0, 720, 725, 730, 750, 0,
128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
130 /* 31 - 1920x1080@50Hz 16:9 */
131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
135 /* 19 - 1280x720@50Hz 16:9 */
136 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
137 1760, 1980, 0, 720, 725, 730, 750, 0,
138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
140 /* 17 - 720x576@50Hz 4:3 */
141 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
142 796, 864, 0, 576, 581, 586, 625, 0,
143 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
145 /* 2 - 720x480@60Hz 4:3 */
146 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
147 798, 858, 0, 480, 489, 495, 525, 0,
148 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
150 };
151
152 enum frl_mask {
153 FRL_3GBPS_3LANE = 1,
154 FRL_6GBPS_3LANE,
155 FRL_6GBPS_4LANE,
156 FRL_8GBPS_4LANE,
157 FRL_10GBPS_4LANE,
158 FRL_12GBPS_4LANE,
159 };
160
161 struct hdmi_vmode_qp {
162 bool mdataenablepolarity;
163
164 unsigned int previous_pixelclock;
165 unsigned long mpixelclock;
166 unsigned int mpixelrepetitioninput;
167 unsigned int mpixelrepetitionoutput;
168 unsigned long previous_tmdsclock;
169 unsigned int mtmdsclock;
170 };
171
172 struct hdmi_qp_data_info {
173 unsigned int enc_in_bus_format;
174 unsigned int enc_out_bus_format;
175 unsigned int enc_in_encoding;
176 unsigned int enc_out_encoding;
177 unsigned int quant_range;
178 unsigned int pix_repet_factor;
179 struct hdmi_vmode_qp video_mode;
180 bool update;
181 };
182
183 struct dw_hdmi_qp_i2c {
184 struct i2c_adapter adap;
185
186 struct mutex lock; /* used to serialize data transfers */
187 struct completion cmp;
188 u32 stat;
189
190 u8 slave_reg;
191 bool is_regaddr;
192 bool is_segment;
193
194 unsigned int scl_high_ns;
195 unsigned int scl_low_ns;
196 };
197
198 struct dw_hdmi_phy_data {
199 enum dw_hdmi_phy_type type;
200 const char *name;
201 unsigned int gen;
202 bool has_svsret;
203 int (*configure)(struct dw_hdmi_qp *hdmi,
204 const struct dw_hdmi_plat_data *pdata,
205 unsigned long mpixelclock);
206 };
207
208 struct dw_hdmi_qp {
209 struct drm_connector connector;
210 struct drm_bridge bridge;
211 struct platform_device *hdcp_dev;
212 struct platform_device *audio;
213 struct platform_device *cec;
214 struct device *dev;
215 struct dw_hdmi_qp_i2c *i2c;
216
217 struct hdmi_qp_data_info hdmi_data;
218 const struct dw_hdmi_plat_data *plat_data;
219
220 int vic;
221 int main_irq;
222 int avp_irq;
223 int earc_irq;
224
225 u8 edid[HDMI_EDID_LEN];
226
227 struct {
228 const struct dw_hdmi_qp_phy_ops *ops;
229 const char *name;
230 void *data;
231 bool enabled;
232 } phy;
233
234 struct drm_display_mode previous_mode;
235
236 struct i2c_adapter *ddc;
237 void __iomem *regs;
238 bool sink_is_hdmi;
239 bool sink_has_audio;
240 bool dclk_en;
241
242 struct mutex mutex; /* for state below and previous_mode */
243 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */
244 enum drm_connector_force force; /* mutex-protected force state */
245 bool disabled; /* DRM has disabled our bridge */
246 bool bridge_is_on; /* indicates the bridge is on */
247 bool rxsense; /* rxsense state */
248 u8 phy_mask; /* desired phy int mask settings */
249 u8 mc_clkdis; /* clock disable register */
250
251 u32 scdc_intr;
252 u32 flt_intr;
253 u32 earc_intr;
254
255 struct mutex audio_mutex;
256 unsigned int sample_rate;
257 unsigned int audio_cts;
258 unsigned int audio_n;
259 bool audio_enable;
260 void (*enable_audio)(struct dw_hdmi_qp *hdmi);
261 void (*disable_audio)(struct dw_hdmi_qp *hdmi);
262
263 struct dentry *debugfs_dir;
264 bool scramble_low_rates;
265
266 struct extcon_dev *extcon;
267
268 struct regmap *regm;
269
270 bool initialized; /* hdmi is enabled before bind */
271 struct completion flt_cmp;
272 struct completion earc_cmp;
273
274 struct cec_notifier *cec_notifier;
275 struct cec_adapter *cec_adap;
276 struct mutex cec_notifier_mutex;
277
278 hdmi_codec_plugged_cb plugged_cb;
279 struct device *codec_dev;
280 enum drm_connector_status last_connector_result;
281 };
282
hdmi_writel(struct dw_hdmi_qp * hdmi,u32 val,int offset)283 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset)
284 {
285 regmap_write(hdmi->regm, offset, val);
286 }
287
hdmi_readl(struct dw_hdmi_qp * hdmi,int offset)288 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset)
289 {
290 unsigned int val = 0;
291
292 regmap_read(hdmi->regm, offset, &val);
293
294 return val;
295 }
296
handle_plugged_change(struct dw_hdmi_qp * hdmi,bool plugged)297 static void handle_plugged_change(struct dw_hdmi_qp *hdmi, bool plugged)
298 {
299 if (hdmi->plugged_cb && hdmi->codec_dev)
300 hdmi->plugged_cb(hdmi->codec_dev, plugged);
301 }
302
dw_hdmi_qp_set_plugged_cb(struct dw_hdmi_qp * hdmi,hdmi_codec_plugged_cb fn,struct device * codec_dev)303 int dw_hdmi_qp_set_plugged_cb(struct dw_hdmi_qp *hdmi, hdmi_codec_plugged_cb fn,
304 struct device *codec_dev)
305 {
306 bool plugged;
307
308 mutex_lock(&hdmi->mutex);
309 hdmi->plugged_cb = fn;
310 hdmi->codec_dev = codec_dev;
311 plugged = hdmi->last_connector_result == connector_status_connected;
312 handle_plugged_change(hdmi, plugged);
313 mutex_unlock(&hdmi->mutex);
314
315 return 0;
316 }
317 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_plugged_cb);
318
hdmi_modb(struct dw_hdmi_qp * hdmi,u32 data,u32 mask,u32 reg)319 static void hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, u32 reg)
320 {
321 regmap_update_bits(hdmi->regm, reg, mask, data);
322 }
323
hdmi_set_cts_n(struct dw_hdmi_qp * hdmi,unsigned int cts,unsigned int n)324 static void hdmi_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts,
325 unsigned int n)
326 {
327 /* Set N */
328 hdmi_modb(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0);
329
330 /* Set CTS */
331 if (cts)
332 hdmi_modb(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK,
333 AUDPKT_ACR_CONTROL1);
334 else
335 hdmi_modb(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK,
336 AUDPKT_ACR_CONTROL1);
337
338 hdmi_modb(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK,
339 AUDPKT_ACR_CONTROL1);
340 }
341
hdmi_match_tmds_n_table(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long freq)342 static int hdmi_match_tmds_n_table(struct dw_hdmi_qp *hdmi,
343 unsigned long pixel_clk,
344 unsigned long freq)
345 {
346 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
347 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
348 int i;
349
350 if (plat_data->tmds_n_table) {
351 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
352 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
353 tmds_n = &plat_data->tmds_n_table[i];
354 break;
355 }
356 }
357 }
358
359 if (tmds_n == NULL) {
360 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
361 if (pixel_clk == common_tmds_n_table[i].tmds) {
362 tmds_n = &common_tmds_n_table[i];
363 break;
364 }
365 }
366 }
367
368 if (tmds_n == NULL)
369 return -ENOENT;
370
371 switch (freq) {
372 case 32000:
373 return tmds_n->n_32k;
374 case 44100:
375 case 88200:
376 case 176400:
377 return (freq / 44100) * tmds_n->n_44k1;
378 case 48000:
379 case 96000:
380 case 192000:
381 return (freq / 48000) * tmds_n->n_48k;
382 default:
383 return -ENOENT;
384 }
385 }
386
hdmi_audio_math_diff(unsigned int freq,unsigned int n,unsigned int pixel_clk)387 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
388 unsigned int pixel_clk)
389 {
390 u64 final, diff;
391 u64 cts;
392
393 final = (u64)pixel_clk * n;
394
395 cts = final;
396 do_div(cts, 128 * freq);
397
398 diff = final - (u64)cts * (128 * freq);
399
400 return diff;
401 }
402
hdmi_compute_n(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long freq)403 static unsigned int hdmi_compute_n(struct dw_hdmi_qp *hdmi,
404 unsigned long pixel_clk,
405 unsigned long freq)
406 {
407 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
408 unsigned int max_n = (128 * freq) / 300;
409 unsigned int ideal_n = (128 * freq) / 1000;
410 unsigned int best_n_distance = ideal_n;
411 unsigned int best_n = 0;
412 u64 best_diff = U64_MAX;
413 int n;
414
415 /* If the ideal N could satisfy the audio math, then just take it */
416 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
417 return ideal_n;
418
419 for (n = min_n; n <= max_n; n++) {
420 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
421
422 if (diff < best_diff || (diff == best_diff &&
423 abs(n - ideal_n) < best_n_distance)) {
424 best_n = n;
425 best_diff = diff;
426 best_n_distance = abs(best_n - ideal_n);
427 }
428
429 /*
430 * The best N already satisfy the audio math, and also be
431 * the closest value to ideal N, so just cut the loop.
432 */
433 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
434 break;
435 }
436
437 return best_n;
438 }
439
hdmi_find_n(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long sample_rate)440 static unsigned int hdmi_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk,
441 unsigned long sample_rate)
442 {
443 int n;
444
445 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
446 if (n > 0)
447 return n;
448
449 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
450 pixel_clk);
451
452 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
453 }
454
455 /*
456 * When transmitting IEC60958 linear PCM audio, these registers allow to
457 * configure the channel status information of all the channel status
458 * bits in the IEC60958 frame. For the moment this configuration is only
459 * used when the I2S audio interface, General Purpose Audio (GPA),
460 * or AHB audio DMA (AHBAUDDMA) interface is active
461 * (for S/PDIF interface this information comes from the stream).
462 */
dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp * hdmi,u8 * channel_status,bool ref2stream)463 void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi,
464 u8 *channel_status, bool ref2stream)
465 {
466 mutex_lock(&hdmi->audio_mutex);
467 if (!hdmi->dclk_en) {
468 mutex_unlock(&hdmi->audio_mutex);
469 return;
470 }
471
472 /* Set channel status */
473 hdmi_writel(hdmi, channel_status[3] | (channel_status[4] << 8),
474 AUDPKT_CHSTATUS_OVR1);
475
476 if (ref2stream)
477 hdmi_modb(hdmi, 0,
478 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK,
479 AUDPKT_CONTROL0);
480 else
481 hdmi_modb(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN,
482 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK,
483 AUDPKT_CONTROL0);
484
485 mutex_unlock(&hdmi->audio_mutex);
486 }
487 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_status);
488
hdmi_set_clk_regenerator(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned int sample_rate)489 static void hdmi_set_clk_regenerator(struct dw_hdmi_qp *hdmi,
490 unsigned long pixel_clk, unsigned int sample_rate)
491 {
492 unsigned int n = 0, cts = 0;
493
494 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
495
496 hdmi->audio_n = n;
497 hdmi->audio_cts = cts;
498 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
499 }
500
hdmi_init_clk_regenerator(struct dw_hdmi_qp * hdmi)501 static void hdmi_init_clk_regenerator(struct dw_hdmi_qp *hdmi)
502 {
503 mutex_lock(&hdmi->audio_mutex);
504 if (hdmi->dclk_en)
505 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
506 mutex_unlock(&hdmi->audio_mutex);
507 }
508
hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi_qp * hdmi)509 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi_qp *hdmi)
510 {
511 mutex_lock(&hdmi->audio_mutex);
512 if (hdmi->dclk_en)
513 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
514 hdmi->sample_rate);
515 mutex_unlock(&hdmi->audio_mutex);
516 }
517
dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp * hdmi,unsigned int rate)518 void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned int rate)
519 {
520 mutex_lock(&hdmi->audio_mutex);
521 if (hdmi->dclk_en) {
522 hdmi->sample_rate = rate;
523 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
524 hdmi->sample_rate);
525 }
526 mutex_unlock(&hdmi->audio_mutex);
527 }
528 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_sample_rate);
529
dw_hdmi_qp_set_channel_count(struct dw_hdmi_qp * hdmi,unsigned int cnt)530 void dw_hdmi_qp_set_channel_count(struct dw_hdmi_qp *hdmi, unsigned int cnt)
531 {
532 }
533 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_count);
534
dw_hdmi_qp_set_channel_allocation(struct dw_hdmi_qp * hdmi,unsigned int ca)535 void dw_hdmi_qp_set_channel_allocation(struct dw_hdmi_qp *hdmi, unsigned int ca)
536 {
537 }
538 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_allocation);
539
dw_hdmi_qp_set_audio_infoframe(struct dw_hdmi_qp * hdmi,struct hdmi_codec_params * hparms)540 void dw_hdmi_qp_set_audio_infoframe(struct dw_hdmi_qp *hdmi,
541 struct hdmi_codec_params *hparms)
542 {
543 u8 infoframe_buf[HDMI_INFOFRAME_SIZE(AUDIO)];
544 int ret = 0;
545
546 ret = hdmi_audio_infoframe_pack(&hparms->cea, infoframe_buf,
547 sizeof(infoframe_buf));
548 if (!ret) {
549 dev_err(hdmi->dev, "%s: Failed to pack audio infoframe: %d\n",
550 __func__, ret);
551 return;
552 }
553
554 mutex_lock(&hdmi->audio_mutex);
555 if (!hdmi->dclk_en) {
556 mutex_unlock(&hdmi->audio_mutex);
557 return;
558 }
559
560 /*
561 * AUDI_CONTENTS0: { RSV, HB2, HB1, RSV }
562 * AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 }
563 * AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 }
564 *
565 * PB0: CheckSum
566 * PB1: | CT3 | CT2 | CT1 | CT0 | F13 | CC2 | CC1 | CC0 |
567 * PB2: | F27 | F26 | F25 | SF2 | SF1 | SF0 | SS1 | SS0 |
568 * PB3: | F37 | F36 | F35 | F34 | F33 | F32 | F31 | F30 |
569 * PB4: | CA7 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 |
570 * PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 |
571 * PB6~PB10: Reserved
572 *
573 * AUDI_CONTENTS0 default value defined by HDMI specification,
574 * and shall only be changed for debug purposes.
575 * So, we only configure payload byte from PB0~PB7(2 word total).
576 */
577 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &infoframe_buf[3], 2);
578
579 /* Enable ACR, AUDI, AMD */
580 hdmi_modb(hdmi,
581 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN,
582 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN,
583 PKTSCHED_PKT_EN);
584
585 /* Enable AUDS */
586 hdmi_modb(hdmi, PKTSCHED_AUDS_TX_EN, PKTSCHED_AUDS_TX_EN, PKTSCHED_PKT_EN);
587 mutex_unlock(&hdmi->audio_mutex);
588 }
589 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_audio_infoframe);
590
hdmi_enable_audio_clk(struct dw_hdmi_qp * hdmi,bool enable)591 static void hdmi_enable_audio_clk(struct dw_hdmi_qp *hdmi, bool enable)
592 {
593 if (enable)
594 hdmi_modb(hdmi, 0,
595 AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
596 else
597 hdmi_modb(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE,
598 AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
599 }
600
dw_hdmi_i2s_audio_enable(struct dw_hdmi_qp * hdmi)601 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi_qp *hdmi)
602 {
603 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
604 hdmi_enable_audio_clk(hdmi, true);
605 }
606
dw_hdmi_i2s_audio_disable(struct dw_hdmi_qp * hdmi)607 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi_qp *hdmi)
608 {
609 /* Disable AUDS, ACR, AUDI, AMD */
610 hdmi_modb(hdmi, 0,
611 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDS_TX_EN |
612 PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN,
613 PKTSCHED_PKT_EN);
614
615 hdmi_enable_audio_clk(hdmi, false);
616 }
617
dw_hdmi_qp_audio_enable(struct dw_hdmi_qp * hdmi)618 void dw_hdmi_qp_audio_enable(struct dw_hdmi_qp *hdmi)
619 {
620 mutex_lock(&hdmi->audio_mutex);
621 if (hdmi->dclk_en) {
622 hdmi->audio_enable = true;
623 if (hdmi->enable_audio)
624 hdmi->enable_audio(hdmi);
625 }
626 mutex_unlock(&hdmi->audio_mutex);
627 }
628 EXPORT_SYMBOL_GPL(dw_hdmi_qp_audio_enable);
629
dw_hdmi_qp_audio_disable(struct dw_hdmi_qp * hdmi)630 void dw_hdmi_qp_audio_disable(struct dw_hdmi_qp *hdmi)
631 {
632 mutex_lock(&hdmi->audio_mutex);
633 if (hdmi->dclk_en) {
634 hdmi->audio_enable = false;
635 if (hdmi->disable_audio)
636 hdmi->disable_audio(hdmi);
637 }
638 mutex_unlock(&hdmi->audio_mutex);
639 }
640 EXPORT_SYMBOL_GPL(dw_hdmi_qp_audio_disable);
641
hdmi_bus_fmt_is_rgb(unsigned int bus_format)642 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
643 {
644 switch (bus_format) {
645 case MEDIA_BUS_FMT_RGB888_1X24:
646 case MEDIA_BUS_FMT_RGB101010_1X30:
647 case MEDIA_BUS_FMT_RGB121212_1X36:
648 case MEDIA_BUS_FMT_RGB161616_1X48:
649 return true;
650
651 default:
652 return false;
653 }
654 }
655
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)656 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
657 {
658 switch (bus_format) {
659 case MEDIA_BUS_FMT_YUV8_1X24:
660 case MEDIA_BUS_FMT_YUV10_1X30:
661 case MEDIA_BUS_FMT_YUV12_1X36:
662 case MEDIA_BUS_FMT_YUV16_1X48:
663 return true;
664
665 default:
666 return false;
667 }
668 }
669
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)670 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
671 {
672 switch (bus_format) {
673 case MEDIA_BUS_FMT_UYVY8_1X16:
674 case MEDIA_BUS_FMT_UYVY10_1X20:
675 case MEDIA_BUS_FMT_UYVY12_1X24:
676 return true;
677
678 default:
679 return false;
680 }
681 }
682
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)683 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
684 {
685 switch (bus_format) {
686 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
687 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
688 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
689 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
690 return true;
691
692 default:
693 return false;
694 }
695 }
696
hdmi_bus_fmt_color_depth(unsigned int bus_format)697 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
698 {
699 switch (bus_format) {
700 case MEDIA_BUS_FMT_RGB888_1X24:
701 case MEDIA_BUS_FMT_YUV8_1X24:
702 case MEDIA_BUS_FMT_UYVY8_1X16:
703 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
704 return 8;
705
706 case MEDIA_BUS_FMT_RGB101010_1X30:
707 case MEDIA_BUS_FMT_YUV10_1X30:
708 case MEDIA_BUS_FMT_UYVY10_1X20:
709 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
710 return 10;
711
712 case MEDIA_BUS_FMT_RGB121212_1X36:
713 case MEDIA_BUS_FMT_YUV12_1X36:
714 case MEDIA_BUS_FMT_UYVY12_1X24:
715 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
716 return 12;
717
718 case MEDIA_BUS_FMT_RGB161616_1X48:
719 case MEDIA_BUS_FMT_YUV16_1X48:
720 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
721 return 16;
722
723 default:
724 return 0;
725 }
726 }
727
dw_hdmi_i2c_init(struct dw_hdmi_qp * hdmi)728 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi)
729 {
730 /* Software reset */
731 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
732
733 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
734
735 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
736
737 /* Clear DONE and ERROR interrupts */
738 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR,
739 MAINUNIT_1_INT_CLEAR);
740 }
741
dw_hdmi_i2c_read(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)742 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi,
743 unsigned char *buf, unsigned int length)
744 {
745 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
746 int stat;
747
748 if (!i2c->is_regaddr) {
749 dev_dbg(hdmi->dev, "set read register address to 0\n");
750 i2c->slave_reg = 0x00;
751 i2c->is_regaddr = true;
752 }
753
754 while (length--) {
755 reinit_completion(&i2c->cmp);
756
757 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
758 I2CM_INTERFACE_CONTROL0);
759
760 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK,
761 I2CM_INTERFACE_CONTROL0);
762
763 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
764 if (!stat) {
765 dev_err(hdmi->dev, "i2c read time out!\n");
766 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
767 return -EAGAIN;
768 }
769
770 /* Check for error condition on the bus */
771 if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
772 dev_err(hdmi->dev, "i2c read err!\n");
773 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
774 return -EIO;
775 }
776
777 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff;
778 dev_dbg(hdmi->dev, "i2c read done! i2c->stat:%02x 0x%02x\n",
779 i2c->stat, hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3));
780 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
781 }
782 i2c->is_segment = false;
783
784 return 0;
785 }
786
dw_hdmi_i2c_write(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)787 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi,
788 unsigned char *buf, unsigned int length)
789 {
790 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
791 int stat;
792
793 if (!i2c->is_regaddr) {
794 /* Use the first write byte as register address */
795 i2c->slave_reg = buf[0];
796 length--;
797 buf++;
798 i2c->is_regaddr = true;
799 }
800
801 while (length--) {
802 reinit_completion(&i2c->cmp);
803
804 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
805 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
806 I2CM_INTERFACE_CONTROL0);
807 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
808 I2CM_INTERFACE_CONTROL0);
809
810 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
811 if (!stat) {
812 dev_err(hdmi->dev, "i2c write time out!\n");
813 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
814 return -EAGAIN;
815 }
816
817 /* Check for error condition on the bus */
818 if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
819 dev_err(hdmi->dev, "i2c write nack!\n");
820 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
821 return -EIO;
822 }
823 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
824 }
825 dev_dbg(hdmi->dev, "i2c write done!\n");
826 return 0;
827 }
828
dw_hdmi_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)829 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
830 struct i2c_msg *msgs, int num)
831 {
832 struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap);
833 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
834 u8 addr = msgs[0].addr;
835 int i, ret = 0;
836
837 if (addr == DDC_CI_ADDR)
838 /*
839 * The internal I2C controller does not support the multi-byte
840 * read and write operations needed for DDC/CI.
841 * TOFIX: Blacklist the DDC/CI address until we filter out
842 * unsupported I2C operations.
843 */
844 return -EOPNOTSUPP;
845
846 dev_dbg(hdmi->dev, "i2c xfer: num: %d, addr: %#x\n", num, addr);
847
848 for (i = 0; i < num; i++) {
849 if (msgs[i].len == 0) {
850 dev_err(hdmi->dev,
851 "unsupported transfer %d/%d, no data\n",
852 i + 1, num);
853 return -EOPNOTSUPP;
854 }
855 }
856
857 mutex_lock(&i2c->lock);
858
859 /* Unmute DONE and ERROR interrupts */
860 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
861 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
862 MAINUNIT_1_INT_MASK_N);
863
864 /* Set slave device address taken from the first I2C message */
865 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
866 addr = DDC_ADDR;
867
868 hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0);
869
870 /* Set slave device register address on transfer */
871 i2c->is_regaddr = false;
872
873 /* Set segment pointer for I2C extended read mode operation */
874 i2c->is_segment = false;
875
876 for (i = 0; i < num; i++) {
877 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
878 i + 1, num, msgs[i].len, msgs[i].flags);
879
880 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
881 i2c->is_segment = true;
882 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR,
883 I2CM_INTERFACE_CONTROL1);
884 hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR,
885 I2CM_INTERFACE_CONTROL1);
886 } else {
887 if (msgs[i].flags & I2C_M_RD)
888 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
889 msgs[i].len);
890 else
891 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
892 msgs[i].len);
893 }
894 if (ret < 0)
895 break;
896 }
897
898 if (!ret)
899 ret = num;
900
901 /* Mute DONE and ERROR interrupts */
902 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N,
903 MAINUNIT_1_INT_MASK_N);
904
905 mutex_unlock(&i2c->lock);
906
907 return ret;
908 }
909
dw_hdmi_i2c_func(struct i2c_adapter * adapter)910 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
911 {
912 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
913 }
914
915 static const struct i2c_algorithm dw_hdmi_algorithm = {
916 .master_xfer = dw_hdmi_i2c_xfer,
917 .functionality = dw_hdmi_i2c_func,
918 };
919
dw_hdmi_i2c_adapter(struct dw_hdmi_qp * hdmi)920 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi_qp *hdmi)
921 {
922 struct i2c_adapter *adap;
923 struct dw_hdmi_qp_i2c *i2c;
924 int ret;
925
926 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
927 if (!i2c)
928 return ERR_PTR(-ENOMEM);
929
930 mutex_init(&i2c->lock);
931 init_completion(&i2c->cmp);
932
933 adap = &i2c->adap;
934 adap->class = I2C_CLASS_DDC;
935 adap->owner = THIS_MODULE;
936 adap->dev.parent = hdmi->dev;
937 adap->algo = &dw_hdmi_algorithm;
938 strscpy(adap->name, "ddc", sizeof(adap->name));
939 i2c_set_adapdata(adap, hdmi);
940
941 ret = i2c_add_adapter(adap);
942 if (ret) {
943 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
944 devm_kfree(hdmi->dev, i2c);
945 return ERR_PTR(ret);
946 }
947
948 hdmi->i2c = i2c;
949
950 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
951
952 return adap;
953 }
954
955 #define HDMI_PHY_EARC_MASK BIT(29)
956
dw_hdmi_qp_set_earc(struct dw_hdmi_qp * hdmi)957 int dw_hdmi_qp_set_earc(struct dw_hdmi_qp *hdmi)
958 {
959 u32 stat, ret;
960
961 /* set hdmi phy earc mode */
962 hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_PHY_EARC_MASK,
963 true);
964
965 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
966 &hdmi->previous_mode);
967 if (ret)
968 return ret;
969
970 reinit_completion(&hdmi->earc_cmp);
971
972 hdmi_modb(hdmi, EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ |
973 EARCRX_CMDC_DISCOVERY_DONE_IRQ,
974 EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ |
975 EARCRX_CMDC_DISCOVERY_DONE_IRQ, EARCRX_0_INT_MASK_N);
976
977 /* start discovery */
978 hdmi_modb(hdmi, EARCRX_CMDC_DISCOVERY_EN, EARCRX_CMDC_DISCOVERY_EN,
979 EARCRX_CMDC_CONTROL);
980
981 /*
982 * The eARC TX device drives a logic-high-voltage-level
983 * pulse on the physical HPD connector pin, after
984 * at least 100 ms of low voltage level to start the
985 * eARC Discovery process.
986 */
987 hdmi_modb(hdmi, EARCRX_CONNECTOR_HPD, EARCRX_CONNECTOR_HPD,
988 EARCRX_CMDC_CONTROL);
989
990 stat = wait_for_completion_timeout(&hdmi->earc_cmp, HZ / 10);
991 if (!stat)
992 return -EAGAIN;
993
994 if (hdmi->earc_intr & EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ) {
995 dev_err(hdmi->dev, "discovery timeout\n");
996 return -ETIMEDOUT;
997 } else if (hdmi->earc_intr & EARCRX_CMDC_DISCOVERY_DONE_IRQ) {
998 dev_info(hdmi->dev, "discovery done\n");
999 } else {
1000 dev_err(hdmi->dev, "discovery failed\n");
1001 return -EINVAL;
1002 }
1003
1004 hdmi_writel(hdmi, 1, EARCRX_DMAC_PHY_CONTROL);
1005 hdmi_modb(hdmi, EARCRX_CMDC_SWINIT_P, EARCRX_CMDC_SWINIT_P,
1006 EARCRX_CMDC_CONFIG0);
1007
1008 hdmi_writel(hdmi, 0xf3, EARCRX_DMAC_CONFIG);
1009 hdmi_writel(hdmi, 0x63, EARCRX_DMAC_CONTROL0);
1010 hdmi_writel(hdmi, 0xff, EARCRX_DMAC_CONTROL1);
1011
1012 hdmi_modb(hdmi, EARCRX_XACTREAD_STOP_CFG | EARCRX_XACTREAD_RETRY_CFG |
1013 EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 | EARCRX_CMDC_XACT_RESTART_EN,
1014 EARCRX_XACTREAD_STOP_CFG | EARCRX_XACTREAD_RETRY_CFG |
1015 EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 | EARCRX_CMDC_XACT_RESTART_EN,
1016 EARCRX_CMDC_CONFIG0);
1017
1018 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER0);
1019 hdmi_writel(hdmi, 0x1b0e, EARCRX_DMAC_CHSTATUS_STREAMER1);
1020 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER2);
1021 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER3);
1022 hdmi_writel(hdmi, 0xf2000000, EARCRX_DMAC_CHSTATUS_STREAMER4);
1023 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER5);
1024 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER6);
1025 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER7);
1026 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER8);
1027
1028 return 0;
1029 }
1030 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_earc);
1031
1032 /* -----------------------------------------------------------------------------
1033 * HDMI TX Setup
1034 */
1035
hdmi_config_AVI(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)1036 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi,
1037 const struct drm_connector *connector,
1038 const struct drm_display_mode *mode)
1039 {
1040 struct hdmi_avi_infoframe frame;
1041 u32 val, i, j;
1042 u8 buff[17];
1043 enum hdmi_quantization_range rgb_quant_range =
1044 hdmi->hdmi_data.quant_range;
1045
1046 /* Initialise info frame from DRM mode */
1047 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1048
1049 /*
1050 * Ignore monitor selectable quantization, use quantization set
1051 * by the user
1052 */
1053 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, rgb_quant_range);
1054 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1055 frame.colorspace = HDMI_COLORSPACE_YUV444;
1056 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1057 frame.colorspace = HDMI_COLORSPACE_YUV422;
1058 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1059 frame.colorspace = HDMI_COLORSPACE_YUV420;
1060 else
1061 frame.colorspace = HDMI_COLORSPACE_RGB;
1062
1063 /* Set up colorimetry */
1064 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1065 switch (hdmi->hdmi_data.enc_out_encoding) {
1066 case V4L2_YCBCR_ENC_601:
1067 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1068 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1069 else
1070 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1071 frame.extended_colorimetry =
1072 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1073 break;
1074 case V4L2_YCBCR_ENC_709:
1075 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1076 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1077 else
1078 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1079 frame.extended_colorimetry =
1080 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1081 break;
1082 case V4L2_YCBCR_ENC_BT2020:
1083 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020)
1084 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1085 else
1086 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1087 frame.extended_colorimetry =
1088 HDMI_EXTENDED_COLORIMETRY_BT2020;
1089 break;
1090 default: /* Carries no data */
1091 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1092 frame.extended_colorimetry =
1093 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1094 break;
1095 }
1096 } else {
1097 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1098 frame.extended_colorimetry =
1099 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1100 }
1101
1102 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1103
1104 hdmi_avi_infoframe_pack_only(&frame, buff, 17);
1105
1106 /*
1107 * The Designware IP uses a different byte format from standard
1108 * AVI info frames, though generally the bits are in the correct
1109 * bytes.
1110 */
1111
1112 val = (frame.version << 8) | (frame.length << 16);
1113 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0);
1114
1115 for (i = 0; i < 4; i++) {
1116 for (j = 0; j < 4; j++) {
1117 if (i * 4 + j >= 14)
1118 break;
1119 if (!j)
1120 val = buff[i * 4 + j + 3];
1121 val |= buff[i * 4 + j + 3] << (8 * j);
1122 }
1123
1124 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4);
1125 }
1126
1127 hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
1128
1129 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
1130 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
1131 PKTSCHED_PKT_EN);
1132 }
1133
hdmi_config_CVTEM(struct dw_hdmi_qp * hdmi)1134 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi)
1135 {
1136 u8 ds_type = 0;
1137 u8 sync = 1;
1138 u8 vfr = 1;
1139 u8 afr = 0;
1140 u8 new = 1;
1141 u8 end = 0;
1142 u8 data_set_length = 136;
1143 u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 };
1144 u8 *pps_body;
1145 u32 val, i, reg;
1146 struct drm_display_mode *mode = &hdmi->previous_mode;
1147 int hsync, hfront, hback;
1148 struct dw_hdmi_link_config *link_cfg;
1149 void *data = hdmi->plat_data->phy_data;
1150
1151 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN);
1152
1153 if (hdmi->plat_data->get_link_cfg) {
1154 link_cfg = hdmi->plat_data->get_link_cfg(data);
1155 } else {
1156 dev_err(hdmi->dev, "can't get frl link cfg\n");
1157 return;
1158 }
1159
1160 if (!link_cfg->dsc_mode) {
1161 dev_info(hdmi->dev, "don't use dsc mode\n");
1162 return;
1163 }
1164
1165 pps_body = link_cfg->pps_payload;
1166
1167 hsync = mode->hsync_end - mode->hsync_start;
1168 hback = mode->htotal - mode->hsync_end;
1169 hfront = mode->hsync_start - mode->hdisplay;
1170
1171 for (i = 0; i < 6; i++) {
1172 val = i << 16 | hb1[i] << 8;
1173 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20);
1174 }
1175
1176 val = new << 7 | end << 6 | ds_type << 4 | afr << 3 |
1177 vfr << 2 | sync << 1;
1178 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1);
1179
1180 val = data_set_length << 16 | pps_body[0] << 24;
1181 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2);
1182
1183 reg = PKT0_EMP_CVTEM_CONTENTS3;
1184 for (i = 1; i < 125; i++) {
1185 if (reg == PKT1_EMP_CVTEM_CONTENTS0 ||
1186 reg == PKT2_EMP_CVTEM_CONTENTS0 ||
1187 reg == PKT3_EMP_CVTEM_CONTENTS0 ||
1188 reg == PKT4_EMP_CVTEM_CONTENTS0 ||
1189 reg == PKT5_EMP_CVTEM_CONTENTS0) {
1190 reg += 4;
1191 i--;
1192 continue;
1193 }
1194 if (i % 4 == 1)
1195 val = pps_body[i];
1196 if (i % 4 == 2)
1197 val |= pps_body[i] << 8;
1198 if (i % 4 == 3)
1199 val |= pps_body[i] << 16;
1200 if (!(i % 4)) {
1201 val |= pps_body[i] << 24;
1202 hdmi_writel(hdmi, val, reg);
1203 reg += 4;
1204 }
1205 }
1206
1207 val = (hfront & 0xff) << 24 | pps_body[127] << 16 |
1208 pps_body[126] << 8 | pps_body[125];
1209 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6);
1210
1211 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 |
1212 (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff);
1213 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7);
1214
1215 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff);
1216 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1);
1217
1218 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4)
1219 hdmi_writel(hdmi, 0, i);
1220
1221 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN,
1222 PKTSCHED_PKT_EN);
1223 }
1224
hdmi_config_drm_infoframe(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector)1225 static void hdmi_config_drm_infoframe(struct dw_hdmi_qp *hdmi,
1226 const struct drm_connector *connector)
1227 {
1228 const struct drm_connector_state *conn_state = connector->state;
1229 struct hdr_output_metadata *hdr_metadata;
1230 struct hdmi_drm_infoframe frame;
1231 u8 buffer[30];
1232 ssize_t err;
1233 int i;
1234 u32 val;
1235
1236 if (!hdmi->plat_data->use_drm_infoframe)
1237 return;
1238
1239 hdmi_modb(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
1240
1241 if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
1242 DRM_DEBUG("No need to set HDR metadata in infoframe\n");
1243 return;
1244 }
1245
1246 if (!conn_state->hdr_output_metadata) {
1247 DRM_DEBUG("source metadata not set yet\n");
1248 return;
1249 }
1250
1251 hdr_metadata = (struct hdr_output_metadata *)
1252 conn_state->hdr_output_metadata->data;
1253
1254 if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf &
1255 BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
1256 DRM_ERROR("Not support EOTF %d\n",
1257 hdr_metadata->hdmi_metadata_type1.eotf);
1258 return;
1259 }
1260
1261 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1262 if (err < 0)
1263 return;
1264
1265 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1266 if (err < 0) {
1267 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1268 return;
1269 }
1270
1271 val = (frame.version << 8) | (frame.length << 16);
1272 hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS0);
1273
1274 for (i = 0; i <= frame.length; i++) {
1275 if (i % 4 == 0)
1276 val = buffer[3 + i];
1277 val |= buffer[3 + i] << ((i % 4) * 8);
1278
1279 if (i % 4 == 3 || (i == (frame.length)))
1280 hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS1 + ((i / 4) * 4));
1281 }
1282
1283 hdmi_modb(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
1284
1285 hdmi_modb(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
1286
1287 DRM_DEBUG("%s eotf %d end\n", __func__,
1288 hdr_metadata->hdmi_metadata_type1.eotf);
1289 }
1290
1291 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
dw_hdmi_support_scdc(struct dw_hdmi_qp * hdmi,const struct drm_display_info * display)1292 static bool dw_hdmi_support_scdc(struct dw_hdmi_qp *hdmi,
1293 const struct drm_display_info *display)
1294 {
1295 /* Disable if no DDC bus */
1296 if (!hdmi->ddc)
1297 return false;
1298
1299 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1300 if (!display->hdmi.scdc.supported ||
1301 !display->hdmi.scdc.scrambling.supported)
1302 return false;
1303
1304 /*
1305 * Disable if display only support low TMDS rates and scrambling
1306 * for low rates is not supported either
1307 */
1308 if (!display->hdmi.scdc.scrambling.low_rates &&
1309 display->max_tmds_clock <= 340000)
1310 return false;
1311
1312 return true;
1313 }
1314
hdmi_set_frl_mask(int frl_rate)1315 static int hdmi_set_frl_mask(int frl_rate)
1316 {
1317 switch (frl_rate) {
1318 case 48:
1319 return FRL_12GBPS_4LANE;
1320 case 40:
1321 return FRL_10GBPS_4LANE;
1322 case 32:
1323 return FRL_8GBPS_4LANE;
1324 case 24:
1325 return FRL_6GBPS_4LANE;
1326 case 18:
1327 return FRL_6GBPS_3LANE;
1328 case 9:
1329 return FRL_3GBPS_3LANE;
1330 }
1331
1332 return 0;
1333 }
1334
hdmi_start_flt(struct dw_hdmi_qp * hdmi,u8 rate)1335 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate)
1336 {
1337 u8 val;
1338 u8 ffe_lv = 0;
1339 int i = 0, stat;
1340
1341 /* FLT_READY & FFE_LEVELS read */
1342 for (i = 0; i < 20; i++) {
1343 drm_scdc_readb(hdmi->ddc, SCDC_STATUS_FLAGS_0, &val);
1344 if (val & BIT(6))
1345 break;
1346 msleep(20);
1347 }
1348
1349 if (i == 20) {
1350 dev_err(hdmi->dev, "sink flt isn't ready\n");
1351 return -EINVAL;
1352 }
1353
1354 hdmi_modb(hdmi, SCDC_UPD_FLAGS_RD_IRQ, SCDC_UPD_FLAGS_RD_IRQ,
1355 MAINUNIT_1_INT_MASK_N);
1356 hdmi_modb(hdmi, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR,
1357 SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR,
1358 SCDC_CONFIG0);
1359
1360 /* max ffe level 3 */
1361 val = 3 << 4 | hdmi_set_frl_mask(rate);
1362 drm_scdc_writeb(hdmi->ddc, 0x31, val);
1363
1364 /* select FRL_RATE & FFE_LEVELS */
1365 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0);
1366
1367 /* Start LTS_3 state in source DUT */
1368 reinit_completion(&hdmi->flt_cmp);
1369 hdmi_modb(hdmi, FLT_EXIT_TO_LTSP_IRQ, FLT_EXIT_TO_LTSP_IRQ,
1370 MAINUNIT_1_INT_MASK_N);
1371 hdmi_writel(hdmi, 1, FLT_CONTROL0);
1372
1373 /* wait for completed link training at source side */
1374 stat = wait_for_completion_timeout(&hdmi->flt_cmp, HZ * 2);
1375 if (!stat) {
1376 dev_err(hdmi->dev, "wait lts3 finish time out\n");
1377 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN |
1378 SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
1379 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ,
1380 MAINUNIT_1_INT_MASK_N);
1381 return -EAGAIN;
1382 }
1383
1384 if (!(hdmi->flt_intr & FLT_EXIT_TO_LTSP_IRQ)) {
1385 dev_err(hdmi->dev, "not to ltsp\n");
1386 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN |
1387 SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
1388 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ,
1389 MAINUNIT_1_INT_MASK_N);
1390 return -EINVAL;
1391 }
1392
1393 return 0;
1394 }
1395
1396 #define HDMI_MODE_FRL_MASK BIT(30)
1397
hdmi_set_op_mode(struct dw_hdmi_qp * hdmi,struct dw_hdmi_link_config * link_cfg,const struct drm_connector * connector)1398 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi,
1399 struct dw_hdmi_link_config *link_cfg,
1400 const struct drm_connector *connector)
1401 {
1402 int frl_rate;
1403
1404 /* set sink frl mode disable and wait sink ready */
1405 hdmi_writel(hdmi, 0, FLT_CONFIG0);
1406 if (dw_hdmi_support_scdc(hdmi, &connector->display_info))
1407 drm_scdc_writeb(hdmi->ddc, 0x31, 0);
1408 /*
1409 * some TVs must wait a while before switching frl mode resolution,
1410 * or the signal may not be recognized.
1411 */
1412 msleep(200);
1413 if (!link_cfg->frl_mode) {
1414 dev_info(hdmi->dev, "dw hdmi qp use tmds mode\n");
1415 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0);
1416 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0);
1417 return;
1418 }
1419
1420 if (link_cfg->frl_lanes == 4)
1421 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES,
1422 LINK_CONFIG0);
1423 else
1424 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0);
1425
1426 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0);
1427
1428 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane;
1429 hdmi_start_flt(hdmi, frl_rate);
1430 }
1431
1432 static unsigned long
hdmi_get_tmdsclock(struct dw_hdmi_qp * hdmi,unsigned long mpixelclock)1433 hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock)
1434 {
1435 unsigned long tmdsclock = mpixelclock;
1436 unsigned int depth =
1437 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
1438
1439 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1440 switch (depth) {
1441 case 16:
1442 tmdsclock = mpixelclock * 2;
1443 break;
1444 case 12:
1445 tmdsclock = mpixelclock * 3 / 2;
1446 break;
1447 case 10:
1448 tmdsclock = mpixelclock * 5 / 4;
1449 break;
1450 default:
1451 break;
1452 }
1453 }
1454
1455 return tmdsclock;
1456 }
1457
dw_hdmi_qp_setup(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector,struct drm_display_mode * mode)1458 static int dw_hdmi_qp_setup(struct dw_hdmi_qp *hdmi,
1459 const struct drm_connector *connector,
1460 struct drm_display_mode *mode)
1461 {
1462 int ret;
1463 void *data = hdmi->plat_data->phy_data;
1464 struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode;
1465 struct dw_hdmi_link_config *link_cfg;
1466 u8 bytes = 0;
1467
1468 hdmi->vic = drm_match_cea_mode(mode);
1469 if (!hdmi->vic)
1470 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1471 else
1472 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1473
1474 if (hdmi->plat_data->get_enc_out_encoding)
1475 hdmi->hdmi_data.enc_out_encoding =
1476 hdmi->plat_data->get_enc_out_encoding(data);
1477 else if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1478 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1479 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1480 (hdmi->vic == 17) || (hdmi->vic == 18))
1481 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1482 else
1483 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1484
1485 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1486 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1487 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1488 } else {
1489 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1490 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1491 }
1492 /* Get input format from plat data or fallback to RGB888 */
1493 if (hdmi->plat_data->get_input_bus_format)
1494 hdmi->hdmi_data.enc_in_bus_format =
1495 hdmi->plat_data->get_input_bus_format(data);
1496 else if (hdmi->plat_data->input_bus_format)
1497 hdmi->hdmi_data.enc_in_bus_format =
1498 hdmi->plat_data->input_bus_format;
1499 else
1500 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1501
1502 /* Default to RGB888 output format */
1503 if (hdmi->plat_data->get_output_bus_format)
1504 hdmi->hdmi_data.enc_out_bus_format =
1505 hdmi->plat_data->get_output_bus_format(data);
1506 else
1507 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1508
1509 /* Get input encoding from plat data or fallback to none */
1510 if (hdmi->plat_data->get_enc_in_encoding)
1511 hdmi->hdmi_data.enc_in_encoding =
1512 hdmi->plat_data->get_enc_in_encoding(data);
1513 else if (hdmi->plat_data->input_bus_encoding)
1514 hdmi->hdmi_data.enc_in_encoding =
1515 hdmi->plat_data->input_bus_encoding;
1516 else
1517 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1518
1519 if (hdmi->plat_data->get_quant_range)
1520 hdmi->hdmi_data.quant_range =
1521 hdmi->plat_data->get_quant_range(data);
1522 else
1523 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1524
1525 if (hdmi->plat_data->get_link_cfg)
1526 link_cfg = hdmi->plat_data->get_link_cfg(data);
1527 else
1528 return -EINVAL;
1529
1530 hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_MODE_FRL_MASK,
1531 link_cfg->frl_mode);
1532
1533 /*
1534 * According to the dw-hdmi specification 6.4.2
1535 * vp_pr_cd[3:0]:
1536 * 0000b: No pixel repetition (pixel sent only once)
1537 * 0001b: Pixel sent two times (pixel repeated once)
1538 */
1539 hdmi->hdmi_data.pix_repet_factor =
1540 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1541 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1542
1543 vmode->previous_pixelclock = vmode->mpixelclock;
1544 if (hdmi->plat_data->split_mode)
1545 mode->crtc_clock /= 2;
1546 vmode->mpixelclock = mode->crtc_clock * 1000;
1547 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1548 vmode->mpixelclock *= 2;
1549 dev_dbg(hdmi->dev, "final pixclk = %ld\n", vmode->mpixelclock);
1550 vmode->previous_tmdsclock = vmode->mtmdsclock;
1551 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
1552 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1553 vmode->mtmdsclock /= 2;
1554 dev_info(hdmi->dev, "final tmdsclk = %d\n", vmode->mtmdsclock);
1555
1556 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1557 if (ret)
1558 return ret;
1559
1560 if (hdmi->plat_data->set_grf_cfg)
1561 hdmi->plat_data->set_grf_cfg(data);
1562
1563 if (hdmi->sink_has_audio) {
1564 dev_dbg(hdmi->dev, "sink has audio support\n");
1565
1566 /* HDMI Initialization Step E - Configure audio */
1567 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1568 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
1569 }
1570
1571 /* not for DVI mode */
1572 if (hdmi->sink_is_hdmi) {
1573 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1574 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0);
1575 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
1576 if (!link_cfg->frl_mode) {
1577 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) {
1578 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, &bytes);
1579 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1580 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1581 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1582 drm_scdc_set_scrambling(hdmi->ddc, 1);
1583 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0);
1584 } else {
1585 if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) {
1586 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1587 drm_scdc_set_scrambling(hdmi->ddc, 0);
1588 }
1589 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0);
1590 }
1591 }
1592 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1593 hdmi_config_AVI(hdmi, connector, mode);
1594 hdmi_config_CVTEM(hdmi);
1595 hdmi_config_drm_infoframe(hdmi, connector);
1596 hdmi_set_op_mode(hdmi, link_cfg, connector);
1597 } else {
1598 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0);
1599 dev_info(hdmi->dev, "%s DVI mode\n", __func__);
1600 }
1601
1602 return 0;
1603 }
1604
1605 static enum drm_connector_status
dw_hdmi_connector_detect(struct drm_connector * connector,bool force)1606 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1607 {
1608 struct dw_hdmi_qp *hdmi =
1609 container_of(connector, struct dw_hdmi_qp, connector);
1610 struct dw_hdmi_qp *secondary = NULL;
1611 enum drm_connector_status result, result_secondary;
1612
1613 mutex_lock(&hdmi->mutex);
1614 hdmi->force = DRM_FORCE_UNSPECIFIED;
1615 mutex_unlock(&hdmi->mutex);
1616
1617 if (hdmi->plat_data->left)
1618 secondary = hdmi->plat_data->left;
1619 else if (hdmi->plat_data->right)
1620 secondary = hdmi->plat_data->right;
1621
1622 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
1623
1624 if (secondary) {
1625 result_secondary = secondary->phy.ops->read_hpd(secondary, secondary->phy.data);
1626 if (result == connector_status_connected &&
1627 result_secondary == connector_status_connected)
1628 result = connector_status_connected;
1629 else
1630 result = connector_status_disconnected;
1631 }
1632
1633 return result;
1634 }
1635
1636 static int
dw_hdmi_update_hdr_property(struct drm_connector * connector)1637 dw_hdmi_update_hdr_property(struct drm_connector *connector)
1638 {
1639 struct drm_device *dev = connector->dev;
1640 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp,
1641 connector);
1642 void *data = hdmi->plat_data->phy_data;
1643 const struct hdr_static_metadata *metadata =
1644 &connector->hdr_sink_metadata.hdmi_type1;
1645 size_t size = sizeof(*metadata);
1646 struct drm_property *property;
1647 struct drm_property_blob *blob;
1648 int ret;
1649
1650 if (hdmi->plat_data->get_hdr_property)
1651 property = hdmi->plat_data->get_hdr_property(data);
1652 else
1653 return -EINVAL;
1654
1655 if (hdmi->plat_data->get_hdr_blob)
1656 blob = hdmi->plat_data->get_hdr_blob(data);
1657 else
1658 return -EINVAL;
1659
1660 ret = drm_property_replace_global_blob(dev, &blob, size, metadata,
1661 &connector->base, property);
1662 return ret;
1663 }
1664
dw_hdmi_connector_get_modes(struct drm_connector * connector)1665 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1666 {
1667 struct dw_hdmi_qp *hdmi =
1668 container_of(connector, struct dw_hdmi_qp, connector);
1669 struct hdr_static_metadata *metedata =
1670 &connector->hdr_sink_metadata.hdmi_type1;
1671 struct edid *edid;
1672 struct drm_display_mode *mode;
1673 struct drm_display_info *info = &connector->display_info;
1674 void *data = hdmi->plat_data->phy_data;
1675 int i, ret = 0;
1676
1677 if (!hdmi->ddc)
1678 return 0;
1679
1680 memset(metedata, 0, sizeof(*metedata));
1681 edid = drm_get_edid(connector, hdmi->ddc);
1682 if (edid) {
1683 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1684 edid->width_cm, edid->height_cm);
1685
1686 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1687 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1688 drm_connector_update_edid_property(connector, edid);
1689 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
1690 if (hdmi->plat_data->get_edid_dsc_info)
1691 hdmi->plat_data->get_edid_dsc_info(data, edid);
1692 ret = drm_add_edid_modes(connector, edid);
1693 dw_hdmi_update_hdr_property(connector);
1694 if (ret > 0 && hdmi->plat_data->split_mode) {
1695 struct dw_hdmi_qp *secondary = NULL;
1696 void *secondary_data;
1697
1698 if (hdmi->plat_data->left)
1699 secondary = hdmi->plat_data->left;
1700 else if (hdmi->plat_data->right)
1701 secondary = hdmi->plat_data->right;
1702
1703 if (!secondary)
1704 return -ENOMEM;
1705 secondary_data = secondary->plat_data->phy_data;
1706
1707 list_for_each_entry(mode, &connector->probed_modes, head)
1708 hdmi->plat_data->convert_to_split_mode(mode);
1709
1710 secondary->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1711 secondary->sink_has_audio = drm_detect_monitor_audio(edid);
1712 cec_notifier_set_phys_addr_from_edid(secondary->cec_notifier, edid);
1713 if (secondary->plat_data->get_edid_dsc_info)
1714 secondary->plat_data->get_edid_dsc_info(secondary_data, edid);
1715 }
1716 kfree(edid);
1717 } else {
1718 hdmi->sink_is_hdmi = true;
1719 hdmi->sink_has_audio = true;
1720
1721 if (hdmi->plat_data->split_mode) {
1722 if (hdmi->plat_data->left) {
1723 hdmi->plat_data->left->sink_is_hdmi = true;
1724 hdmi->plat_data->left->sink_has_audio = true;
1725 } else if (hdmi->plat_data->right) {
1726 hdmi->plat_data->right->sink_is_hdmi = true;
1727 hdmi->plat_data->right->sink_has_audio = true;
1728 }
1729 }
1730
1731 for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) {
1732 const struct drm_display_mode *ptr =
1733 &dw_hdmi_default_modes[i];
1734
1735 mode = drm_mode_duplicate(connector->dev, ptr);
1736 if (mode) {
1737 if (!i)
1738 mode->type = DRM_MODE_TYPE_PREFERRED;
1739 drm_mode_probed_add(connector, mode);
1740 ret++;
1741 }
1742 }
1743 if (ret > 0 && hdmi->plat_data->split_mode) {
1744 struct drm_display_mode *mode;
1745
1746 list_for_each_entry(mode, &connector->probed_modes, head)
1747 hdmi->plat_data->convert_to_split_mode(mode);
1748 }
1749 info->edid_hdmi_dc_modes = 0;
1750 info->hdmi.y420_dc_modes = 0;
1751 info->color_formats = 0;
1752
1753 dev_info(hdmi->dev, "failed to get edid\n");
1754 }
1755
1756 return ret;
1757 }
1758
1759 static int
dw_hdmi_atomic_connector_set_property(struct drm_connector * connector,struct drm_connector_state * state,struct drm_property * property,uint64_t val)1760 dw_hdmi_atomic_connector_set_property(struct drm_connector *connector,
1761 struct drm_connector_state *state,
1762 struct drm_property *property,
1763 uint64_t val)
1764 {
1765 struct dw_hdmi_qp *hdmi =
1766 container_of(connector, struct dw_hdmi_qp, connector);
1767 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
1768
1769 if (ops && ops->set_property)
1770 return ops->set_property(connector, state, property,
1771 val, hdmi->plat_data->phy_data);
1772 else
1773 return -EINVAL;
1774 }
1775
1776 static int
dw_hdmi_atomic_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)1777 dw_hdmi_atomic_connector_get_property(struct drm_connector *connector,
1778 const struct drm_connector_state *state,
1779 struct drm_property *property,
1780 uint64_t *val)
1781 {
1782 struct dw_hdmi_qp *hdmi =
1783 container_of(connector, struct dw_hdmi_qp, connector);
1784 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
1785
1786 if (ops && ops->get_property)
1787 return ops->get_property(connector, state, property,
1788 val, hdmi->plat_data->phy_data);
1789 else
1790 return -EINVAL;
1791 }
1792
1793 static int
dw_hdmi_connector_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)1794 dw_hdmi_connector_set_property(struct drm_connector *connector,
1795 struct drm_property *property, uint64_t val)
1796 {
1797 return dw_hdmi_atomic_connector_set_property(connector, NULL,
1798 property, val);
1799 }
1800
dw_hdmi_attach_properties(struct dw_hdmi_qp * hdmi)1801 static void dw_hdmi_attach_properties(struct dw_hdmi_qp *hdmi)
1802 {
1803 unsigned int color = MEDIA_BUS_FMT_RGB888_1X24;
1804 const struct dw_hdmi_property_ops *ops =
1805 hdmi->plat_data->property_ops;
1806
1807 if (ops && ops->attach_properties)
1808 return ops->attach_properties(&hdmi->connector, color, 0,
1809 hdmi->plat_data->phy_data);
1810 }
1811
dw_hdmi_destroy_properties(struct dw_hdmi_qp * hdmi)1812 static void dw_hdmi_destroy_properties(struct dw_hdmi_qp *hdmi)
1813 {
1814 const struct dw_hdmi_property_ops *ops =
1815 hdmi->plat_data->property_ops;
1816
1817 if (ops && ops->destroy_properties)
1818 return ops->destroy_properties(&hdmi->connector,
1819 hdmi->plat_data->phy_data);
1820 }
1821
1822 static struct drm_encoder *
dw_hdmi_connector_best_encoder(struct drm_connector * connector)1823 dw_hdmi_connector_best_encoder(struct drm_connector *connector)
1824 {
1825 struct dw_hdmi_qp *hdmi =
1826 container_of(connector, struct dw_hdmi_qp, connector);
1827
1828 return hdmi->bridge.encoder;
1829 }
1830
dw_hdmi_color_changed(struct drm_connector * connector,struct drm_atomic_state * state)1831 static bool dw_hdmi_color_changed(struct drm_connector *connector,
1832 struct drm_atomic_state *state)
1833 {
1834 struct dw_hdmi_qp *hdmi =
1835 container_of(connector, struct dw_hdmi_qp, connector);
1836 void *data = hdmi->plat_data->phy_data;
1837 struct drm_connector_state *old_state =
1838 drm_atomic_get_old_connector_state(state, connector);
1839 struct drm_connector_state *new_state =
1840 drm_atomic_get_new_connector_state(state, connector);
1841 bool ret = false;
1842
1843 if (hdmi->plat_data->get_color_changed)
1844 ret = hdmi->plat_data->get_color_changed(data);
1845
1846 if (new_state->colorspace != old_state->colorspace)
1847 ret = true;
1848
1849 return ret;
1850 }
1851
hdr_metadata_equal(const struct drm_connector_state * old_state,const struct drm_connector_state * new_state)1852 static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
1853 const struct drm_connector_state *new_state)
1854 {
1855 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
1856 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
1857
1858 if (!old_blob || !new_blob)
1859 return old_blob == new_blob;
1860
1861 if (old_blob->length != new_blob->length)
1862 return false;
1863
1864 return !memcmp(old_blob->data, new_blob->data, old_blob->length);
1865 }
1866
dw_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1867 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
1868 struct drm_atomic_state *state)
1869 {
1870 struct drm_connector_state *old_state =
1871 drm_atomic_get_old_connector_state(state, connector);
1872 struct drm_connector_state *new_state =
1873 drm_atomic_get_new_connector_state(state, connector);
1874 struct drm_crtc *crtc = new_state->crtc;
1875 struct drm_crtc_state *crtc_state;
1876 struct dw_hdmi_qp *hdmi =
1877 container_of(connector, struct dw_hdmi_qp, connector);
1878 struct drm_display_mode *mode = NULL;
1879 void *data = hdmi->plat_data->phy_data;
1880 struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode;
1881
1882 if (!crtc)
1883 return 0;
1884
1885 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1886 if (IS_ERR(crtc_state))
1887 return PTR_ERR(crtc_state);
1888
1889 /*
1890 * If HDMI is enabled in uboot, it's need to record
1891 * drm_display_mode and set phy status to enabled.
1892 */
1893 if (!vmode->mpixelclock) {
1894 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1895 if (hdmi->plat_data->get_enc_in_encoding)
1896 hdmi->hdmi_data.enc_in_encoding =
1897 hdmi->plat_data->get_enc_in_encoding(data);
1898 if (hdmi->plat_data->get_enc_out_encoding)
1899 hdmi->hdmi_data.enc_out_encoding =
1900 hdmi->plat_data->get_enc_out_encoding(data);
1901 if (hdmi->plat_data->get_input_bus_format)
1902 hdmi->hdmi_data.enc_in_bus_format =
1903 hdmi->plat_data->get_input_bus_format(data);
1904 if (hdmi->plat_data->get_output_bus_format)
1905 hdmi->hdmi_data.enc_out_bus_format =
1906 hdmi->plat_data->get_output_bus_format(data);
1907
1908 mode = &crtc_state->mode;
1909 if (hdmi->plat_data->split_mode) {
1910 hdmi->plat_data->convert_to_origin_mode(mode);
1911 mode->crtc_clock /= 2;
1912 }
1913 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1914 vmode->mpixelclock = mode->crtc_clock * 1000;
1915 vmode->previous_pixelclock = mode->clock;
1916 vmode->previous_tmdsclock = mode->clock;
1917 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi,
1918 vmode->mpixelclock);
1919 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1920 vmode->mtmdsclock /= 2;
1921
1922 /*
1923 * If uboot logo enabled, atomic_enable won't be called,
1924 * but atomic_disable will be called when hdmi plug out.
1925 * That will cause dclk enable count is incorrect. So
1926 * we should check ipi/link/video clk to determine whether
1927 * uboot logo is enabled.
1928 */
1929 if (hdmi->initialized && !hdmi->dclk_en) {
1930 mutex_lock(&hdmi->audio_mutex);
1931 if (hdmi->plat_data->dclk_set)
1932 hdmi->plat_data->dclk_set(data, true);
1933 hdmi->dclk_en = true;
1934 mutex_unlock(&hdmi->audio_mutex);
1935 }
1936 }
1937
1938 if (!hdr_metadata_equal(old_state, new_state) ||
1939 dw_hdmi_color_changed(connector, state)) {
1940 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1941 if (IS_ERR(crtc_state))
1942 return PTR_ERR(crtc_state);
1943
1944 crtc_state->mode_changed = true;
1945 }
1946
1947 return 0;
1948 }
1949
dw_hdmi_connector_force(struct drm_connector * connector)1950 static void dw_hdmi_connector_force(struct drm_connector *connector)
1951 {
1952 struct dw_hdmi_qp *hdmi =
1953 container_of(connector, struct dw_hdmi_qp, connector);
1954
1955 mutex_lock(&hdmi->mutex);
1956
1957 if (hdmi->force != connector->force) {
1958 if (!hdmi->disabled && connector->force == DRM_FORCE_OFF)
1959 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI,
1960 false);
1961 else if (hdmi->disabled && connector->force == DRM_FORCE_ON)
1962 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI,
1963 true);
1964 }
1965
1966 hdmi->force = connector->force;
1967 mutex_unlock(&hdmi->mutex);
1968 }
1969
dw_hdmi_qp_fill_modes(struct drm_connector * connector,u32 max_x,u32 max_y)1970 static int dw_hdmi_qp_fill_modes(struct drm_connector *connector, u32 max_x,
1971 u32 max_y)
1972 {
1973 return drm_helper_probe_single_connector_modes(connector, 9000, 9000);
1974 }
1975
1976 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1977 .fill_modes = dw_hdmi_qp_fill_modes,
1978 .detect = dw_hdmi_connector_detect,
1979 .destroy = drm_connector_cleanup,
1980 .force = dw_hdmi_connector_force,
1981 .reset = drm_atomic_helper_connector_reset,
1982 .set_property = dw_hdmi_connector_set_property,
1983 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1984 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1985 .atomic_set_property = dw_hdmi_atomic_connector_set_property,
1986 .atomic_get_property = dw_hdmi_atomic_connector_get_property,
1987 };
1988
1989 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1990 .get_modes = dw_hdmi_connector_get_modes,
1991 .best_encoder = dw_hdmi_connector_best_encoder,
1992 .atomic_check = dw_hdmi_connector_atomic_check,
1993 };
1994
dw_hdmi_qp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1995 static int dw_hdmi_qp_bridge_attach(struct drm_bridge *bridge,
1996 enum drm_bridge_attach_flags flags)
1997 {
1998 struct dw_hdmi_qp *hdmi = bridge->driver_private;
1999 struct drm_encoder *encoder = bridge->encoder;
2000 struct drm_connector *connector = &hdmi->connector;
2001 struct cec_connector_info conn_info;
2002 struct cec_notifier *notifier;
2003
2004 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
2005 return 0;
2006
2007 connector->interlace_allowed = 1;
2008 connector->polled = DRM_CONNECTOR_POLL_HPD;
2009
2010 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2011
2012 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
2013 DRM_MODE_CONNECTOR_HDMIA);
2014
2015 drm_connector_attach_encoder(connector, encoder);
2016 dw_hdmi_attach_properties(hdmi);
2017
2018 cec_fill_conn_info_from_drm(&conn_info, connector);
2019 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2020 if (!notifier)
2021 return -ENOMEM;
2022
2023 mutex_lock(&hdmi->cec_notifier_mutex);
2024 hdmi->cec_notifier = notifier;
2025 mutex_unlock(&hdmi->cec_notifier_mutex);
2026
2027 return 0;
2028 }
2029
dw_hdmi_qp_bridge_detach(struct drm_bridge * bridge)2030 static void dw_hdmi_qp_bridge_detach(struct drm_bridge *bridge)
2031 {
2032 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2033
2034 mutex_lock(&hdmi->cec_notifier_mutex);
2035 cec_notifier_conn_unregister(hdmi->cec_notifier);
2036 hdmi->cec_notifier = NULL;
2037 mutex_unlock(&hdmi->cec_notifier_mutex);
2038 }
2039
2040 static enum drm_mode_status
dw_hdmi_qp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)2041 dw_hdmi_qp_bridge_mode_valid(struct drm_bridge *bridge,
2042 const struct drm_display_info *info,
2043 const struct drm_display_mode *mode)
2044 {
2045 return MODE_OK;
2046 }
2047
dw_hdmi_qp_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * orig_mode,const struct drm_display_mode * mode)2048 static void dw_hdmi_qp_bridge_mode_set(struct drm_bridge *bridge,
2049 const struct drm_display_mode *orig_mode,
2050 const struct drm_display_mode *mode)
2051 {
2052 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2053
2054 mutex_lock(&hdmi->mutex);
2055
2056 /* Store the display mode for plugin/DKMS poweron events */
2057 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2058 if (hdmi->plat_data->split_mode)
2059 hdmi->plat_data->convert_to_origin_mode(&hdmi->previous_mode);
2060
2061 mutex_unlock(&hdmi->mutex);
2062 }
2063
dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2064 static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge,
2065 struct drm_bridge_state *old_state)
2066 {
2067 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2068 void *data = hdmi->plat_data->phy_data;
2069
2070 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
2071 handle_plugged_change(hdmi, false);
2072 mutex_lock(&hdmi->mutex);
2073 hdmi->disabled = true;
2074 hdmi->curr_conn = NULL;
2075
2076 if (hdmi->dclk_en) {
2077 mutex_lock(&hdmi->audio_mutex);
2078 if (hdmi->plat_data->dclk_set)
2079 hdmi->plat_data->dclk_set(data, false);
2080 hdmi->dclk_en = false;
2081 mutex_unlock(&hdmi->audio_mutex);
2082 };
2083
2084 if (hdmi->phy.ops->disable)
2085 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2086 mutex_unlock(&hdmi->mutex);
2087 }
2088
dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2089 static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge,
2090 struct drm_bridge_state *old_state)
2091 {
2092 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2093 struct drm_atomic_state *state = old_state->base.state;
2094 struct drm_connector *connector;
2095 void *data = hdmi->plat_data->phy_data;
2096
2097 connector = drm_atomic_get_new_connector_for_encoder(state,
2098 bridge->encoder);
2099
2100 mutex_lock(&hdmi->mutex);
2101 hdmi->disabled = false;
2102 hdmi->curr_conn = connector;
2103 dw_hdmi_qp_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2104 mutex_unlock(&hdmi->mutex);
2105
2106 if (!hdmi->dclk_en) {
2107 mutex_lock(&hdmi->audio_mutex);
2108 if (hdmi->plat_data->dclk_set)
2109 hdmi->plat_data->dclk_set(data, true);
2110 hdmi->dclk_en = true;
2111 mutex_unlock(&hdmi->audio_mutex);
2112 }
2113
2114 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
2115 handle_plugged_change(hdmi, true);
2116 }
2117
2118 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2119 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2120 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2121 .atomic_reset = drm_atomic_helper_bridge_reset,
2122 .attach = dw_hdmi_qp_bridge_attach,
2123 .detach = dw_hdmi_qp_bridge_detach,
2124 .mode_set = dw_hdmi_qp_bridge_mode_set,
2125 .mode_valid = dw_hdmi_qp_bridge_mode_valid,
2126 .atomic_enable = dw_hdmi_qp_bridge_atomic_enable,
2127 .atomic_disable = dw_hdmi_qp_bridge_atomic_disable,
2128 };
2129
dw_hdmi_qp_set_cec_adap(struct dw_hdmi_qp * hdmi,struct cec_adapter * adap)2130 void dw_hdmi_qp_set_cec_adap(struct dw_hdmi_qp *hdmi, struct cec_adapter *adap)
2131 {
2132 hdmi->cec_adap = adap;
2133 }
2134 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_cec_adap);
2135
dw_hdmi_qp_main_hardirq(int irq,void * dev_id)2136 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id)
2137 {
2138 struct dw_hdmi_qp *hdmi = dev_id;
2139 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
2140 u32 stat;
2141
2142 stat = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS);
2143
2144 i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ |
2145 I2CM_NACK_RCVD_IRQ);
2146 hdmi->scdc_intr = stat & (SCDC_UPD_FLAGS_RD_IRQ |
2147 SCDC_UPD_FLAGS_CHG_IRQ |
2148 SCDC_UPD_FLAGS_CLR_IRQ |
2149 SCDC_RR_REPLY_STOP_IRQ |
2150 SCDC_NACK_RCVD_IRQ);
2151 hdmi->flt_intr = stat & (FLT_EXIT_TO_LTSP_IRQ |
2152 FLT_EXIT_TO_LTS4_IRQ |
2153 FLT_EXIT_TO_LTSL_IRQ);
2154
2155 dev_dbg(hdmi->dev, "i2c main unit irq:%#x\n", stat);
2156 if (i2c->stat) {
2157 hdmi_writel(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR);
2158 complete(&i2c->cmp);
2159 }
2160
2161 if (hdmi->flt_intr) {
2162 dev_dbg(hdmi->dev, "i2c flt irq:%#x\n", hdmi->flt_intr);
2163 hdmi_writel(hdmi, hdmi->flt_intr, MAINUNIT_1_INT_CLEAR);
2164 complete(&hdmi->flt_cmp);
2165 }
2166
2167 if (hdmi->scdc_intr) {
2168 u8 val;
2169
2170 dev_dbg(hdmi->dev, "i2c scdc irq:%#x\n", hdmi->scdc_intr);
2171 hdmi_writel(hdmi, hdmi->scdc_intr, MAINUNIT_1_INT_CLEAR);
2172 val = hdmi_readl(hdmi, SCDC_STATUS0);
2173
2174 /* frl start */
2175 if (val & BIT(4)) {
2176 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN |
2177 SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
2178 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ,
2179 MAINUNIT_1_INT_MASK_N);
2180 dev_info(hdmi->dev, "frl start\n");
2181 }
2182
2183 }
2184
2185 if (stat)
2186 return IRQ_HANDLED;
2187
2188 return IRQ_NONE;
2189 }
2190
dw_hdmi_qp_avp_hardirq(int irq,void * dev_id)2191 static irqreturn_t dw_hdmi_qp_avp_hardirq(int irq, void *dev_id)
2192 {
2193 struct dw_hdmi_qp *hdmi = dev_id;
2194 u32 stat;
2195
2196 stat = hdmi_readl(hdmi, AVP_1_INT_STATUS);
2197 if (stat) {
2198 dev_dbg(hdmi->dev, "HDCP irq %#x\n", stat);
2199 stat &= ~stat;
2200 hdmi_writel(hdmi, stat, AVP_1_INT_MASK_N);
2201 return IRQ_WAKE_THREAD;
2202 }
2203
2204 return IRQ_NONE;
2205 }
2206
dw_hdmi_qp_earc_hardirq(int irq,void * dev_id)2207 static irqreturn_t dw_hdmi_qp_earc_hardirq(int irq, void *dev_id)
2208 {
2209 struct dw_hdmi_qp *hdmi = dev_id;
2210 u32 stat;
2211
2212 stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS);
2213 if (stat) {
2214 dev_dbg(hdmi->dev, "earc irq %#x\n", stat);
2215 stat &= ~stat;
2216 hdmi_writel(hdmi, stat, EARCRX_0_INT_MASK_N);
2217 return IRQ_WAKE_THREAD;
2218 }
2219
2220 return IRQ_NONE;
2221 }
2222
dw_hdmi_qp_avp_irq(int irq,void * dev_id)2223 static irqreturn_t dw_hdmi_qp_avp_irq(int irq, void *dev_id)
2224 {
2225 struct dw_hdmi_qp *hdmi = dev_id;
2226 u32 stat;
2227
2228 stat = hdmi_readl(hdmi, AVP_1_INT_STATUS);
2229
2230 if (!stat)
2231 return IRQ_NONE;
2232
2233 hdmi_writel(hdmi, stat, AVP_1_INT_CLEAR);
2234
2235 return IRQ_HANDLED;
2236 }
2237
dw_hdmi_qp_earc_irq(int irq,void * dev_id)2238 static irqreturn_t dw_hdmi_qp_earc_irq(int irq, void *dev_id)
2239 {
2240 struct dw_hdmi_qp *hdmi = dev_id;
2241 u32 stat;
2242
2243 stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS);
2244
2245 if (!stat)
2246 return IRQ_NONE;
2247
2248 hdmi_writel(hdmi, stat, EARCRX_0_INT_CLEAR);
2249
2250 hdmi->earc_intr = stat;
2251 complete(&hdmi->earc_cmp);
2252
2253 return IRQ_HANDLED;
2254 }
2255
dw_hdmi_detect_phy(struct dw_hdmi_qp * hdmi)2256 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi)
2257 {
2258 u8 phy_type;
2259
2260 phy_type = hdmi->plat_data->phy_force_vendor ?
2261 DW_HDMI_PHY_VENDOR_PHY : 0;
2262
2263 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2264 /* Vendor PHYs require support from the glue layer. */
2265 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) {
2266 dev_err(hdmi->dev,
2267 "Vendor HDMI PHY not supported by glue layer\n");
2268 return -ENODEV;
2269 }
2270
2271 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops;
2272 hdmi->phy.data = hdmi->plat_data->phy_data;
2273 hdmi->phy.name = hdmi->plat_data->phy_name;
2274 }
2275
2276 return 0;
2277 }
2278
dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp * hdmi,bool plug_in,bool change)2279 void dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp *hdmi, bool plug_in, bool change)
2280 {
2281 enum drm_connector_status status = plug_in ?
2282 connector_status_connected : connector_status_disconnected;
2283
2284 if (!plug_in)
2285 cec_notifier_set_phys_addr(hdmi->cec_notifier,
2286 CEC_PHYS_ADDR_INVALID);
2287
2288 if (hdmi->bridge.dev) {
2289 if (change && hdmi->cec_adap && hdmi->cec_adap->devnode.registered)
2290 cec_queue_pin_hpd_event(hdmi->cec_adap, plug_in, ktime_get());
2291 drm_bridge_hpd_notify(&hdmi->bridge, status);
2292 }
2293 }
2294 EXPORT_SYMBOL_GPL(dw_hdmi_qp_cec_set_hpd);
2295
dw_hdmi_qp_cec_enable(struct dw_hdmi_qp * hdmi)2296 static void dw_hdmi_qp_cec_enable(struct dw_hdmi_qp *hdmi)
2297 {
2298 mutex_lock(&hdmi->mutex);
2299 hdmi_modb(hdmi, 0, CEC_SWDISABLE, GLOBAL_SWDISABLE);
2300 mutex_unlock(&hdmi->mutex);
2301 }
2302
dw_hdmi_qp_cec_disable(struct dw_hdmi_qp * hdmi)2303 static void dw_hdmi_qp_cec_disable(struct dw_hdmi_qp *hdmi)
2304 {
2305 mutex_lock(&hdmi->mutex);
2306 hdmi_modb(hdmi, CEC_SWDISABLE, CEC_SWDISABLE, GLOBAL_SWDISABLE);
2307 mutex_unlock(&hdmi->mutex);
2308 }
2309
2310 static const struct dw_hdmi_qp_cec_ops dw_hdmi_qp_cec_ops = {
2311 .enable = dw_hdmi_qp_cec_enable,
2312 .disable = dw_hdmi_qp_cec_disable,
2313 .write = hdmi_writel,
2314 .read = hdmi_readl,
2315 };
2316
2317 static const struct regmap_config hdmi_regmap_config = {
2318 .reg_bits = 32,
2319 .val_bits = 32,
2320 .reg_stride = 4,
2321 .max_register = EARCRX_1_INT_FORCE,
2322 };
2323
2324 static struct dw_hdmi_qp *
__dw_hdmi_probe(struct platform_device * pdev,const struct dw_hdmi_plat_data * plat_data)2325 __dw_hdmi_probe(struct platform_device *pdev,
2326 const struct dw_hdmi_plat_data *plat_data)
2327 {
2328 struct device *dev = &pdev->dev;
2329 struct device_node *np = dev->of_node;
2330 struct device_node *ddc_node;
2331 struct dw_hdmi_qp *hdmi;
2332 struct dw_hdmi_qp_i2s_audio_data audio;
2333 struct platform_device_info pdevinfo;
2334 struct dw_hdmi_qp_cec_data cec;
2335 struct resource *iores = NULL;
2336 int irq;
2337 int ret;
2338
2339 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2340 if (!hdmi)
2341 return ERR_PTR(-ENOMEM);
2342
2343 hdmi->connector.stereo_allowed = 1;
2344 hdmi->plat_data = plat_data;
2345 hdmi->dev = dev;
2346 hdmi->sample_rate = 48000;
2347 hdmi->disabled = true;
2348
2349 mutex_init(&hdmi->mutex);
2350 mutex_init(&hdmi->audio_mutex);
2351 mutex_init(&hdmi->cec_notifier_mutex);
2352
2353 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2354 if (ddc_node) {
2355 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2356 of_node_put(ddc_node);
2357 if (!hdmi->ddc) {
2358 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2359 return ERR_PTR(-EPROBE_DEFER);
2360 }
2361
2362 } else {
2363 dev_dbg(hdmi->dev, "no ddc property found\n");
2364 }
2365
2366 if (!plat_data->regm) {
2367 const struct regmap_config *reg_config;
2368
2369 reg_config = &hdmi_regmap_config;
2370
2371 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2372 hdmi->regs = devm_ioremap_resource(dev, iores);
2373 if (IS_ERR(hdmi->regs)) {
2374 ret = PTR_ERR(hdmi->regs);
2375 goto err_res;
2376 }
2377
2378 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2379 if (IS_ERR(hdmi->regm)) {
2380 dev_err(dev, "Failed to configure regmap\n");
2381 ret = PTR_ERR(hdmi->regm);
2382 goto err_res;
2383 }
2384 } else {
2385 hdmi->regm = plat_data->regm;
2386 }
2387
2388 ret = dw_hdmi_detect_phy(hdmi);
2389 if (ret < 0)
2390 goto err_res;
2391
2392 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
2393 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
2394 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0);
2395 if ((hdmi_readl(hdmi, CMU_STATUS) & DISPLAY_CLK_MONITOR) == DISPLAY_CLK_LOCKED)
2396 hdmi->initialized = true;
2397
2398 irq = platform_get_irq(pdev, 0);
2399 if (irq < 0) {
2400 ret = irq;
2401 goto err_res;
2402 }
2403
2404 hdmi->avp_irq = irq;
2405 ret = devm_request_threaded_irq(dev, hdmi->avp_irq,
2406 dw_hdmi_qp_avp_hardirq,
2407 dw_hdmi_qp_avp_irq, IRQF_SHARED,
2408 dev_name(dev), hdmi);
2409 if (ret)
2410 goto err_res;
2411
2412 irq = platform_get_irq(pdev, 1);
2413 if (irq < 0) {
2414 ret = irq;
2415 goto err_res;
2416 }
2417
2418 cec.irq = irq;
2419
2420 irq = platform_get_irq(pdev, 2);
2421 if (irq < 0) {
2422 ret = irq;
2423 goto err_res;
2424 }
2425
2426 hdmi->earc_irq = irq;
2427 ret = devm_request_threaded_irq(dev, hdmi->earc_irq,
2428 dw_hdmi_qp_earc_hardirq,
2429 dw_hdmi_qp_earc_irq, IRQF_SHARED,
2430 dev_name(dev), hdmi);
2431 if (ret)
2432 goto err_res;
2433
2434 irq = platform_get_irq(pdev, 3);
2435 if (irq < 0) {
2436 ret = irq;
2437 goto err_res;
2438 }
2439
2440 hdmi->main_irq = irq;
2441 ret = devm_request_threaded_irq(dev, hdmi->main_irq,
2442 dw_hdmi_qp_main_hardirq, NULL,
2443 IRQF_SHARED, dev_name(dev), hdmi);
2444 if (ret)
2445 goto err_res;
2446
2447 hdmi_init_clk_regenerator(hdmi);
2448
2449 /* If DDC bus is not specified, try to register HDMI I2C bus */
2450 if (!hdmi->ddc) {
2451 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2452 if (IS_ERR(hdmi->ddc))
2453 hdmi->ddc = NULL;
2454 /*
2455 * Read high and low time from device tree. If not available use
2456 * the default timing scl clock rate is about 99.6KHz.
2457 */
2458 if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns",
2459 &hdmi->i2c->scl_high_ns))
2460 hdmi->i2c->scl_high_ns = 4708;
2461 if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns",
2462 &hdmi->i2c->scl_low_ns))
2463 hdmi->i2c->scl_low_ns = 4916;
2464 }
2465
2466 hdmi->bridge.driver_private = hdmi;
2467 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2468 #ifdef CONFIG_OF
2469 hdmi->bridge.of_node = pdev->dev.of_node;
2470 #endif
2471
2472 if (hdmi->phy.ops->setup_hpd)
2473 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2474
2475 hdmi->connector.ycbcr_420_allowed = hdmi->plat_data->ycbcr_420_allowed;
2476
2477 audio.hdmi = hdmi;
2478 audio.eld = hdmi->connector.eld;
2479 audio.write = hdmi_writel;
2480 audio.read = hdmi_readl;
2481 audio.mod = hdmi_modb;
2482 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2483 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2484
2485 memset(&pdevinfo, 0, sizeof(pdevinfo));
2486 pdevinfo.parent = dev;
2487 pdevinfo.id = PLATFORM_DEVID_AUTO;
2488 pdevinfo.name = "dw-hdmi-qp-i2s-audio";
2489 pdevinfo.data = &audio;
2490 pdevinfo.size_data = sizeof(audio);
2491 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2492 hdmi->audio = platform_device_register_full(&pdevinfo);
2493
2494 hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable);
2495 if (IS_ERR(hdmi->extcon)) {
2496 dev_err(hdmi->dev, "allocate extcon failed\n");
2497 ret = PTR_ERR(hdmi->extcon);
2498 goto err_res;
2499 }
2500
2501 ret = devm_extcon_dev_register(hdmi->dev, hdmi->extcon);
2502 if (ret) {
2503 dev_err(hdmi->dev, "failed to register extcon: %d\n", ret);
2504 goto err_res;
2505 }
2506
2507 ret = extcon_set_property_capability(hdmi->extcon, EXTCON_DISP_HDMI,
2508 EXTCON_PROP_DISP_HPD);
2509 if (ret) {
2510 dev_err(hdmi->dev,
2511 "failed to set USB property capability: %d\n", ret);
2512 goto err_res;
2513 }
2514
2515 cec.hdmi = hdmi;
2516 cec.ops = &dw_hdmi_qp_cec_ops;
2517 pdevinfo.name = "dw-hdmi-qp-cec";
2518 pdevinfo.data = &cec;
2519 pdevinfo.size_data = sizeof(cec);
2520 pdevinfo.dma_mask = 0;
2521 hdmi->cec = platform_device_register_full(&pdevinfo);
2522
2523 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2524 if (hdmi->i2c)
2525 dw_hdmi_i2c_init(hdmi);
2526
2527 init_completion(&hdmi->flt_cmp);
2528 init_completion(&hdmi->earc_cmp);
2529
2530 if (of_property_read_bool(np, "scramble-low-rates"))
2531 hdmi->scramble_low_rates = true;
2532
2533 return hdmi;
2534
2535 err_res:
2536 if (hdmi->i2c)
2537 i2c_del_adapter(&hdmi->i2c->adap);
2538 else
2539 i2c_put_adapter(hdmi->ddc);
2540
2541 return ERR_PTR(ret);
2542 }
2543
__dw_hdmi_remove(struct dw_hdmi_qp * hdmi)2544 static void __dw_hdmi_remove(struct dw_hdmi_qp *hdmi)
2545 {
2546 if (hdmi->avp_irq)
2547 disable_irq(hdmi->avp_irq);
2548
2549 if (hdmi->main_irq)
2550 disable_irq(hdmi->main_irq);
2551
2552 if (hdmi->earc_irq)
2553 disable_irq(hdmi->earc_irq);
2554
2555 if (!hdmi->plat_data->first_screen) {
2556 dw_hdmi_destroy_properties(hdmi);
2557 hdmi->connector.funcs->destroy(&hdmi->connector);
2558 }
2559
2560 if (hdmi->audio && !IS_ERR(hdmi->audio))
2561 platform_device_unregister(hdmi->audio);
2562
2563 if (hdmi->bridge.encoder && !hdmi->plat_data->first_screen)
2564 hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder);
2565 if (!IS_ERR(hdmi->cec))
2566 platform_device_unregister(hdmi->cec);
2567 if (hdmi->i2c)
2568 i2c_del_adapter(&hdmi->i2c->adap);
2569 else
2570 i2c_put_adapter(hdmi->ddc);
2571 }
2572
2573 /* -----------------------------------------------------------------------------
2574 * Bind/unbind API, used from platforms based on the component framework.
2575 */
dw_hdmi_qp_bind(struct platform_device * pdev,struct drm_encoder * encoder,struct dw_hdmi_plat_data * plat_data)2576 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
2577 struct drm_encoder *encoder,
2578 struct dw_hdmi_plat_data *plat_data)
2579 {
2580 struct dw_hdmi_qp *hdmi;
2581 int ret;
2582
2583 hdmi = __dw_hdmi_probe(pdev, plat_data);
2584 if (IS_ERR(hdmi))
2585 return hdmi;
2586
2587 if (!plat_data->first_screen) {
2588 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
2589 if (ret) {
2590 __dw_hdmi_remove(hdmi);
2591 dev_err(hdmi->dev, "Failed to initialize bridge with drm\n");
2592 return ERR_PTR(ret);
2593 }
2594
2595 plat_data->connector = &hdmi->connector;
2596 }
2597
2598 if (plat_data->split_mode && !hdmi->plat_data->first_screen) {
2599 struct dw_hdmi_qp *secondary = NULL;
2600
2601 if (hdmi->plat_data->left)
2602 secondary = hdmi->plat_data->left;
2603 else if (hdmi->plat_data->right)
2604 secondary = hdmi->plat_data->right;
2605
2606 if (!secondary)
2607 return ERR_PTR(-ENOMEM);
2608 ret = drm_bridge_attach(encoder, &secondary->bridge, &hdmi->bridge,
2609 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
2610 if (ret)
2611 return ERR_PTR(ret);
2612 }
2613
2614 return hdmi;
2615 }
2616 EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind);
2617
dw_hdmi_qp_unbind(struct dw_hdmi_qp * hdmi)2618 void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi)
2619 {
2620 __dw_hdmi_remove(hdmi);
2621 }
2622 EXPORT_SYMBOL_GPL(dw_hdmi_qp_unbind);
2623
dw_hdmi_qp_suspend(struct device * dev,struct dw_hdmi_qp * hdmi)2624 void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi)
2625 {
2626 if (!hdmi) {
2627 dev_warn(dev, "Hdmi has not been initialized\n");
2628 return;
2629 }
2630
2631 mutex_lock(&hdmi->mutex);
2632
2633 /*
2634 * When system shutdown, hdmi should be disabled.
2635 * When system suspend, dw_hdmi_qp_bridge_disable will disable hdmi first.
2636 * To prevent duplicate operation, we should determine whether hdmi
2637 * has been disabled.
2638 */
2639 if (!hdmi->disabled)
2640 hdmi->disabled = true;
2641 mutex_unlock(&hdmi->mutex);
2642
2643 if (hdmi->avp_irq)
2644 disable_irq(hdmi->avp_irq);
2645
2646 if (hdmi->main_irq)
2647 disable_irq(hdmi->main_irq);
2648
2649 if (hdmi->earc_irq)
2650 disable_irq(hdmi->earc_irq);
2651
2652 pinctrl_pm_select_sleep_state(dev);
2653 }
2654 EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend);
2655
dw_hdmi_qp_resume(struct device * dev,struct dw_hdmi_qp * hdmi)2656 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi)
2657 {
2658 if (!hdmi) {
2659 dev_warn(dev, "Hdmi has not been initialized\n");
2660 return;
2661 }
2662
2663 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
2664 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
2665 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0);
2666
2667 pinctrl_pm_select_default_state(dev);
2668
2669 hdmi->cec_adap->ops->adap_enable(hdmi->cec_adap, true);
2670
2671 mutex_lock(&hdmi->mutex);
2672 if (hdmi->i2c)
2673 dw_hdmi_i2c_init(hdmi);
2674 if (hdmi->avp_irq)
2675 enable_irq(hdmi->avp_irq);
2676
2677 if (hdmi->main_irq)
2678 enable_irq(hdmi->main_irq);
2679
2680 if (hdmi->earc_irq)
2681 enable_irq(hdmi->earc_irq);
2682
2683 mutex_unlock(&hdmi->mutex);
2684 }
2685 EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume);
2686
2687 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
2688 MODULE_DESCRIPTION("DW HDMI QP transmitter driver");
2689 MODULE_LICENSE("GPL");
2690 MODULE_ALIAS("platform:dw-hdmi-qp");
2691