1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 */
6
7 #include <linux/device.h>
8 #include <linux/delay.h>
9 #include <linux/phy/phy.h>
10
11 #include "cdn-dp-core.h"
12 #include "cdn-dp-reg.h"
13
cdn_dp_set_signal_levels(struct cdn_dp_device * dp)14 static void cdn_dp_set_signal_levels(struct cdn_dp_device *dp)
15 {
16 struct cdn_dp_port *port = dp->port[dp->active_port];
17 int rate = drm_dp_bw_code_to_link_rate(dp->link.rate);
18 u8 swing = (dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
19 DP_TRAIN_VOLTAGE_SWING_SHIFT;
20 u8 pre_emphasis = (dp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
21 >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
22
23 tcphy_dp_set_phy_config(port->phy, rate, dp->link.num_lanes,
24 swing, pre_emphasis);
25 }
26
cdn_dp_set_pattern(struct cdn_dp_device * dp,uint8_t dp_train_pat)27 static int cdn_dp_set_pattern(struct cdn_dp_device *dp, uint8_t dp_train_pat)
28 {
29 u32 phy_config, global_config;
30 int ret;
31 uint8_t pattern = dp_train_pat & DP_TRAINING_PATTERN_MASK;
32
33 global_config = NUM_LANES(dp->link.num_lanes - 1) | SST_MODE |
34 GLOBAL_EN | RG_EN | ENC_RST_DIS | WR_VHSYNC_FALL;
35
36 phy_config = DP_TX_PHY_ENCODER_BYPASS(0) |
37 DP_TX_PHY_SKEW_BYPASS(0) |
38 DP_TX_PHY_DISPARITY_RST(0) |
39 DP_TX_PHY_LANE0_SKEW(0) |
40 DP_TX_PHY_LANE1_SKEW(1) |
41 DP_TX_PHY_LANE2_SKEW(2) |
42 DP_TX_PHY_LANE3_SKEW(3) |
43 DP_TX_PHY_10BIT_ENABLE(0);
44
45 if (pattern != DP_TRAINING_PATTERN_DISABLE) {
46 global_config |= NO_VIDEO;
47 phy_config |= DP_TX_PHY_TRAINING_ENABLE(1) |
48 DP_TX_PHY_SCRAMBLER_BYPASS(1) |
49 DP_TX_PHY_TRAINING_PATTERN(pattern);
50 }
51
52 ret = cdn_dp_reg_write(dp, DP_FRAMER_GLOBAL_CONFIG, global_config);
53 if (ret) {
54 DRM_ERROR("fail to set DP_FRAMER_GLOBAL_CONFIG, error: %d\n",
55 ret);
56 return ret;
57 }
58
59 ret = cdn_dp_reg_write(dp, DP_TX_PHY_CONFIG_REG, phy_config);
60 if (ret) {
61 DRM_ERROR("fail to set DP_TX_PHY_CONFIG_REG, error: %d\n",
62 ret);
63 return ret;
64 }
65
66 ret = cdn_dp_reg_write(dp, DPTX_LANE_EN, BIT(dp->link.num_lanes) - 1);
67 if (ret) {
68 DRM_ERROR("fail to set DPTX_LANE_EN, error: %d\n", ret);
69 return ret;
70 }
71
72 if (drm_dp_enhanced_frame_cap(dp->dpcd) ||
73 /*
74 * A setting of 1 indicates that this is an eDP device that uses
75 * only Enhanced Framing, independently of the setting by the
76 * source of ENHANCED_FRAME_EN
77 */
78 dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_FRAMING_CHANGE_CAP)
79 ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 1);
80 else
81 ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 0);
82 if (ret)
83 DRM_ERROR("failed to set DPTX_ENHNCD, error: %x\n", ret);
84
85 return ret;
86 }
87
cdn_dp_pre_emphasis_max(u8 voltage_swing)88 static u8 cdn_dp_pre_emphasis_max(u8 voltage_swing)
89 {
90 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
91 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
92 return DP_TRAIN_PRE_EMPH_LEVEL_3;
93 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
94 return DP_TRAIN_PRE_EMPH_LEVEL_2;
95 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
96 return DP_TRAIN_PRE_EMPH_LEVEL_1;
97 default:
98 return DP_TRAIN_PRE_EMPH_LEVEL_0;
99 }
100 }
101
cdn_dp_get_adjust_train(struct cdn_dp_device * dp,uint8_t link_status[DP_LINK_STATUS_SIZE])102 static void cdn_dp_get_adjust_train(struct cdn_dp_device *dp,
103 uint8_t link_status[DP_LINK_STATUS_SIZE])
104 {
105 int i;
106 uint8_t v = 0, p = 0;
107 uint8_t preemph_max;
108
109 for (i = 0; i < dp->link.num_lanes; i++) {
110 v = max(v, drm_dp_get_adjust_request_voltage(link_status, i));
111 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status,
112 i));
113 }
114
115 if (v >= VOLTAGE_LEVEL_2)
116 v = VOLTAGE_LEVEL_2 | DP_TRAIN_MAX_SWING_REACHED;
117
118 preemph_max = cdn_dp_pre_emphasis_max(v);
119 if (p >= preemph_max)
120 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
121
122 for (i = 0; i < dp->link.num_lanes; i++)
123 dp->train_set[i] = v | p;
124 }
125
126 /*
127 * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
128 * or 1.2 devices that support it, Training Pattern 2 otherwise.
129 */
cdn_dp_select_chaneq_pattern(struct cdn_dp_device * dp)130 static u32 cdn_dp_select_chaneq_pattern(struct cdn_dp_device *dp)
131 {
132 u32 training_pattern = DP_TRAINING_PATTERN_2;
133
134 /*
135 * cdn dp support HBR2 also support TPS3. TPS3 support is also mandatory
136 * for downstream devices that support HBR2. However, not all sinks
137 * follow the spec.
138 */
139 if (drm_dp_tps3_supported(dp->dpcd))
140 training_pattern = DP_TRAINING_PATTERN_3;
141 else
142 DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
143
144 return training_pattern;
145 }
146
147
cdn_dp_link_max_vswing_reached(struct cdn_dp_device * dp)148 static bool cdn_dp_link_max_vswing_reached(struct cdn_dp_device *dp)
149 {
150 int lane;
151
152 for (lane = 0; lane < dp->link.num_lanes; lane++)
153 if ((dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0)
154 return false;
155
156 return true;
157 }
158
cdn_dp_update_link_train(struct cdn_dp_device * dp)159 static int cdn_dp_update_link_train(struct cdn_dp_device *dp)
160 {
161 int ret;
162
163 cdn_dp_set_signal_levels(dp);
164
165 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
166 dp->train_set, dp->link.num_lanes);
167 if (ret != dp->link.num_lanes)
168 return -EINVAL;
169
170 return 0;
171 }
172
cdn_dp_set_link_train(struct cdn_dp_device * dp,uint8_t dp_train_pat)173 static int cdn_dp_set_link_train(struct cdn_dp_device *dp,
174 uint8_t dp_train_pat)
175 {
176 uint8_t buf[sizeof(dp->train_set) + 1];
177 int ret, len;
178
179 buf[0] = dp_train_pat;
180 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
181 DP_TRAINING_PATTERN_DISABLE) {
182 /* don't write DP_TRAINING_LANEx_SET on disable */
183 len = 1;
184 } else {
185 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
186 memcpy(buf + 1, dp->train_set, dp->link.num_lanes);
187 len = dp->link.num_lanes + 1;
188 }
189
190 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET,
191 buf, len);
192 if (ret != len)
193 return -EINVAL;
194
195 return 0;
196 }
197
cdn_dp_reset_link_train(struct cdn_dp_device * dp,uint8_t dp_train_pat)198 static int cdn_dp_reset_link_train(struct cdn_dp_device *dp,
199 uint8_t dp_train_pat)
200 {
201 int ret;
202
203 memset(dp->train_set, 0, sizeof(dp->train_set));
204
205 cdn_dp_set_signal_levels(dp);
206
207 ret = cdn_dp_set_pattern(dp, dp_train_pat);
208 if (ret)
209 return ret;
210
211 return cdn_dp_set_link_train(dp, dp_train_pat);
212 }
213
214 /* Enable corresponding port and start training pattern 1 */
cdn_dp_link_training_clock_recovery(struct cdn_dp_device * dp)215 static int cdn_dp_link_training_clock_recovery(struct cdn_dp_device *dp)
216 {
217 u8 voltage;
218 u8 link_status[DP_LINK_STATUS_SIZE];
219 u32 voltage_tries, max_vswing_tries;
220 int ret;
221
222 /* clock recovery */
223 ret = cdn_dp_reset_link_train(dp, DP_TRAINING_PATTERN_1 |
224 DP_LINK_SCRAMBLING_DISABLE);
225 if (ret) {
226 DRM_ERROR("failed to start link train\n");
227 return ret;
228 }
229
230 voltage_tries = 1;
231 max_vswing_tries = 0;
232 for (;;) {
233 drm_dp_link_train_clock_recovery_delay(dp->dpcd);
234 if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) !=
235 DP_LINK_STATUS_SIZE) {
236 DRM_ERROR("failed to get link status\n");
237 return -EINVAL;
238 }
239
240 if (drm_dp_clock_recovery_ok(link_status, dp->link.num_lanes)) {
241 DRM_DEBUG_KMS("clock recovery OK\n");
242 return 0;
243 }
244
245 if (voltage_tries >= 5) {
246 DRM_DEBUG_KMS("Same voltage tried 5 times\n");
247 return -EINVAL;
248 }
249
250 if (max_vswing_tries >= 1) {
251 DRM_DEBUG_KMS("Max Voltage Swing reached\n");
252 return -EINVAL;
253 }
254
255 voltage = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
256
257 /* Update training set as requested by target */
258 cdn_dp_get_adjust_train(dp, link_status);
259 if (cdn_dp_update_link_train(dp)) {
260 DRM_ERROR("failed to update link training\n");
261 return -EINVAL;
262 }
263
264 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
265 voltage)
266 ++voltage_tries;
267 else
268 voltage_tries = 1;
269
270 if (cdn_dp_link_max_vswing_reached(dp))
271 ++max_vswing_tries;
272 }
273 }
274
cdn_dp_link_training_channel_equalization(struct cdn_dp_device * dp)275 static int cdn_dp_link_training_channel_equalization(struct cdn_dp_device *dp)
276 {
277 int tries, ret;
278 u32 training_pattern;
279 uint8_t link_status[DP_LINK_STATUS_SIZE];
280
281 training_pattern = cdn_dp_select_chaneq_pattern(dp);
282 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
283
284 ret = cdn_dp_set_pattern(dp, training_pattern);
285 if (ret)
286 return ret;
287
288 ret = cdn_dp_set_link_train(dp, training_pattern);
289 if (ret) {
290 DRM_ERROR("failed to start channel equalization\n");
291 return ret;
292 }
293
294 for (tries = 0; tries < 5; tries++) {
295 drm_dp_link_train_channel_eq_delay(dp->dpcd);
296 if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) !=
297 DP_LINK_STATUS_SIZE) {
298 DRM_ERROR("failed to get link status\n");
299 break;
300 }
301
302 /* Make sure clock is still ok */
303 if (!drm_dp_clock_recovery_ok(link_status,
304 dp->link.num_lanes)) {
305 DRM_DEBUG_KMS("Clock recovery check failed\n");
306 break;
307 }
308
309 if (drm_dp_channel_eq_ok(link_status, dp->link.num_lanes)) {
310 DRM_DEBUG_KMS("Channel EQ done\n");
311 return 0;
312 }
313
314 /* Update training set as requested by target */
315 cdn_dp_get_adjust_train(dp, link_status);
316 if (cdn_dp_update_link_train(dp)) {
317 DRM_ERROR("failed to update link training\n");
318 break;
319 }
320 }
321
322 /* Try 5 times, else fail and try at lower BW */
323 if (tries == 5)
324 DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
325
326 return -EINVAL;
327 }
328
cdn_dp_stop_link_train(struct cdn_dp_device * dp)329 static int cdn_dp_stop_link_train(struct cdn_dp_device *dp)
330 {
331 int ret = cdn_dp_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
332
333 if (ret)
334 return ret;
335
336 return cdn_dp_set_link_train(dp, DP_TRAINING_PATTERN_DISABLE);
337 }
338
cdn_dp_get_lower_link_rate(struct cdn_dp_device * dp)339 static int cdn_dp_get_lower_link_rate(struct cdn_dp_device *dp)
340 {
341 switch (dp->link.rate) {
342 case DP_LINK_BW_1_62:
343 return -EINVAL;
344 case DP_LINK_BW_2_7:
345 dp->link.rate = DP_LINK_BW_1_62;
346 break;
347 case DP_LINK_BW_5_4:
348 dp->link.rate = DP_LINK_BW_2_7;
349 break;
350 default:
351 dp->link.rate = DP_LINK_BW_5_4;
352 break;
353 }
354
355 return 0;
356 }
357
cdn_dp_software_train_link(struct cdn_dp_device * dp)358 int cdn_dp_software_train_link(struct cdn_dp_device *dp)
359 {
360 struct cdn_dp_port *port = dp->port[dp->active_port];
361 int ret, stop_err;
362 u8 link_config[2];
363 u32 rate, sink_max, source_max;
364 bool ssc_on;
365
366 ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd,
367 sizeof(dp->dpcd));
368 if (ret < 0) {
369 DRM_DEV_ERROR(dp->dev, "Failed to get caps %d\n", ret);
370 return ret;
371 }
372
373 source_max = dp->lanes;
374 sink_max = drm_dp_max_lane_count(dp->dpcd);
375 dp->link.num_lanes = min(source_max, sink_max);
376
377 source_max = drm_dp_bw_code_to_link_rate(CDN_DP_MAX_LINK_RATE);
378 sink_max = drm_dp_max_link_rate(dp->dpcd);
379 rate = min(source_max, sink_max);
380 dp->link.rate = drm_dp_link_rate_to_bw_code(rate);
381
382 ssc_on = !!(dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
383 link_config[0] = ssc_on ? DP_SPREAD_AMP_0_5 : 0;
384 link_config[1] = 0;
385 if (dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & 0x01)
386 link_config[1] = DP_SET_ANSI_8B10B;
387 drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
388
389 while (true) {
390 ret = tcphy_dp_set_link_rate(port->phy,
391 drm_dp_bw_code_to_link_rate(dp->link.rate),
392 ssc_on);
393 if (ret) {
394 DRM_ERROR("failed to set link rate: %d\n", ret);
395 return ret;
396 }
397
398 ret = tcphy_dp_set_lane_count(port->phy, dp->link.num_lanes);
399 if (ret) {
400 DRM_ERROR("failed to set lane count: %d\n", ret);
401 return ret;
402 }
403
404 /* Write the link configuration data */
405 link_config[0] = dp->link.rate;
406 link_config[1] = dp->link.num_lanes;
407 if (drm_dp_enhanced_frame_cap(dp->dpcd))
408 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
409 drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, link_config, 2);
410
411 ret = cdn_dp_link_training_clock_recovery(dp);
412 if (ret) {
413 if (!cdn_dp_get_lower_link_rate(dp))
414 continue;
415
416 DRM_ERROR("training clock recovery failed: %d\n", ret);
417 break;
418 }
419
420 ret = cdn_dp_link_training_channel_equalization(dp);
421 if (ret) {
422 if (!cdn_dp_get_lower_link_rate(dp))
423 continue;
424
425 DRM_ERROR("training channel eq failed: %d\n", ret);
426 break;
427 }
428
429 break;
430 }
431
432 stop_err = cdn_dp_stop_link_train(dp);
433 if (stop_err) {
434 DRM_ERROR("stop training fail, error: %d\n", stop_err);
435 return stop_err;
436 }
437
438 return ret;
439 }
440