1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip CIF Driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 */
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_gpio.h>
13 #include <linux/of_graph.h>
14 #include <linux/of_platform.h>
15 #include <linux/of_reserved_mem.h>
16 #include <linux/reset.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/regmap.h>
20 #include <media/videobuf2-dma-contig.h>
21 #include <media/videobuf2-dma-sg.h>
22 #include <media/v4l2-fwnode.h>
23 #include <linux/iommu.h>
24 #include <dt-bindings/soc/rockchip-system-status.h>
25 #include <soc/rockchip/rockchip-system-status.h>
26 #include <linux/io.h>
27 #include <linux/mfd/syscon.h>
28 #include <soc/rockchip/rockchip_iommu.h>
29 #include "dev.h"
30 #include "common.h"
31
32 static const struct cif_reg px30_cif_regs[] = {
33 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
34 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
35 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
36 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
37 [CIF_REG_DVP_LINE_NUM_ADDR] = CIF_REG(CIF_LINE_NUM_ADDR),
38 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
39 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
40 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
41 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
42 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
43 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
44 [CIF_REG_DVP_SCM_ADDR_Y] = CIF_REG(CIF_SCM_ADDR_Y),
45 [CIF_REG_DVP_SCM_ADDR_U] = CIF_REG(CIF_SCM_ADDR_U),
46 [CIF_REG_DVP_SCM_ADDR_V] = CIF_REG(CIF_SCM_ADDR_V),
47 [CIF_REG_DVP_WB_UP_FILTER] = CIF_REG(CIF_WB_UP_FILTER),
48 [CIF_REG_DVP_WB_LOW_FILTER] = CIF_REG(CIF_WB_LOW_FILTER),
49 [CIF_REG_DVP_WBC_CNT] = CIF_REG(CIF_WBC_CNT),
50 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
51 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
52 [CIF_REG_DVP_SCL_DST] = CIF_REG(CIF_SCL_DST),
53 [CIF_REG_DVP_SCL_FCT] = CIF_REG(CIF_SCL_FCT),
54 [CIF_REG_DVP_SCL_VALID_NUM] = CIF_REG(CIF_SCL_VALID_NUM),
55 [CIF_REG_DVP_LINE_LOOP_CTRL] = CIF_REG(CIF_LINE_LOOP_CTR),
56 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
57 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
58 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
59 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
60 };
61
62 static const char * const px30_cif_clks[] = {
63 "aclk_cif",
64 "hclk_cif",
65 "pclk_cif",
66 "cif_out",
67 };
68
69 static const char * const px30_cif_rsts[] = {
70 "rst_cif_a",
71 "rst_cif_h",
72 "rst_cif_pclkin",
73 };
74
75 static const struct cif_reg rk1808_cif_regs[] = {
76 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
77 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
78 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
79 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
80 [CIF_REG_DVP_DMA_IDLE_REQ] = CIF_REG(CIF_DMA_IDLE_REQ),
81 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
82 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
83 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
84 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
85 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
86 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
87 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(CIF_LINE_INT_NUM),
88 [CIF_REG_DVP_LINE_CNT] = CIF_REG(CIF_LINE_CNT),
89 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
90 [CIF_REG_DVP_PATH_SEL] = CIF_REG(CIF_PATH_SEL),
91 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
92 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
93 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
94 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
95 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
96 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CIF_CSI_ID0_CTRL0),
97 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CIF_CSI_ID0_CTRL1),
98 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CIF_CSI_ID1_CTRL0),
99 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CIF_CSI_ID1_CTRL1),
100 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CIF_CSI_ID2_CTRL0),
101 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CIF_CSI_ID2_CTRL1),
102 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CIF_CSI_ID3_CTRL0),
103 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CIF_CSI_ID3_CTRL1),
104 [CIF_REG_MIPI_WATER_LINE] = CIF_REG(CIF_CSI_WATER_LINE),
105 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID0),
106 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID0),
107 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID0),
108 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID0),
109 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID0),
110 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID0),
111 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID0),
112 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID0),
113 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID1),
114 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID1),
115 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID1),
116 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID1),
117 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID1),
118 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID1),
119 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID1),
120 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID1),
121 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID2),
122 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID2),
123 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID2),
124 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID2),
125 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID2),
126 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID2),
127 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID2),
128 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID2),
129 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID3),
130 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID3),
131 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID3),
132 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID3),
133 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID3),
134 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID3),
135 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID3),
136 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID3),
137 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CIF_CSI_INTEN),
138 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CIF_CSI_INTSTAT),
139 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID0_1),
140 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID2_3),
141 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CIF_CSI_LINE_CNT_ID0_1),
142 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CIF_CSI_LINE_CNT_ID2_3),
143 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CIF_CSI_ID0_CROP_START),
144 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CIF_CSI_ID1_CROP_START),
145 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CIF_CSI_ID2_CROP_START),
146 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CIF_CSI_ID3_CROP_START),
147 [CIF_REG_MMU_DTE_ADDR] = CIF_REG(CIF_MMU_DTE_ADDR),
148 [CIF_REG_MMU_STATUS] = CIF_REG(CIF_MMU_DTE_ADDR),
149 [CIF_REG_MMU_COMMAND] = CIF_REG(CIF_MMU_COMMAND),
150 [CIF_REG_MMU_PAGE_FAULT_ADDR] = CIF_REG(CIF_MMU_PAGE_FAULT_ADDR),
151 [CIF_REG_MMU_ZAP_ONE_LINE] = CIF_REG(CIF_MMU_ZAP_ONE_LINE),
152 [CIF_REG_MMU_INT_RAWSTAT] = CIF_REG(CIF_MMU_INT_RAWSTAT),
153 [CIF_REG_MMU_INT_CLEAR] = CIF_REG(CIF_MMU_INT_CLEAR),
154 [CIF_REG_MMU_INT_MASK] = CIF_REG(CIF_MMU_INT_MASK),
155 [CIF_REG_MMU_INT_STATUS] = CIF_REG(CIF_MMU_INT_STATUS),
156 [CIF_REG_MMU_AUTO_GATING] = CIF_REG(CIF_MMU_AUTO_GATING),
157 };
158
159 static const char * const rk1808_cif_clks[] = {
160 "aclk_cif",
161 "dclk_cif",
162 "hclk_cif",
163 "sclk_cif_out",
164 /* "pclk_csi2host" */
165 };
166
167 static const char * const rk1808_cif_rsts[] = {
168 "rst_cif_a",
169 "rst_cif_h",
170 "rst_cif_i",
171 "rst_cif_d",
172 "rst_cif_pclkin",
173 };
174
175 static const struct cif_reg rk3128_cif_regs[] = {
176 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
177 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
178 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
179 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
180 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
181 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
182 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
183 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
184 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
185 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
186 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
187 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
188 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
189 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
190 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
191 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
192 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
193 };
194
195 static const char * const rk3128_cif_clks[] = {
196 "aclk_cif",
197 "hclk_cif",
198 "sclk_cif_out",
199 };
200
201 static const char * const rk3128_cif_rsts[] = {
202 "rst_cif",
203 };
204
205 static const struct cif_reg rk3288_cif_regs[] = {
206 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
207 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
208 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
209 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
210 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
211 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
212 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
213 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
214 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
215 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
216 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
217 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
218 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
219 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
220 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
221 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
222 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
223 };
224
225 static const char * const rk3288_cif_clks[] = {
226 "aclk_cif0",
227 "hclk_cif0",
228 "cif0_in",
229 };
230
231 static const char * const rk3288_cif_rsts[] = {
232 "rst_cif",
233 };
234
235 static const struct cif_reg rk3328_cif_regs[] = {
236 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
237 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
238 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
239 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
240 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
241 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
242 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
243 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
244 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
245 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
246 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
247 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
248 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
249 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
250 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
251 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
252 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
253 };
254
255 static const char * const rk3328_cif_clks[] = {
256 "aclk_cif",
257 "hclk_cif",
258 };
259
260 static const char * const rk3328_cif_rsts[] = {
261 "rst_cif_a",
262 "rst_cif_p",
263 "rst_cif_h",
264 };
265
266 static const char * const rk3368_cif_clks[] = {
267 "pclk_cif",
268 "aclk_cif0",
269 "hclk_cif0",
270 "cif0_in",
271 };
272
273 static const char * const rk3368_cif_rsts[] = {
274 "rst_cif",
275 };
276
277 static const struct cif_reg rk3368_cif_regs[] = {
278 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
279 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
280 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
281 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
282 [CIF_REG_DVP_DMA_IDLE_REQ] = CIF_REG(CIF_DMA_IDLE_REQ),
283 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
284 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
285 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
286 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
287 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
288 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
289 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
290 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
291 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
292 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
293 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
294 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
295 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
296 };
297
298 static const char * const rv1126_cif_clks[] = {
299 "aclk_cif",
300 "hclk_cif",
301 "dclk_cif",
302 };
303
304 static const char * const rv1126_cif_rsts[] = {
305 "rst_cif_a",
306 "rst_cif_h",
307 "rst_cif_d",
308 "rst_cif_p",
309 "rst_cif_i",
310 "rst_cif_rx_p",
311 };
312
313 static const struct cif_reg rv1126_cif_regs[] = {
314 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
315 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
316 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
317 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
318 [CIF_REG_DVP_MULTI_ID] = CIF_REG(CIF_MULTI_ID),
319 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
320 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
321 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
322 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
323 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
324 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
325 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(CIF_LINE_INT_NUM),
326 [CIF_REG_DVP_LINE_CNT] = CIF_REG(CIF_LINE_CNT),
327 [CIF_REG_DVP_CROP] = CIF_REG(RV1126_CIF_CROP),
328 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(RV1126_CIF_FRAME_STATUS),
329 [CIF_REG_DVP_CUR_DST] = CIF_REG(RV1126_CIF_CUR_DST),
330 [CIF_REG_DVP_LAST_LINE] = CIF_REG(RV1126_CIF_LAST_LINE),
331 [CIF_REG_DVP_LAST_PIX] = CIF_REG(RV1126_CIF_LAST_PIX),
332 [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(CIF_FRM0_ADDR_Y_ID1),
333 [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(CIF_FRM0_ADDR_UV_ID1),
334 [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(CIF_FRM1_ADDR_Y_ID1),
335 [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(CIF_FRM1_ADDR_UV_ID1),
336 [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(CIF_FRM0_ADDR_Y_ID2),
337 [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(CIF_FRM0_ADDR_UV_ID2),
338 [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(CIF_FRM1_ADDR_Y_ID2),
339 [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(CIF_FRM1_ADDR_UV_ID2),
340 [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(CIF_FRM0_ADDR_Y_ID3),
341 [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(CIF_FRM0_ADDR_UV_ID3),
342 [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(CIF_FRM1_ADDR_Y_ID3),
343 [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(CIF_FRM1_ADDR_UV_ID3),
344 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CIF_CSI_ID0_CTRL0),
345 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CIF_CSI_ID0_CTRL1),
346 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CIF_CSI_ID1_CTRL0),
347 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CIF_CSI_ID1_CTRL1),
348 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CIF_CSI_ID2_CTRL0),
349 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CIF_CSI_ID2_CTRL1),
350 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CIF_CSI_ID3_CTRL0),
351 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CIF_CSI_ID3_CTRL1),
352 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CIF_CSI_MIPI_LVDS_CTRL),
353 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID0),
354 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID0),
355 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID0),
356 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID0),
357 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID0),
358 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID0),
359 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID0),
360 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID0),
361 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID1),
362 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID1),
363 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID1),
364 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID1),
365 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID1),
366 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID1),
367 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID1),
368 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID1),
369 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID2),
370 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID2),
371 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID2),
372 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID2),
373 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID2),
374 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID2),
375 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID2),
376 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID2),
377 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID3),
378 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID3),
379 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID3),
380 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID3),
381 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID3),
382 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID3),
383 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID3),
384 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID3),
385 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CIF_CSI_INTEN),
386 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CIF_CSI_INTSTAT),
387 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID0_1),
388 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID2_3),
389 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CIF_CSI_LINE_CNT_ID0_1),
390 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CIF_CSI_LINE_CNT_ID2_3),
391 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CIF_CSI_ID0_CROP_START),
392 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CIF_CSI_ID1_CROP_START),
393 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CIF_CSI_ID2_CROP_START),
394 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CIF_CSI_ID3_CROP_START),
395 [CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0),
396 [CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0),
397 [CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0),
398 [CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0),
399 [CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1),
400 [CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1),
401 [CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1),
402 [CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1),
403 [CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2),
404 [CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2),
405 [CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2),
406 [CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2),
407 [CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3),
408 [CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3),
409 [CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3),
410 [CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3),
411 [CIF_REG_Y_STAT_CONTROL] = CIF_REG(CIF_Y_STAT_CONTROL),
412 [CIF_REG_Y_STAT_VALUE] = CIF_REG(CIF_Y_STAT_VALUE),
413 [CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_CIFIO_CON),
414 };
415
416 static const char * const rv1126_cif_lite_clks[] = {
417 "aclk_cif_lite",
418 "hclk_cif_lite",
419 "dclk_cif_lite",
420 };
421
422 static const char * const rv1126_cif_lite_rsts[] = {
423 "rst_cif_lite_a",
424 "rst_cif_lite_h",
425 "rst_cif_lite_d",
426 "rst_cif_lite_rx_p",
427 };
428
429 static const struct cif_reg rv1126_cif_lite_regs[] = {
430 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CIF_CSI_ID0_CTRL0),
431 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CIF_CSI_ID0_CTRL1),
432 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CIF_CSI_ID1_CTRL0),
433 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CIF_CSI_ID1_CTRL1),
434 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CIF_CSI_ID2_CTRL0),
435 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CIF_CSI_ID2_CTRL1),
436 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CIF_CSI_ID3_CTRL0),
437 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CIF_CSI_ID3_CTRL1),
438 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CIF_CSI_MIPI_LVDS_CTRL),
439 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID0),
440 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID0),
441 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID0),
442 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID0),
443 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID1),
444 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID1),
445 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID1),
446 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID1),
447 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID2),
448 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID2),
449 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID2),
450 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID2),
451 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID3),
452 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID3),
453 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID3),
454 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID3),
455 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CIF_CSI_INTEN),
456 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CIF_CSI_INTSTAT),
457 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID0_1),
458 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID2_3),
459 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CIF_CSI_LINE_CNT_ID0_1),
460 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CIF_CSI_LINE_CNT_ID2_3),
461 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CIF_CSI_ID0_CROP_START),
462 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CIF_CSI_ID1_CROP_START),
463 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CIF_CSI_ID2_CROP_START),
464 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CIF_CSI_ID3_CROP_START),
465 [CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0),
466 [CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0),
467 [CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0),
468 [CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0),
469 [CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1),
470 [CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1),
471 [CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1),
472 [CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1),
473 [CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2),
474 [CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2),
475 [CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2),
476 [CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2),
477 [CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3),
478 [CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3),
479 [CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3),
480 [CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3),
481 [CIF_REG_Y_STAT_CONTROL] = CIF_REG(CIF_Y_STAT_CONTROL),
482 [CIF_REG_Y_STAT_VALUE] = CIF_REG(CIF_Y_STAT_VALUE),
483 };
484
485 static const char * const rk3568_cif_clks[] = {
486 "aclk_cif",
487 "hclk_cif",
488 "dclk_cif",
489 "iclk_cif_g",
490 };
491
492 static const char * const rk3568_cif_rsts[] = {
493 "rst_cif_a",
494 "rst_cif_h",
495 "rst_cif_d",
496 "rst_cif_p",
497 "rst_cif_i",
498 };
499
500 static const struct cif_reg rk3568_cif_regs[] = {
501 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
502 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
503 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
504 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
505 [CIF_REG_DVP_MULTI_ID] = CIF_REG(CIF_MULTI_ID),
506 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
507 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
508 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
509 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
510 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
511 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
512 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(CIF_LINE_INT_NUM),
513 [CIF_REG_DVP_LINE_CNT] = CIF_REG(CIF_LINE_CNT),
514 [CIF_REG_DVP_CROP] = CIF_REG(RV1126_CIF_CROP),
515 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(RK3568_CIF_FIFO_ENTRY),
516 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(RV1126_CIF_FRAME_STATUS),
517 [CIF_REG_DVP_CUR_DST] = CIF_REG(RV1126_CIF_CUR_DST),
518 [CIF_REG_DVP_LAST_LINE] = CIF_REG(RV1126_CIF_LAST_LINE),
519 [CIF_REG_DVP_LAST_PIX] = CIF_REG(RV1126_CIF_LAST_PIX),
520 [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(CIF_FRM0_ADDR_Y_ID1),
521 [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(CIF_FRM0_ADDR_UV_ID1),
522 [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(CIF_FRM1_ADDR_Y_ID1),
523 [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(CIF_FRM1_ADDR_UV_ID1),
524 [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(CIF_FRM0_ADDR_Y_ID2),
525 [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(CIF_FRM0_ADDR_UV_ID2),
526 [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(CIF_FRM1_ADDR_Y_ID2),
527 [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(CIF_FRM1_ADDR_UV_ID2),
528 [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(CIF_FRM0_ADDR_Y_ID3),
529 [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(CIF_FRM0_ADDR_UV_ID3),
530 [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(CIF_FRM1_ADDR_Y_ID3),
531 [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(CIF_FRM1_ADDR_UV_ID3),
532 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CIF_CSI_ID0_CTRL0),
533 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CIF_CSI_ID0_CTRL1),
534 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CIF_CSI_ID1_CTRL0),
535 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CIF_CSI_ID1_CTRL1),
536 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CIF_CSI_ID2_CTRL0),
537 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CIF_CSI_ID2_CTRL1),
538 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CIF_CSI_ID3_CTRL0),
539 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CIF_CSI_ID3_CTRL1),
540 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CIF_CSI_MIPI_LVDS_CTRL),
541 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID0),
542 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID0),
543 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID0),
544 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID0),
545 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID0),
546 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID0),
547 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID0),
548 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID0),
549 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID1),
550 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID1),
551 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID1),
552 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID1),
553 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID1),
554 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID1),
555 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID1),
556 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID1),
557 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID2),
558 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID2),
559 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID2),
560 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID2),
561 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID2),
562 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID2),
563 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID2),
564 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID2),
565 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID3),
566 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID3),
567 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID3),
568 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID3),
569 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID3),
570 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID3),
571 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID3),
572 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID3),
573 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CIF_CSI_INTEN),
574 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CIF_CSI_INTSTAT),
575 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID0_1),
576 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID2_3),
577 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CIF_CSI_LINE_CNT_ID0_1),
578 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CIF_CSI_LINE_CNT_ID2_3),
579 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CIF_CSI_ID0_CROP_START),
580 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CIF_CSI_ID1_CROP_START),
581 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CIF_CSI_ID2_CROP_START),
582 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CIF_CSI_ID3_CROP_START),
583 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CIF_CSI_FRAME_NUM_VC0),
584 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CIF_CSI_FRAME_NUM_VC1),
585 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CIF_CSI_FRAME_NUM_VC2),
586 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CIF_CSI_FRAME_NUM_VC3),
587 [CIF_REG_Y_STAT_CONTROL] = CIF_REG(CIF_Y_STAT_CONTROL),
588 [CIF_REG_Y_STAT_VALUE] = CIF_REG(CIF_Y_STAT_VALUE),
589 [CIF_REG_MMU_DTE_ADDR] = CIF_REG(CIF_MMU_DTE_ADDR),
590 [CIF_REG_MMU_STATUS] = CIF_REG(CIF_MMU_STATUS),
591 [CIF_REG_MMU_COMMAND] = CIF_REG(CIF_MMU_COMMAND),
592 [CIF_REG_MMU_PAGE_FAULT_ADDR] = CIF_REG(CIF_MMU_PAGE_FAULT_ADDR),
593 [CIF_REG_MMU_ZAP_ONE_LINE] = CIF_REG(CIF_MMU_ZAP_ONE_LINE),
594 [CIF_REG_MMU_INT_RAWSTAT] = CIF_REG(CIF_MMU_INT_RAWSTAT),
595 [CIF_REG_MMU_INT_CLEAR] = CIF_REG(CIF_MMU_INT_CLEAR),
596 [CIF_REG_MMU_INT_MASK] = CIF_REG(CIF_MMU_INT_MASK),
597 [CIF_REG_MMU_INT_STATUS] = CIF_REG(CIF_MMU_INT_STATUS),
598 [CIF_REG_MMU_AUTO_GATING] = CIF_REG(CIF_MMU_AUTO_GATING),
599 [CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_VI_CON0),
600 [CIF_REG_GRF_CIFIO_CON1] = CIF_REG(CIF_GRF_VI_CON1),
601 };
602
603 static const char * const rk3588_cif_clks[] = {
604 "aclk_cif",
605 "hclk_cif",
606 "dclk_cif",
607 };
608
609 static const char * const rk3588_cif_rsts[] = {
610 "rst_cif_a",
611 "rst_cif_h",
612 "rst_cif_d",
613 };
614
615 static const struct cif_reg rk3588_cif_regs[] = {
616 [CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
617 [CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
618 [CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
619 [CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
620 [CIF_REG_DVP_MULTI_ID] = CIF_REG(DVP_MULTI_ID),
621 [CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
622 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
623 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
624 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
625 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
626 [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(DVP_FRM0_ADDR_Y_ID1),
627 [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(DVP_FRM0_ADDR_UV_ID1),
628 [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(DVP_FRM1_ADDR_Y_ID1),
629 [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(DVP_FRM1_ADDR_UV_ID1),
630 [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(DVP_FRM0_ADDR_Y_ID2),
631 [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(DVP_FRM0_ADDR_UV_ID2),
632 [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(DVP_FRM1_ADDR_Y_ID2),
633 [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(DVP_FRM1_ADDR_UV_ID2),
634 [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(DVP_FRM0_ADDR_Y_ID3),
635 [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(DVP_FRM0_ADDR_UV_ID3),
636 [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(DVP_FRM1_ADDR_Y_ID3),
637 [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(DVP_FRM1_ADDR_UV_ID3),
638 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
639 [CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
640 [CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
641 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
642 [CIF_REG_DVP_LINE_INT_NUM1] = CIF_REG(DVP_LINE_INT_NUM_23),
643 [CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_INT_NUM_01),
644 [CIF_REG_DVP_LINE_CNT1] = CIF_REG(DVP_LINE_INT_NUM_23),
645
646 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
647 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
648 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
649 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
650 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
651 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
652 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
653 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
654 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
655 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
656 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
657 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
658 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
659 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
660 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
661 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
662 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
663 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
664 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
665 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
666 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
667 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
668 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
669 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
670 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
671 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
672 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
673 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
674 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
675 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
676 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
677 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
678 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
679 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
680 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
681 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
682 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
683 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
684 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
685 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
686 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
687 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
688 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
689 [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
690 [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
691 [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
692 [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
693 [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
694
695 [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
696 [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
697 [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
698
699 [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
700 [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
701 [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
702 [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
703 [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
704 [CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
705 [CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
706 [CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
707 [CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
708 [CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
709 [CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
710 [CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
711 [CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
712 [CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
713 [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
714 [CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
715 [CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
716 [CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
717 [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
718 [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
719 [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
720 [CIF_REG_TOISP1_CTRL] = CIF_REG(TOISP1_CH_CTRL),
721 [CIF_REG_TOISP1_SIZE] = CIF_REG(TOISP1_CROP_SIZE),
722 [CIF_REG_TOISP1_CROP] = CIF_REG(TOISP1_CROP),
723 [CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_SOC_CON2),
724 };
725
726 static const struct rkcif_hw_match_data px30_cif_match_data = {
727 .chip_id = CHIP_PX30_CIF,
728 .clks = px30_cif_clks,
729 .clks_num = ARRAY_SIZE(px30_cif_clks),
730 .rsts = px30_cif_rsts,
731 .rsts_num = ARRAY_SIZE(px30_cif_rsts),
732 .cif_regs = px30_cif_regs,
733 };
734
735 static const struct rkcif_hw_match_data rk1808_cif_match_data = {
736 .chip_id = CHIP_RK1808_CIF,
737 .clks = rk1808_cif_clks,
738 .clks_num = ARRAY_SIZE(rk1808_cif_clks),
739 .rsts = rk1808_cif_rsts,
740 .rsts_num = ARRAY_SIZE(rk1808_cif_rsts),
741 .cif_regs = rk1808_cif_regs,
742 };
743
744 static const struct rkcif_hw_match_data rk3128_cif_match_data = {
745 .chip_id = CHIP_RK3128_CIF,
746 .clks = rk3128_cif_clks,
747 .clks_num = ARRAY_SIZE(rk3128_cif_clks),
748 .rsts = rk3128_cif_rsts,
749 .rsts_num = ARRAY_SIZE(rk3128_cif_rsts),
750 .cif_regs = rk3128_cif_regs,
751 };
752
753 static const struct rkcif_hw_match_data rk3288_cif_match_data = {
754 .chip_id = CHIP_RK3288_CIF,
755 .clks = rk3288_cif_clks,
756 .clks_num = ARRAY_SIZE(rk3288_cif_clks),
757 .rsts = rk3288_cif_rsts,
758 .rsts_num = ARRAY_SIZE(rk3288_cif_rsts),
759 .cif_regs = rk3288_cif_regs,
760 };
761
762 static const struct rkcif_hw_match_data rk3328_cif_match_data = {
763 .chip_id = CHIP_RK3328_CIF,
764 .clks = rk3328_cif_clks,
765 .clks_num = ARRAY_SIZE(rk3328_cif_clks),
766 .rsts = rk3328_cif_rsts,
767 .rsts_num = ARRAY_SIZE(rk3328_cif_rsts),
768 .cif_regs = rk3328_cif_regs,
769 };
770
771 static const struct rkcif_hw_match_data rk3368_cif_match_data = {
772 .chip_id = CHIP_RK3368_CIF,
773 .clks = rk3368_cif_clks,
774 .clks_num = ARRAY_SIZE(rk3368_cif_clks),
775 .rsts = rk3368_cif_rsts,
776 .rsts_num = ARRAY_SIZE(rk3368_cif_rsts),
777 .cif_regs = rk3368_cif_regs,
778 };
779
780 static const struct rkcif_hw_match_data rv1126_cif_match_data = {
781 .chip_id = CHIP_RV1126_CIF,
782 .clks = rv1126_cif_clks,
783 .clks_num = ARRAY_SIZE(rv1126_cif_clks),
784 .rsts = rv1126_cif_rsts,
785 .rsts_num = ARRAY_SIZE(rv1126_cif_rsts),
786 .cif_regs = rv1126_cif_regs,
787 };
788
789 static const struct rkcif_hw_match_data rv1126_cif_lite_match_data = {
790 .chip_id = CHIP_RV1126_CIF_LITE,
791 .clks = rv1126_cif_lite_clks,
792 .clks_num = ARRAY_SIZE(rv1126_cif_lite_clks),
793 .rsts = rv1126_cif_lite_rsts,
794 .rsts_num = ARRAY_SIZE(rv1126_cif_lite_rsts),
795 .cif_regs = rv1126_cif_lite_regs,
796 };
797
798 static const struct rkcif_hw_match_data rk3568_cif_match_data = {
799 .chip_id = CHIP_RK3568_CIF,
800 .clks = rk3568_cif_clks,
801 .clks_num = ARRAY_SIZE(rk3568_cif_clks),
802 .rsts = rk3568_cif_rsts,
803 .rsts_num = ARRAY_SIZE(rk3568_cif_rsts),
804 .cif_regs = rk3568_cif_regs,
805 };
806
807 static const struct rkcif_hw_match_data rk3588_cif_match_data = {
808 .chip_id = CHIP_RK3588_CIF,
809 .clks = rk3588_cif_clks,
810 .clks_num = ARRAY_SIZE(rk3588_cif_clks),
811 .rsts = rk3588_cif_rsts,
812 .rsts_num = ARRAY_SIZE(rk3588_cif_rsts),
813 .cif_regs = rk3588_cif_regs,
814 };
815
816 static const struct of_device_id rkcif_plat_of_match[] = {
817 {
818 .compatible = "rockchip,px30-cif",
819 .data = &px30_cif_match_data,
820 },
821 {
822 .compatible = "rockchip,rk1808-cif",
823 .data = &rk1808_cif_match_data,
824 },
825 {
826 .compatible = "rockchip,rk3128-cif",
827 .data = &rk3128_cif_match_data,
828 },
829 {
830 .compatible = "rockchip,rk3288-cif",
831 .data = &rk3288_cif_match_data,
832 },
833 {
834 .compatible = "rockchip,rk3328-cif",
835 .data = &rk3328_cif_match_data,
836 },
837 {
838 .compatible = "rockchip,rk3368-cif",
839 .data = &rk3368_cif_match_data,
840 },
841 {
842 .compatible = "rockchip,rk3568-cif",
843 .data = &rk3568_cif_match_data,
844 },
845 {
846 .compatible = "rockchip,rk3588-cif",
847 .data = &rk3588_cif_match_data,
848 },
849 {
850 .compatible = "rockchip,rv1126-cif",
851 .data = &rv1126_cif_match_data,
852 },
853 {
854 .compatible = "rockchip,rv1126-cif-lite",
855 .data = &rv1126_cif_lite_match_data,
856 },
857 {},
858 };
859
rkcif_irq_handler(int irq,void * ctx)860 static irqreturn_t rkcif_irq_handler(int irq, void *ctx)
861 {
862 struct device *dev = ctx;
863 struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
864 unsigned int intstat_glb = 0;
865 int i;
866
867 if (cif_hw->chip_id == CHIP_RK3588_CIF)
868 intstat_glb = rkcif_irq_global(cif_hw->cif_dev[0]);
869 for (i = 0; i < cif_hw->dev_num; i++) {
870 if (cif_hw->cif_dev[i]->isr_hdl) {
871 cif_hw->cif_dev[i]->isr_hdl(irq, cif_hw->cif_dev[i]);
872 if (cif_hw->chip_id == CHIP_RK3588_CIF && intstat_glb)
873 rkcif_irq_handle_toisp(cif_hw->cif_dev[i], intstat_glb);
874 }
875 }
876
877 return IRQ_HANDLED;
878 }
879
rkcif_disable_sys_clk(struct rkcif_hw * cif_hw)880 void rkcif_disable_sys_clk(struct rkcif_hw *cif_hw)
881 {
882 int i;
883
884 for (i = cif_hw->clk_size - 1; i >= 0; i--)
885 clk_disable_unprepare(cif_hw->clks[i]);
886 }
887
rkcif_enable_sys_clk(struct rkcif_hw * cif_hw)888 int rkcif_enable_sys_clk(struct rkcif_hw *cif_hw)
889 {
890 int i, ret = -EINVAL;
891
892 for (i = 0; i < cif_hw->clk_size; i++) {
893 ret = clk_prepare_enable(cif_hw->clks[i]);
894
895 if (ret < 0)
896 goto err;
897 }
898
899 write_cif_reg_and(cif_hw->base_addr, CIF_CSI_INTEN, 0x0);
900 return 0;
901
902 err:
903 for (--i; i >= 0; --i)
904 clk_disable_unprepare(cif_hw->clks[i]);
905
906 return ret;
907 }
908
rkcif_iommu_cleanup(struct rkcif_hw * cif_hw)909 static void rkcif_iommu_cleanup(struct rkcif_hw *cif_hw)
910 {
911 if (cif_hw->iommu_en)
912 rockchip_iommu_disable(cif_hw->dev);
913 }
914
rkcif_iommu_enable(struct rkcif_hw * cif_hw)915 static void rkcif_iommu_enable(struct rkcif_hw *cif_hw)
916 {
917 if (cif_hw->iommu_en)
918 rockchip_iommu_enable(cif_hw->dev);
919 }
920
is_iommu_enable(struct device * dev)921 static inline bool is_iommu_enable(struct device *dev)
922 {
923 struct device_node *iommu;
924
925 iommu = of_parse_phandle(dev->of_node, "iommus", 0);
926 if (!iommu) {
927 dev_info(dev, "no iommu attached, using non-iommu buffers\n");
928 return false;
929 } else if (!of_device_is_available(iommu)) {
930 dev_info(dev, "iommu is disabled, using non-iommu buffers\n");
931 of_node_put(iommu);
932 return false;
933 }
934 of_node_put(iommu);
935
936 return true;
937 }
938
rkcif_hw_soft_reset(struct rkcif_hw * cif_hw,bool is_rst_iommu)939 void rkcif_hw_soft_reset(struct rkcif_hw *cif_hw, bool is_rst_iommu)
940 {
941 unsigned int i;
942
943 if (cif_hw->iommu_en && is_rst_iommu)
944 rkcif_iommu_cleanup(cif_hw);
945
946 for (i = 0; i < ARRAY_SIZE(cif_hw->cif_rst); i++)
947 if (cif_hw->cif_rst[i])
948 reset_control_assert(cif_hw->cif_rst[i]);
949 udelay(5);
950 for (i = 0; i < ARRAY_SIZE(cif_hw->cif_rst); i++)
951 if (cif_hw->cif_rst[i])
952 reset_control_deassert(cif_hw->cif_rst[i]);
953
954 if (cif_hw->iommu_en && is_rst_iommu)
955 rkcif_iommu_enable(cif_hw);
956 }
957
rkcif_plat_hw_probe(struct platform_device * pdev)958 static int rkcif_plat_hw_probe(struct platform_device *pdev)
959 {
960 const struct of_device_id *match;
961 struct device_node *node = pdev->dev.of_node;
962 struct device *dev = &pdev->dev;
963 struct device_node *np = dev->of_node;
964 struct rkcif_hw *cif_hw;
965 struct rkcif_device *cif_dev;
966 const struct rkcif_hw_match_data *data;
967 struct resource *res;
968 int i, ret, irq;
969 bool is_mem_reserved = false;
970
971 match = of_match_node(rkcif_plat_of_match, node);
972 if (IS_ERR(match))
973 return PTR_ERR(match);
974 data = match->data;
975
976 cif_hw = devm_kzalloc(dev, sizeof(*cif_hw), GFP_KERNEL);
977 if (!cif_hw)
978 return -ENOMEM;
979
980 dev_set_drvdata(dev, cif_hw);
981 cif_hw->dev = dev;
982
983 irq = platform_get_irq(pdev, 0);
984 if (irq < 0)
985 return irq;
986
987 ret = devm_request_irq(dev, irq, rkcif_irq_handler,
988 IRQF_SHARED,
989 dev_driver_string(dev), dev);
990 if (ret < 0) {
991 dev_err(dev, "request irq failed: %d\n", ret);
992 return ret;
993 }
994
995 cif_hw->irq = irq;
996 cif_hw->match_data = data;
997 cif_hw->chip_id = data->chip_id;
998 cif_hw->sync_config.is_attach = false;
999 cif_hw->sync_config.mode = RKCIF_NOSYNC_MODE;
1000 if (data->chip_id >= CHIP_RK1808_CIF) {
1001 res = platform_get_resource_byname(pdev,
1002 IORESOURCE_MEM,
1003 "cif_regs");
1004 cif_hw->base_addr = devm_ioremap_resource(dev, res);
1005 if (PTR_ERR(cif_hw->base_addr) == -EBUSY) {
1006 resource_size_t offset = res->start;
1007 resource_size_t size = resource_size(res);
1008
1009 cif_hw->base_addr = devm_ioremap(dev, offset, size);
1010 if (IS_ERR(cif_hw->base_addr)) {
1011 dev_err(dev, "ioremap failed\n");
1012 return PTR_ERR(cif_hw->base_addr);
1013 }
1014 }
1015 } else {
1016 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1017 cif_hw->base_addr = devm_ioremap_resource(dev, res);
1018 if (IS_ERR(cif_hw->base_addr))
1019 return PTR_ERR(cif_hw->base_addr);
1020 }
1021
1022 cif_hw->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1023 if (IS_ERR(cif_hw->grf))
1024 dev_warn(dev, "unable to get rockchip,grf\n");
1025
1026 if (data->clks_num > RKCIF_MAX_BUS_CLK ||
1027 data->rsts_num > RKCIF_MAX_RESET) {
1028 dev_err(dev, "out of range: clks(%d %d) rsts(%d %d)\n",
1029 data->clks_num, RKCIF_MAX_BUS_CLK,
1030 data->rsts_num, RKCIF_MAX_RESET);
1031 return -EINVAL;
1032 }
1033
1034 for (i = 0; i < data->clks_num; i++) {
1035 struct clk *clk = devm_clk_get(dev, data->clks[i]);
1036
1037 if (IS_ERR(clk)) {
1038 dev_err(dev, "failed to get %s\n", data->clks[i]);
1039 return PTR_ERR(clk);
1040 }
1041 cif_hw->clks[i] = clk;
1042 }
1043 cif_hw->clk_size = data->clks_num;
1044
1045 for (i = 0; i < data->rsts_num; i++) {
1046 struct reset_control *rst = NULL;
1047
1048 if (data->rsts[i])
1049 rst = devm_reset_control_get(dev, data->rsts[i]);
1050 if (IS_ERR(rst)) {
1051 dev_err(dev, "failed to get %s\n", data->rsts[i]);
1052 return PTR_ERR(rst);
1053 }
1054 cif_hw->cif_rst[i] = rst;
1055 }
1056
1057 cif_hw->cif_regs = data->cif_regs;
1058
1059 cif_hw->is_dma_contig = true;
1060 cif_hw->is_dma_sg_ops = false;
1061 mutex_init(&cif_hw->dev_lock);
1062
1063 cif_hw->iommu_en = is_iommu_enable(dev);
1064 ret = of_reserved_mem_device_init(dev);
1065 if (ret) {
1066 is_mem_reserved = false;
1067 if (!cif_hw->iommu_en)
1068 dev_info(dev, "No reserved memory region assign to CIF\n");
1069 else
1070 cif_hw->is_dma_contig = false;
1071 }
1072 if (is_mem_reserved) {
1073 cif_hw->mem_ops = &vb2_rdma_sg_memops;
1074 cif_hw->is_dma_sg_ops = true;
1075 } else if (cif_hw->iommu_en) {
1076 cif_hw->mem_ops = &vb2_dma_sg_memops;
1077 cif_hw->is_dma_sg_ops = true;
1078 } else {
1079 cif_hw->mem_ops = &vb2_dma_contig_memops;
1080 }
1081
1082 if (data->chip_id < CHIP_RK1808_CIF) {
1083 cif_dev = devm_kzalloc(dev, sizeof(*cif_dev), GFP_KERNEL);
1084 if (!cif_dev)
1085 return -ENOMEM;
1086
1087 cif_dev->dev = dev;
1088 cif_dev->hw_dev = cif_hw;
1089 cif_dev->chip_id = cif_hw->chip_id;
1090 cif_hw->cif_dev[0] = cif_dev;
1091 cif_hw->dev_num = 1;
1092 ret = rkcif_plat_init(cif_dev, node, RKCIF_DVP);
1093 if (ret)
1094 return ret;
1095 }
1096
1097 rkcif_hw_soft_reset(cif_hw, true);
1098
1099 mutex_init(&cif_hw->dev_lock);
1100
1101 pm_runtime_enable(&pdev->dev);
1102
1103 if (data->chip_id >= CHIP_RK1808_CIF &&
1104 data->chip_id != CHIP_RV1126_CIF_LITE) {
1105 platform_driver_register(&rkcif_plat_drv);
1106 platform_driver_register(&rkcif_subdev_driver);
1107 }
1108
1109 return 0;
1110 }
1111
rkcif_plat_remove(struct platform_device * pdev)1112 static int rkcif_plat_remove(struct platform_device *pdev)
1113 {
1114 struct rkcif_hw *cif_hw = platform_get_drvdata(pdev);
1115
1116 pm_runtime_disable(&pdev->dev);
1117 if (cif_hw->iommu_en)
1118 rkcif_iommu_cleanup(cif_hw);
1119
1120 mutex_destroy(&cif_hw->dev_lock);
1121 if (cif_hw->chip_id < CHIP_RK1808_CIF)
1122 rkcif_plat_uninit(cif_hw->cif_dev[0]);
1123
1124 return 0;
1125 }
1126
rkcif_runtime_suspend(struct device * dev)1127 static int __maybe_unused rkcif_runtime_suspend(struct device *dev)
1128 {
1129 struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1130
1131 rkcif_disable_sys_clk(cif_hw);
1132
1133 return pinctrl_pm_select_sleep_state(dev);
1134 }
1135
rkcif_runtime_resume(struct device * dev)1136 static int __maybe_unused rkcif_runtime_resume(struct device *dev)
1137 {
1138 struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1139 int ret;
1140
1141 ret = pinctrl_pm_select_default_state(dev);
1142 if (ret < 0)
1143 return ret;
1144 rkcif_enable_sys_clk(cif_hw);
1145
1146 return 0;
1147 }
1148
1149 static const struct dev_pm_ops rkcif_plat_pm_ops = {
1150 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1151 pm_runtime_force_resume)
1152 SET_RUNTIME_PM_OPS(rkcif_runtime_suspend, rkcif_runtime_resume, NULL)
1153 };
1154
1155 static struct platform_driver rkcif_hw_plat_drv = {
1156 .driver = {
1157 .name = RKCIF_HW_DRIVER_NAME,
1158 .of_match_table = of_match_ptr(rkcif_plat_of_match),
1159 .pm = &rkcif_plat_pm_ops,
1160 },
1161 .probe = rkcif_plat_hw_probe,
1162 .remove = rkcif_plat_remove,
1163 };
1164
rk_cif_plat_drv_init(void)1165 static int __init rk_cif_plat_drv_init(void)
1166 {
1167 int ret;
1168
1169 ret = platform_driver_register(&rkcif_hw_plat_drv);
1170 if (ret)
1171 return ret;
1172 return rkcif_csi2_plat_drv_init();
1173 }
1174
rk_cif_plat_drv_exit(void)1175 static void __exit rk_cif_plat_drv_exit(void)
1176 {
1177 platform_driver_unregister(&rkcif_hw_plat_drv);
1178 rkcif_csi2_plat_drv_exit();
1179 }
1180
1181 module_init(rk_cif_plat_drv_init);
1182 module_exit(rk_cif_plat_drv_exit);
1183
1184 MODULE_AUTHOR("Rockchip Camera/ISP team");
1185 MODULE_DESCRIPTION("Rockchip CIF platform driver");
1186 MODULE_LICENSE("GPL v2");
1187